arch/powerpc/include/asm/spu.h

136

void (* wbox_callback)(struct spu *spu);

arch/powerpc/include/asm/spu.h

137

void (* ibox_callback)(struct spu *spu);

arch/powerpc/include/asm/spu.h

138

void (* stop_callback)(struct spu *spu, int irq);

arch/powerpc/include/asm/spu.h

139

void (* mfc_callback)(struct spu *spu);

arch/powerpc/include/asm/spu.h

190

void spu_init_channels(struct spu *spu);

arch/powerpc/include/asm/spu.h

191

void spu_irq_setaffinity(struct spu *spu, int cpu);

arch/powerpc/include/asm/spu.h

193

void spu_setup_kernel_slbs(struct spu *spu, struct spu_lscsa *lscsa,

arch/powerpc/include/asm/spu.h

196

extern void spu_invalidate_slbs(struct spu *spu);

arch/powerpc/include/asm/spu.h

197

extern void spu_associate_mm(struct spu *spu, struct mm_struct *mm);

arch/powerpc/include/asm/spu_priv1.h

101

spu_priv1_ops->mfc_dsisr_set(spu, dsisr);

arch/powerpc/include/asm/spu_priv1.h

105

spu_mfc_sdr_setup (struct spu *spu)

arch/powerpc/include/asm/spu_priv1.h

107

spu_priv1_ops->mfc_sdr_setup(spu);

arch/powerpc/include/asm/spu_priv1.h

111

spu_mfc_sr1_set (struct spu *spu, u64 sr1)

arch/powerpc/include/asm/spu_priv1.h

113

spu_priv1_ops->mfc_sr1_set(spu, sr1);

arch/powerpc/include/asm/spu_priv1.h

117

spu_mfc_sr1_get (struct spu *spu)

arch/powerpc/include/asm/spu_priv1.h

119

return spu_priv1_ops->mfc_sr1_get(spu);

arch/powerpc/include/asm/spu_priv1.h

123

spu_mfc_tclass_id_set (struct spu *spu, u64 tclass_id)

arch/powerpc/include/asm/spu_priv1.h

125

spu_priv1_ops->mfc_tclass_id_set(spu, tclass_id);

arch/powerpc/include/asm/spu_priv1.h

129

spu_mfc_tclass_id_get (struct spu *spu)

arch/powerpc/include/asm/spu_priv1.h

131

return spu_priv1_ops->mfc_tclass_id_get(spu);

arch/powerpc/include/asm/spu_priv1.h

135

spu_tlb_invalidate (struct spu *spu)

arch/powerpc/include/asm/spu_priv1.h

137

spu_priv1_ops->tlb_invalidate(spu);

arch/powerpc/include/asm/spu_priv1.h

14

struct spu;

arch/powerpc/include/asm/spu_priv1.h

141

spu_resource_allocation_groupID_set (struct spu *spu, u64 id)

arch/powerpc/include/asm/spu_priv1.h

143

spu_priv1_ops->resource_allocation_groupID_set(spu, id);

arch/powerpc/include/asm/spu_priv1.h

147

spu_resource_allocation_groupID_get (struct spu *spu)

arch/powerpc/include/asm/spu_priv1.h

149

return spu_priv1_ops->resource_allocation_groupID_get(spu);

arch/powerpc/include/asm/spu_priv1.h

153

spu_resource_allocation_enable_set (struct spu *spu, u64 enable)

arch/powerpc/include/asm/spu_priv1.h

155

spu_priv1_ops->resource_allocation_enable_set(spu, enable);

arch/powerpc/include/asm/spu_priv1.h

159

spu_resource_allocation_enable_get (struct spu *spu)

arch/powerpc/include/asm/spu_priv1.h

161

return spu_priv1_ops->resource_allocation_enable_get(spu);

arch/powerpc/include/asm/spu_priv1.h

168

int (*create_spu)(struct spu *spu, void *data);

arch/powerpc/include/asm/spu_priv1.h

169

int (*destroy_spu)(struct spu *spu);

arch/powerpc/include/asm/spu_priv1.h

184

spu_create_spu (struct spu *spu, void *data)

arch/powerpc/include/asm/spu_priv1.h

186

return spu_management_ops->create_spu(spu, data);

arch/powerpc/include/asm/spu_priv1.h

190

spu_destroy_spu (struct spu *spu)

arch/powerpc/include/asm/spu_priv1.h

192

return spu_management_ops->destroy_spu(spu);

arch/powerpc/include/asm/spu_priv1.h

20

void (*int_mask_and) (struct spu *spu, int class, u64 mask);

arch/powerpc/include/asm/spu_priv1.h

21

void (*int_mask_or) (struct spu *spu, int class, u64 mask);

arch/powerpc/include/asm/spu_priv1.h

22

void (*int_mask_set) (struct spu *spu, int class, u64 mask);

arch/powerpc/include/asm/spu_priv1.h

23

u64 (*int_mask_get) (struct spu *spu, int class);

arch/powerpc/include/asm/spu_priv1.h

24

void (*int_stat_clear) (struct spu *spu, int class, u64 stat);

arch/powerpc/include/asm/spu_priv1.h

25

u64 (*int_stat_get) (struct spu *spu, int class);

arch/powerpc/include/asm/spu_priv1.h

26

void (*cpu_affinity_set) (struct spu *spu, int cpu);

arch/powerpc/include/asm/spu_priv1.h

27

u64 (*mfc_dar_get) (struct spu *spu);

arch/powerpc/include/asm/spu_priv1.h

28

u64 (*mfc_dsisr_get) (struct spu *spu);

arch/powerpc/include/asm/spu_priv1.h

29

void (*mfc_dsisr_set) (struct spu *spu, u64 dsisr);

arch/powerpc/include/asm/spu_priv1.h

30

void (*mfc_sdr_setup) (struct spu *spu);

arch/powerpc/include/asm/spu_priv1.h

31

void (*mfc_sr1_set) (struct spu *spu, u64 sr1);

arch/powerpc/include/asm/spu_priv1.h

32

u64 (*mfc_sr1_get) (struct spu *spu);

arch/powerpc/include/asm/spu_priv1.h

33

void (*mfc_tclass_id_set) (struct spu *spu, u64 tclass_id);

arch/powerpc/include/asm/spu_priv1.h

34

u64 (*mfc_tclass_id_get) (struct spu *spu);

arch/powerpc/include/asm/spu_priv1.h

35

void (*tlb_invalidate) (struct spu *spu);

arch/powerpc/include/asm/spu_priv1.h

36

void (*resource_allocation_groupID_set) (struct spu *spu, u64 id);

arch/powerpc/include/asm/spu_priv1.h

37

u64 (*resource_allocation_groupID_get) (struct spu *spu);

arch/powerpc/include/asm/spu_priv1.h

38

void (*resource_allocation_enable_set) (struct spu *spu, u64 enable);

arch/powerpc/include/asm/spu_priv1.h

39

u64 (*resource_allocation_enable_get) (struct spu *spu);

arch/powerpc/include/asm/spu_priv1.h

45

spu_int_mask_and (struct spu *spu, int class, u64 mask)

arch/powerpc/include/asm/spu_priv1.h

47

spu_priv1_ops->int_mask_and(spu, class, mask);

arch/powerpc/include/asm/spu_priv1.h

51

spu_int_mask_or (struct spu *spu, int class, u64 mask)

arch/powerpc/include/asm/spu_priv1.h

53

spu_priv1_ops->int_mask_or(spu, class, mask);

arch/powerpc/include/asm/spu_priv1.h

57

spu_int_mask_set (struct spu *spu, int class, u64 mask)

arch/powerpc/include/asm/spu_priv1.h

59

spu_priv1_ops->int_mask_set(spu, class, mask);

arch/powerpc/include/asm/spu_priv1.h

63

spu_int_mask_get (struct spu *spu, int class)

arch/powerpc/include/asm/spu_priv1.h

65

return spu_priv1_ops->int_mask_get(spu, class);

arch/powerpc/include/asm/spu_priv1.h

69

spu_int_stat_clear (struct spu *spu, int class, u64 stat)

arch/powerpc/include/asm/spu_priv1.h

71

spu_priv1_ops->int_stat_clear(spu, class, stat);

arch/powerpc/include/asm/spu_priv1.h

75

spu_int_stat_get (struct spu *spu, int class)

arch/powerpc/include/asm/spu_priv1.h

77

return spu_priv1_ops->int_stat_get (spu, class);

arch/powerpc/include/asm/spu_priv1.h

81

spu_cpu_affinity_set (struct spu *spu, int cpu)

arch/powerpc/include/asm/spu_priv1.h

83

spu_priv1_ops->cpu_affinity_set(spu, cpu);

arch/powerpc/include/asm/spu_priv1.h

87

spu_mfc_dar_get (struct spu *spu)

arch/powerpc/include/asm/spu_priv1.h

89

return spu_priv1_ops->mfc_dar_get(spu);

arch/powerpc/include/asm/spu_priv1.h

93

spu_mfc_dsisr_get (struct spu *spu)

arch/powerpc/include/asm/spu_priv1.h

95

return spu_priv1_ops->mfc_dsisr_get(spu);

arch/powerpc/include/asm/spu_priv1.h

99

spu_mfc_dsisr_set (struct spu *spu, u64 dsisr)

arch/powerpc/platforms/cell/spu_base.c

103

void spu_associate_mm(struct spu *spu, struct mm_struct *mm)

arch/powerpc/platforms/cell/spu_base.c

108

spu->mm = mm;

arch/powerpc/platforms/cell/spu_base.c

121

static void spu_restart_dma(struct spu *spu)

arch/powerpc/platforms/cell/spu_base.c

123

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spu_base.c

125

if (!test_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags))

arch/powerpc/platforms/cell/spu_base.c

128

set_bit(SPU_CONTEXT_FAULT_PENDING, &spu->flags);

arch/powerpc/platforms/cell/spu_base.c

133

static inline void spu_load_slb(struct spu *spu, int slbe, struct copro_slb *slb)

arch/powerpc/platforms/cell/spu_base.c

135

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spu_base.c

149

static int __spu_trap_data_seg(struct spu *spu, unsigned long ea)

arch/powerpc/platforms/cell/spu_base.c

154

ret = copro_calculate_slb(spu->mm, ea, &slb);

arch/powerpc/platforms/cell/spu_base.c

158

spu_load_slb(spu, spu->slb_replace, &slb);

arch/powerpc/platforms/cell/spu_base.c

160

spu->slb_replace++;

arch/powerpc/platforms/cell/spu_base.c

161

if (spu->slb_replace >= 8)

arch/powerpc/platforms/cell/spu_base.c

162

spu->slb_replace = 0;

arch/powerpc/platforms/cell/spu_base.c

164

spu_restart_dma(spu);

arch/powerpc/platforms/cell/spu_base.c

165

spu->stats.slb_flt++;

arch/powerpc/platforms/cell/spu_base.c

171

static int __spu_trap_data_map(struct spu *spu, unsigned long ea, u64 dsisr)

arch/powerpc/platforms/cell/spu_base.c

184

spin_unlock(&spu->register_lock);

arch/powerpc/platforms/cell/spu_base.c

188

spin_lock(&spu->register_lock);

arch/powerpc/platforms/cell/spu_base.c

191

spu_restart_dma(spu);

arch/powerpc/platforms/cell/spu_base.c

196

spu->class_1_dar = ea;

arch/powerpc/platforms/cell/spu_base.c

197

spu->class_1_dsisr = dsisr;

arch/powerpc/platforms/cell/spu_base.c

199

spu->stop_callback(spu, 1);

arch/powerpc/platforms/cell/spu_base.c

201

spu->class_1_dar = 0;

arch/powerpc/platforms/cell/spu_base.c

202

spu->class_1_dsisr = 0;

arch/powerpc/platforms/cell/spu_base.c

248

void spu_setup_kernel_slbs(struct spu *spu, struct spu_lscsa *lscsa,

arch/powerpc/platforms/cell/spu_base.c

269

spin_lock_irq(&spu->register_lock);

arch/powerpc/platforms/cell/spu_base.c

272

spu_load_slb(spu, i, &slbs[i]);

arch/powerpc/platforms/cell/spu_base.c

273

spin_unlock_irq(&spu->register_lock);

arch/powerpc/platforms/cell/spu_base.c

280

struct spu *spu;

arch/powerpc/platforms/cell/spu_base.c

283

spu = data;

arch/powerpc/platforms/cell/spu_base.c

285

spin_lock(&spu->register_lock);

arch/powerpc/platforms/cell/spu_base.c

286

mask = spu_int_mask_get(spu, 0);

arch/powerpc/platforms/cell/spu_base.c

287

stat = spu_int_stat_get(spu, 0) & mask;

arch/powerpc/platforms/cell/spu_base.c

289

spu->class_0_pending |= stat;

arch/powerpc/platforms/cell/spu_base.c

290

spu->class_0_dar = spu_mfc_dar_get(spu);

arch/powerpc/platforms/cell/spu_base.c

291

spu->stop_callback(spu, 0);

arch/powerpc/platforms/cell/spu_base.c

292

spu->class_0_pending = 0;

arch/powerpc/platforms/cell/spu_base.c

293

spu->class_0_dar = 0;

arch/powerpc/platforms/cell/spu_base.c

295

spu_int_stat_clear(spu, 0, stat);

arch/powerpc/platforms/cell/spu_base.c

296

spin_unlock(&spu->register_lock);

arch/powerpc/platforms/cell/spu_base.c

304

struct spu *spu;

arch/powerpc/platforms/cell/spu_base.c

307

spu = data;

arch/powerpc/platforms/cell/spu_base.c

310

spin_lock(&spu->register_lock);

arch/powerpc/platforms/cell/spu_base.c

311

mask = spu_int_mask_get(spu, 1);

arch/powerpc/platforms/cell/spu_base.c

312

stat = spu_int_stat_get(spu, 1) & mask;

arch/powerpc/platforms/cell/spu_base.c

313

dar = spu_mfc_dar_get(spu);

arch/powerpc/platforms/cell/spu_base.c

314

dsisr = spu_mfc_dsisr_get(spu);

arch/powerpc/platforms/cell/spu_base.c

316

spu_mfc_dsisr_set(spu, 0ul);

arch/powerpc/platforms/cell/spu_base.c

317

spu_int_stat_clear(spu, 1, stat);

arch/powerpc/platforms/cell/spu_base.c

323

__spu_trap_data_seg(spu, dar);

arch/powerpc/platforms/cell/spu_base.c

326

__spu_trap_data_map(spu, dar, dsisr);

arch/powerpc/platforms/cell/spu_base.c

328

spu->class_1_dsisr = 0;

arch/powerpc/platforms/cell/spu_base.c

329

spu->class_1_dar = 0;

arch/powerpc/platforms/cell/spu_base.c

331

spin_unlock(&spu->register_lock);

arch/powerpc/platforms/cell/spu_base.c

339

struct spu *spu;

arch/powerpc/platforms/cell/spu_base.c

345

spu = data;

arch/powerpc/platforms/cell/spu_base.c

346

spin_lock(&spu->register_lock);

arch/powerpc/platforms/cell/spu_base.c

347

stat = spu_int_stat_get(spu, 2);

arch/powerpc/platforms/cell/spu_base.c

348

mask = spu_int_mask_get(spu, 2);

arch/powerpc/platforms/cell/spu_base.c

354

spu_int_mask_and(spu, 2, ~(stat & mailbox_intrs));

arch/powerpc/platforms/cell/spu_base.c

356

spu_int_stat_clear(spu, 2, stat);

arch/powerpc/platforms/cell/spu_base.c

361

spu->ibox_callback(spu);

arch/powerpc/platforms/cell/spu_base.c

364

spu->stop_callback(spu, 2);

arch/powerpc/platforms/cell/spu_base.c

367

spu->stop_callback(spu, 2);

arch/powerpc/platforms/cell/spu_base.c

370

spu->mfc_callback(spu);

arch/powerpc/platforms/cell/spu_base.c

373

spu->wbox_callback(spu);

arch/powerpc/platforms/cell/spu_base.c

375

spu->stats.class2_intr++;

arch/powerpc/platforms/cell/spu_base.c

377

spin_unlock(&spu->register_lock);

arch/powerpc/platforms/cell/spu_base.c

382

static int __init spu_request_irqs(struct spu *spu)

arch/powerpc/platforms/cell/spu_base.c

386

if (spu->irqs[0]) {

arch/powerpc/platforms/cell/spu_base.c

387

snprintf(spu->irq_c0, sizeof (spu->irq_c0), "spe%02d.0",

arch/powerpc/platforms/cell/spu_base.c

388

spu->number);

arch/powerpc/platforms/cell/spu_base.c

389

ret = request_irq(spu->irqs[0], spu_irq_class_0,

arch/powerpc/platforms/cell/spu_base.c

390

0, spu->irq_c0, spu);

arch/powerpc/platforms/cell/spu_base.c

394

if (spu->irqs[1]) {

arch/powerpc/platforms/cell/spu_base.c

395

snprintf(spu->irq_c1, sizeof (spu->irq_c1), "spe%02d.1",

arch/powerpc/platforms/cell/spu_base.c

396

spu->number);

arch/powerpc/platforms/cell/spu_base.c

397

ret = request_irq(spu->irqs[1], spu_irq_class_1,

arch/powerpc/platforms/cell/spu_base.c

398

0, spu->irq_c1, spu);

arch/powerpc/platforms/cell/spu_base.c

402

if (spu->irqs[2]) {

arch/powerpc/platforms/cell/spu_base.c

403

snprintf(spu->irq_c2, sizeof (spu->irq_c2), "spe%02d.2",

arch/powerpc/platforms/cell/spu_base.c

404

spu->number);

arch/powerpc/platforms/cell/spu_base.c

405

ret = request_irq(spu->irqs[2], spu_irq_class_2,

arch/powerpc/platforms/cell/spu_base.c

406

0, spu->irq_c2, spu);

arch/powerpc/platforms/cell/spu_base.c

413

if (spu->irqs[1])

arch/powerpc/platforms/cell/spu_base.c

414

free_irq(spu->irqs[1], spu);

arch/powerpc/platforms/cell/spu_base.c

416

if (spu->irqs[0])

arch/powerpc/platforms/cell/spu_base.c

417

free_irq(spu->irqs[0], spu);

arch/powerpc/platforms/cell/spu_base.c

422

static void spu_free_irqs(struct spu *spu)

arch/powerpc/platforms/cell/spu_base.c

424

if (spu->irqs[0])

arch/powerpc/platforms/cell/spu_base.c

425

free_irq(spu->irqs[0], spu);

arch/powerpc/platforms/cell/spu_base.c

426

if (spu->irqs[1])

arch/powerpc/platforms/cell/spu_base.c

427

free_irq(spu->irqs[1], spu);

arch/powerpc/platforms/cell/spu_base.c

428

if (spu->irqs[2])

arch/powerpc/platforms/cell/spu_base.c

429

free_irq(spu->irqs[2], spu);

arch/powerpc/platforms/cell/spu_base.c

432

void spu_init_channels(struct spu *spu)

arch/powerpc/platforms/cell/spu_base.c

448

priv2 = spu->priv2;

arch/powerpc/platforms/cell/spu_base.c

474

struct spu *spu;

arch/powerpc/platforms/cell/spu_base.c

477

list_for_each_entry(spu, &spu_full_list, full_list)

arch/powerpc/platforms/cell/spu_base.c

478

device_create_file(&spu->dev, attr);

arch/powerpc/platforms/cell/spu_base.c

487

struct spu *spu;

arch/powerpc/platforms/cell/spu_base.c

491

list_for_each_entry(spu, &spu_full_list, full_list) {

arch/powerpc/platforms/cell/spu_base.c

492

rc = sysfs_create_group(&spu->dev.kobj, attrs);

arch/powerpc/platforms/cell/spu_base.c

499

list_for_each_entry_continue_reverse(spu,

arch/powerpc/platforms/cell/spu_base.c

501

sysfs_remove_group(&spu->dev.kobj, attrs);

arch/powerpc/platforms/cell/spu_base.c

515

struct spu *spu;

arch/powerpc/platforms/cell/spu_base.c

518

list_for_each_entry(spu, &spu_full_list, full_list)

arch/powerpc/platforms/cell/spu_base.c

519

device_remove_file(&spu->dev, attr);

arch/powerpc/platforms/cell/spu_base.c

526

struct spu *spu;

arch/powerpc/platforms/cell/spu_base.c

529

list_for_each_entry(spu, &spu_full_list, full_list)

arch/powerpc/platforms/cell/spu_base.c

530

sysfs_remove_group(&spu->dev.kobj, attrs);

arch/powerpc/platforms/cell/spu_base.c

535

static int __init spu_create_dev(struct spu *spu)

arch/powerpc/platforms/cell/spu_base.c

539

spu->dev.id = spu->number;

arch/powerpc/platforms/cell/spu_base.c

540

spu->dev.bus = &spu_subsys;

arch/powerpc/platforms/cell/spu_base.c

541

ret = device_register(&spu->dev);

arch/powerpc/platforms/cell/spu_base.c

544

spu->number);

arch/powerpc/platforms/cell/spu_base.c

548

sysfs_add_device_to_node(&spu->dev, spu->node);

arch/powerpc/platforms/cell/spu_base.c

555

struct spu *spu;

arch/powerpc/platforms/cell/spu_base.c

561

spu = kzalloc_obj(*spu);

arch/powerpc/platforms/cell/spu_base.c

562

if (!spu)

arch/powerpc/platforms/cell/spu_base.c

565

spu->alloc_state = SPU_FREE;

arch/powerpc/platforms/cell/spu_base.c

567

spin_lock_init(&spu->register_lock);

arch/powerpc/platforms/cell/spu_base.c

569

spu->number = number++;

arch/powerpc/platforms/cell/spu_base.c

572

ret = spu_create_spu(spu, data);

arch/powerpc/platforms/cell/spu_base.c

577

spu_mfc_sdr_setup(spu);

arch/powerpc/platforms/cell/spu_base.c

578

spu_mfc_sr1_set(spu, 0x33);

arch/powerpc/platforms/cell/spu_base.c

579

ret = spu_request_irqs(spu);

arch/powerpc/platforms/cell/spu_base.c

583

ret = spu_create_dev(spu);

arch/powerpc/platforms/cell/spu_base.c

587

mutex_lock(&cbe_spu_info[spu->node].list_mutex);

arch/powerpc/platforms/cell/spu_base.c

588

list_add(&spu->cbe_list, &cbe_spu_info[spu->node].spus);

arch/powerpc/platforms/cell/spu_base.c

589

cbe_spu_info[spu->node].n_spus++;

arch/powerpc/platforms/cell/spu_base.c

590

mutex_unlock(&cbe_spu_info[spu->node].list_mutex);

arch/powerpc/platforms/cell/spu_base.c

594

list_add(&spu->full_list, &spu_full_list);

arch/powerpc/platforms/cell/spu_base.c

598

spu->stats.util_state = SPU_UTIL_IDLE_LOADED;

arch/powerpc/platforms/cell/spu_base.c

599

spu->stats.tstamp = ktime_get_ns();

arch/powerpc/platforms/cell/spu_base.c

601

INIT_LIST_HEAD(&spu->aff_list);

arch/powerpc/platforms/cell/spu_base.c

606

spu_free_irqs(spu);

arch/powerpc/platforms/cell/spu_base.c

608

spu_destroy_spu(spu);

arch/powerpc/platforms/cell/spu_base.c

610

kfree(spu);

arch/powerpc/platforms/cell/spu_base.c

619

static unsigned long long spu_acct_time(struct spu *spu,

arch/powerpc/platforms/cell/spu_base.c

622

unsigned long long time = spu->stats.times[state];

arch/powerpc/platforms/cell/spu_base.c

629

if (spu->stats.util_state == state)

arch/powerpc/platforms/cell/spu_base.c

630

time += ktime_get_ns() - spu->stats.tstamp;

arch/powerpc/platforms/cell/spu_base.c

639

struct spu *spu = container_of(dev, struct spu, dev);

arch/powerpc/platforms/cell/spu_base.c

64

void spu_invalidate_slbs(struct spu *spu)

arch/powerpc/platforms/cell/spu_base.c

643

spu_state_names[spu->stats.util_state],

arch/powerpc/platforms/cell/spu_base.c

644

spu_acct_time(spu, SPU_UTIL_USER),

arch/powerpc/platforms/cell/spu_base.c

645

spu_acct_time(spu, SPU_UTIL_SYSTEM),

arch/powerpc/platforms/cell/spu_base.c

646

spu_acct_time(spu, SPU_UTIL_IOWAIT),

arch/powerpc/platforms/cell/spu_base.c

647

spu_acct_time(spu, SPU_UTIL_IDLE_LOADED),

arch/powerpc/platforms/cell/spu_base.c

648

spu->stats.vol_ctx_switch,

arch/powerpc/platforms/cell/spu_base.c

649

spu->stats.invol_ctx_switch,

arch/powerpc/platforms/cell/spu_base.c

650

spu->stats.slb_flt,

arch/powerpc/platforms/cell/spu_base.c

651

spu->stats.hash_flt,

arch/powerpc/platforms/cell/spu_base.c

652

spu->stats.min_flt,

arch/powerpc/platforms/cell/spu_base.c

653

spu->stats.maj_flt,

arch/powerpc/platforms/cell/spu_base.c

654

spu->stats.class2_intr,

arch/powerpc/platforms/cell/spu_base.c

655

spu->stats.libassist);

arch/powerpc/platforms/cell/spu_base.c

66

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spu_base.c

663

struct spu *spu;

arch/powerpc/platforms/cell/spu_base.c

677

struct spu *spu;

arch/powerpc/platforms/cell/spu_base.c

682

if (!crash_spu_info[i].spu)

arch/powerpc/platforms/cell/spu_base.c

685

spu = crash_spu_info[i].spu;

arch/powerpc/platforms/cell/spu_base.c

688

in_be32(&spu->problem->spu_runcntl_RW);

arch/powerpc/platforms/cell/spu_base.c

69

spin_lock_irqsave(&spu->register_lock, flags);

arch/powerpc/platforms/cell/spu_base.c

690

in_be32(&spu->problem->spu_status_R);

arch/powerpc/platforms/cell/spu_base.c

692

in_be32(&spu->problem->spu_npc_RW);

arch/powerpc/platforms/cell/spu_base.c

694

crash_spu_info[i].saved_mfc_dar = spu_mfc_dar_get(spu);

arch/powerpc/platforms/cell/spu_base.c

695

crash_spu_info[i].saved_mfc_dsisr = spu_mfc_dsisr_get(spu);

arch/powerpc/platforms/cell/spu_base.c

696

tmp = spu_mfc_sr1_get(spu);

arch/powerpc/platforms/cell/spu_base.c

70

if (spu_mfc_sr1_get(spu) & MFC_STATE1_RELOCATE_MASK)

arch/powerpc/platforms/cell/spu_base.c

700

spu_mfc_sr1_set(spu, tmp);

arch/powerpc/platforms/cell/spu_base.c

708

struct spu *spu;

arch/powerpc/platforms/cell/spu_base.c

711

list_for_each_entry(spu, list, full_list) {

arch/powerpc/platforms/cell/spu_base.c

712

if (WARN_ON(spu->number >= CRASH_NUM_SPUS))

arch/powerpc/platforms/cell/spu_base.c

715

crash_spu_info[spu->number].spu = spu;

arch/powerpc/platforms/cell/spu_base.c

72

spin_unlock_irqrestore(&spu->register_lock, flags);

arch/powerpc/platforms/cell/spu_base.c

731

struct spu *spu;

arch/powerpc/platforms/cell/spu_base.c

734

list_for_each_entry(spu, &spu_full_list, full_list) {

arch/powerpc/platforms/cell/spu_base.c

735

spu_free_irqs(spu);

arch/powerpc/platforms/cell/spu_base.c

736

spu_destroy_spu(spu);

arch/powerpc/platforms/cell/spu_base.c

81

struct spu *spu;

arch/powerpc/platforms/cell/spu_base.c

85

list_for_each_entry(spu, &spu_full_list, full_list) {

arch/powerpc/platforms/cell/spu_base.c

86

if (spu->mm == mm)

arch/powerpc/platforms/cell/spu_base.c

87

spu_invalidate_slbs(spu);

arch/powerpc/platforms/cell/spufs/fault.c

115

ctx->spu->stats.hash_flt++;

arch/powerpc/platforms/cell/spufs/fault.c

155

ctx->spu->stats.maj_flt++;

arch/powerpc/platforms/cell/spufs/fault.c

157

ctx->spu->stats.min_flt++;

arch/powerpc/platforms/cell/spufs/fault.c

160

if (ctx->spu)

arch/powerpc/platforms/cell/spufs/file.c

1458

void spufs_mfc_callback(struct spu *spu)

arch/powerpc/platforms/cell/spufs/file.c

1460

struct spu_context *ctx = spu->ctx;

arch/powerpc/platforms/cell/spufs/file.c

1861

num = ctx->spu->number;

arch/powerpc/platforms/cell/spufs/file.c

2187

if (ctx->spu && ctx->stats.util_state == state) {

arch/powerpc/platforms/cell/spufs/file.c

2199

slb_flts += (ctx->spu->stats.slb_flt -

arch/powerpc/platforms/cell/spufs/file.c

2211

class2_intrs += (ctx->spu->stats.class2_intr -

arch/powerpc/platforms/cell/spufs/file.c

2436

void spu_switch_log_notify(struct spu *spu, struct spu_context *ctx,

arch/powerpc/platforms/cell/spufs/file.c

2448

p->spu_id = spu ? spu->number : -1;

arch/powerpc/platforms/cell/spufs/file.c

2465

if (ctx->spu) {

arch/powerpc/platforms/cell/spufs/file.c

2466

struct spu *spu = ctx->spu;

arch/powerpc/platforms/cell/spufs/file.c

2467

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/file.c

2469

spin_lock_irq(&spu->register_lock);

arch/powerpc/platforms/cell/spufs/file.c

2471

spin_unlock_irq(&spu->register_lock);

arch/powerpc/platforms/cell/spufs/file.c

2485

ctx->spu ? ctx->spu->number : -1,

arch/powerpc/platforms/cell/spufs/file.c

252

pfn = (ctx->spu->local_store_phys + offset) >> PAGE_SHIFT;

arch/powerpc/platforms/cell/spufs/file.c

349

spu_context_trace(spufs_ps_fault__wake, ctx, ctx->spu);

arch/powerpc/platforms/cell/spufs/file.c

352

area = ctx->spu->problem_phys + ps_offs;

arch/powerpc/platforms/cell/spufs/file.c

355

spu_context_trace(spufs_ps_fault__insert, ctx, ctx->spu);

arch/powerpc/platforms/cell/spufs/file.c

674

void spufs_ibox_callback(struct spu *spu)

arch/powerpc/platforms/cell/spufs/file.c

676

struct spu_context *ctx = spu->ctx;

arch/powerpc/platforms/cell/spufs/file.c

805

void spufs_wbox_callback(struct spu *spu)

arch/powerpc/platforms/cell/spufs/file.c

807

struct spu_context *ctx = spu->ctx;

arch/powerpc/platforms/cell/spufs/hw_ops.c

105

struct spu *spu = ctx->spu;

arch/powerpc/platforms/cell/spufs/hw_ops.c

106

struct spu_problem __iomem *prob = spu->problem;

arch/powerpc/platforms/cell/spufs/hw_ops.c

109

spin_lock_irq(&spu->register_lock);

arch/powerpc/platforms/cell/spufs/hw_ops.c

117

spu_int_mask_or(spu, 2, CLASS2_ENABLE_MAILBOX_THRESHOLD_INTR);

arch/powerpc/platforms/cell/spufs/hw_ops.c

120

spin_unlock_irq(&spu->register_lock);

arch/powerpc/platforms/cell/spufs/hw_ops.c

126

out_be32(&ctx->spu->problem->signal_notify1, data);

arch/powerpc/platforms/cell/spufs/hw_ops.c

131

out_be32(&ctx->spu->problem->signal_notify2, data);

arch/powerpc/platforms/cell/spufs/hw_ops.c

136

struct spu *spu = ctx->spu;

arch/powerpc/platforms/cell/spufs/hw_ops.c

137

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/hw_ops.c

140

spin_lock_irq(&spu->register_lock);

arch/powerpc/platforms/cell/spufs/hw_ops.c

147

spin_unlock_irq(&spu->register_lock);

arch/powerpc/platforms/cell/spufs/hw_ops.c

152

return ((in_be64(&ctx->spu->priv2->spu_cfg_RW) & 1) != 0);

arch/powerpc/platforms/cell/spufs/hw_ops.c

157

struct spu *spu = ctx->spu;

arch/powerpc/platforms/cell/spufs/hw_ops.c

158

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/hw_ops.c

161

spin_lock_irq(&spu->register_lock);

arch/powerpc/platforms/cell/spufs/hw_ops.c

168

spin_unlock_irq(&spu->register_lock);

arch/powerpc/platforms/cell/spufs/hw_ops.c

173

return ((in_be64(&ctx->spu->priv2->spu_cfg_RW) & 2) != 0);

arch/powerpc/platforms/cell/spufs/hw_ops.c

178

return in_be32(&ctx->spu->problem->spu_npc_RW);

arch/powerpc/platforms/cell/spufs/hw_ops.c

183

out_be32(&ctx->spu->problem->spu_npc_RW, val);

arch/powerpc/platforms/cell/spufs/hw_ops.c

188

return in_be32(&ctx->spu->problem->spu_status_R);

arch/powerpc/platforms/cell/spufs/hw_ops.c

193

return ctx->spu->local_store;

arch/powerpc/platforms/cell/spufs/hw_ops.c

198

out_be64(&ctx->spu->priv2->spu_privcntl_RW, val);

arch/powerpc/platforms/cell/spufs/hw_ops.c

203

return in_be32(&ctx->spu->problem->spu_runcntl_RW);

arch/powerpc/platforms/cell/spufs/hw_ops.c

208

spin_lock_irq(&ctx->spu->register_lock);

arch/powerpc/platforms/cell/spufs/hw_ops.c

212

out_be32(&ctx->spu->problem->spu_runcntl_RW, val);

arch/powerpc/platforms/cell/spufs/hw_ops.c

213

spin_unlock_irq(&ctx->spu->register_lock);

arch/powerpc/platforms/cell/spufs/hw_ops.c

218

spin_lock_irq(&ctx->spu->register_lock);

arch/powerpc/platforms/cell/spufs/hw_ops.c

219

out_be32(&ctx->spu->problem->spu_runcntl_RW, SPU_RUNCNTL_STOP);

arch/powerpc/platforms/cell/spufs/hw_ops.c

220

while (in_be32(&ctx->spu->problem->spu_status_R) & SPU_STATUS_RUNNING)

arch/powerpc/platforms/cell/spufs/hw_ops.c

222

spin_unlock_irq(&ctx->spu->register_lock);

arch/powerpc/platforms/cell/spufs/hw_ops.c

227

struct spu *spu = ctx->spu;

arch/powerpc/platforms/cell/spufs/hw_ops.c

230

spin_lock_irq(&spu->register_lock);

arch/powerpc/platforms/cell/spufs/hw_ops.c

231

sr1 = spu_mfc_sr1_get(spu) | MFC_STATE1_MASTER_RUN_CONTROL_MASK;

arch/powerpc/platforms/cell/spufs/hw_ops.c

232

spu_mfc_sr1_set(spu, sr1);

arch/powerpc/platforms/cell/spufs/hw_ops.c

233

spin_unlock_irq(&spu->register_lock);

arch/powerpc/platforms/cell/spufs/hw_ops.c

238

struct spu *spu = ctx->spu;

arch/powerpc/platforms/cell/spufs/hw_ops.c

241

spin_lock_irq(&spu->register_lock);

arch/powerpc/platforms/cell/spufs/hw_ops.c

242

sr1 = spu_mfc_sr1_get(spu) & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK;

arch/powerpc/platforms/cell/spufs/hw_ops.c

243

spu_mfc_sr1_set(spu, sr1);

arch/powerpc/platforms/cell/spufs/hw_ops.c

244

spin_unlock_irq(&spu->register_lock);

arch/powerpc/platforms/cell/spufs/hw_ops.c

249

struct spu_problem __iomem *prob = ctx->spu->problem;

arch/powerpc/platforms/cell/spufs/hw_ops.c

252

spin_lock_irq(&ctx->spu->register_lock);

arch/powerpc/platforms/cell/spufs/hw_ops.c

26

struct spu *spu = ctx->spu;

arch/powerpc/platforms/cell/spufs/hw_ops.c

260

spin_unlock_irq(&ctx->spu->register_lock);

arch/powerpc/platforms/cell/spufs/hw_ops.c

266

return in_be32(&ctx->spu->problem->dma_tagstatus_R);

arch/powerpc/platforms/cell/spufs/hw_ops.c

27

struct spu_problem __iomem *prob = spu->problem;

arch/powerpc/platforms/cell/spufs/hw_ops.c

271

return in_be32(&ctx->spu->problem->dma_qstatus_R);

arch/powerpc/platforms/cell/spufs/hw_ops.c

278

struct spu_problem __iomem *prob = ctx->spu->problem;

arch/powerpc/platforms/cell/spufs/hw_ops.c

280

spin_lock_irq(&ctx->spu->register_lock);

arch/powerpc/platforms/cell/spufs/hw_ops.c

288

spin_unlock_irq(&ctx->spu->register_lock);

arch/powerpc/platforms/cell/spufs/hw_ops.c

302

struct spu_priv2 __iomem *priv2 = ctx->spu->priv2;

arch/powerpc/platforms/cell/spufs/hw_ops.c

304

if (!test_bit(SPU_CONTEXT_SWITCH_PENDING, &ctx->spu->flags))

arch/powerpc/platforms/cell/spufs/hw_ops.c

31

spin_lock_irq(&spu->register_lock);

arch/powerpc/platforms/cell/spufs/hw_ops.c

37

spin_unlock_irq(&spu->register_lock);

arch/powerpc/platforms/cell/spufs/hw_ops.c

43

return in_be32(&ctx->spu->problem->mb_stat_R);

arch/powerpc/platforms/cell/spufs/hw_ops.c

48

struct spu *spu = ctx->spu;

arch/powerpc/platforms/cell/spufs/hw_ops.c

52

spin_lock_irq(&spu->register_lock);

arch/powerpc/platforms/cell/spufs/hw_ops.c

53

stat = in_be32(&spu->problem->mb_stat_R);

arch/powerpc/platforms/cell/spufs/hw_ops.c

64

spu_int_stat_clear(spu, 2, CLASS2_MAILBOX_INTR);

arch/powerpc/platforms/cell/spufs/hw_ops.c

65

spu_int_mask_or(spu, 2, CLASS2_ENABLE_MAILBOX_INTR);

arch/powerpc/platforms/cell/spufs/hw_ops.c

72

spu_int_stat_clear(spu, 2,

arch/powerpc/platforms/cell/spufs/hw_ops.c

74

spu_int_mask_or(spu, 2,

arch/powerpc/platforms/cell/spufs/hw_ops.c

78

spin_unlock_irq(&spu->register_lock);

arch/powerpc/platforms/cell/spufs/hw_ops.c

84

struct spu *spu = ctx->spu;

arch/powerpc/platforms/cell/spufs/hw_ops.c

85

struct spu_problem __iomem *prob = spu->problem;

arch/powerpc/platforms/cell/spufs/hw_ops.c

86

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/hw_ops.c

89

spin_lock_irq(&spu->register_lock);

arch/powerpc/platforms/cell/spufs/hw_ops.c

96

spu_int_mask_or(spu, 2, CLASS2_ENABLE_MAILBOX_INTR);

arch/powerpc/platforms/cell/spufs/hw_ops.c

99

spin_unlock_irq(&spu->register_lock);

arch/powerpc/platforms/cell/spufs/inode.c

284

struct spu, cbe_list))->aff_list);

arch/powerpc/platforms/cell/spufs/run.c

104

mfc_cntl = &ctx->spu->priv2->mfc_control_RW;

arch/powerpc/platforms/cell/spufs/run.c

125

sr1 = spu_mfc_sr1_get(ctx->spu);

arch/powerpc/platforms/cell/spufs/run.c

127

spu_mfc_sr1_set(ctx->spu, sr1);

arch/powerpc/platforms/cell/spufs/run.c

15

void spufs_stop_callback(struct spu *spu, int irq)

arch/powerpc/platforms/cell/spufs/run.c

17

struct spu_context *ctx = spu->ctx;

arch/powerpc/platforms/cell/spufs/run.c

170

spu_mfc_sr1_set(ctx->spu, sr1);

arch/powerpc/platforms/cell/spufs/run.c

30

ctx->csa.class_0_pending = spu->class_0_pending;

arch/powerpc/platforms/cell/spufs/run.c

31

ctx->csa.class_0_dar = spu->class_0_dar;

arch/powerpc/platforms/cell/spufs/run.c

34

ctx->csa.class_1_dsisr = spu->class_1_dsisr;

arch/powerpc/platforms/cell/spufs/run.c

35

ctx->csa.class_1_dar = spu->class_1_dar;

arch/powerpc/platforms/cell/spufs/sched.c

1000

list_for_each_entry(spu, &cbe_spu_info[node].spus,

arch/powerpc/platforms/cell/spufs/sched.c

1002

struct spu_context *ctx = spu->ctx;

arch/powerpc/platforms/cell/spufs/sched.c

1024

struct spu *spu;

arch/powerpc/platforms/cell/spufs/sched.c

1034

spu = ctx->spu;

arch/powerpc/platforms/cell/spufs/sched.c

1042

if (spu) {

arch/powerpc/platforms/cell/spufs/sched.c

1044

spu->stats.times[old_state] += delta;

arch/powerpc/platforms/cell/spufs/sched.c

1045

spu->stats.util_state = new_state;

arch/powerpc/platforms/cell/spufs/sched.c

1046

spu->stats.tstamp = curtime;

arch/powerpc/platforms/cell/spufs/sched.c

1047

node = spu->node;

arch/powerpc/platforms/cell/spufs/sched.c

1124

struct spu *spu;

arch/powerpc/platforms/cell/spufs/sched.c

1135

list_for_each_entry(spu, &cbe_spu_info[node].spus, cbe_list)

arch/powerpc/platforms/cell/spufs/sched.c

1136

if (spu->alloc_state != SPU_FREE)

arch/powerpc/platforms/cell/spufs/sched.c

1137

spu->alloc_state = SPU_FREE;

arch/powerpc/platforms/cell/spufs/sched.c

142

node = ctx->spu->node;

arch/powerpc/platforms/cell/spufs/sched.c

186

struct spu *spu;

arch/powerpc/platforms/cell/spufs/sched.c

189

list_for_each_entry(spu, &cbe_spu_info[node].spus, cbe_list) {

arch/powerpc/platforms/cell/spufs/sched.c

190

if (spu->alloc_state != SPU_FREE) {

arch/powerpc/platforms/cell/spufs/sched.c

191

struct spu_context *ctx = spu->ctx;

arch/powerpc/platforms/cell/spufs/sched.c

207

static void spu_bind_context(struct spu *spu, struct spu_context *ctx)

arch/powerpc/platforms/cell/spufs/sched.c

209

spu_context_trace(spu_bind_context__enter, ctx, spu);

arch/powerpc/platforms/cell/spufs/sched.c

214

atomic_inc(&cbe_spu_info[spu->node].reserved_spus);

arch/powerpc/platforms/cell/spufs/sched.c

216

ctx->stats.slb_flt_base = spu->stats.slb_flt;

arch/powerpc/platforms/cell/spufs/sched.c

217

ctx->stats.class2_intr_base = spu->stats.class2_intr;

arch/powerpc/platforms/cell/spufs/sched.c

219

spu_associate_mm(spu, ctx->owner);

arch/powerpc/platforms/cell/spufs/sched.c

221

spin_lock_irq(&spu->register_lock);

arch/powerpc/platforms/cell/spufs/sched.c

222

spu->ctx = ctx;

arch/powerpc/platforms/cell/spufs/sched.c

223

spu->flags = 0;

arch/powerpc/platforms/cell/spufs/sched.c

224

ctx->spu = spu;

arch/powerpc/platforms/cell/spufs/sched.c

226

spu->pid = current->pid;

arch/powerpc/platforms/cell/spufs/sched.c

227

spu->tgid = current->tgid;

arch/powerpc/platforms/cell/spufs/sched.c

228

spu->ibox_callback = spufs_ibox_callback;

arch/powerpc/platforms/cell/spufs/sched.c

229

spu->wbox_callback = spufs_wbox_callback;

arch/powerpc/platforms/cell/spufs/sched.c

230

spu->stop_callback = spufs_stop_callback;

arch/powerpc/platforms/cell/spufs/sched.c

231

spu->mfc_callback = spufs_mfc_callback;

arch/powerpc/platforms/cell/spufs/sched.c

232

spin_unlock_irq(&spu->register_lock);

arch/powerpc/platforms/cell/spufs/sched.c

236

spu_switch_log_notify(spu, ctx, SWITCH_LOG_START, 0);

arch/powerpc/platforms/cell/spufs/sched.c

237

spu_restore(&ctx->csa, spu);

arch/powerpc/platforms/cell/spufs/sched.c

238

spu->timestamp = jiffies;

arch/powerpc/platforms/cell/spufs/sched.c

247

static inline int sched_spu(struct spu *spu)

arch/powerpc/platforms/cell/spufs/sched.c

249

BUG_ON(!mutex_is_locked(&cbe_spu_info[spu->node].list_mutex));

arch/powerpc/platforms/cell/spufs/sched.c

251

return (!spu->ctx || !(spu->ctx->flags & SPU_CREATE_NOSCHED));

arch/powerpc/platforms/cell/spufs/sched.c

288

static struct spu *aff_ref_location(struct spu_context *ctx, int mem_aff,

arch/powerpc/platforms/cell/spufs/sched.c

291

struct spu *spu;

arch/powerpc/platforms/cell/spufs/sched.c

317

list_for_each_entry(spu, &cbe_spu_info[node].spus, cbe_list) {

arch/powerpc/platforms/cell/spufs/sched.c

318

if (spu->ctx && spu->ctx->gang && !spu->ctx->aff_offset

arch/powerpc/platforms/cell/spufs/sched.c

319

&& spu->ctx->gang->aff_ref_spu)

arch/powerpc/platforms/cell/spufs/sched.c

320

available_spus -= spu->ctx->gang->contexts;

arch/powerpc/platforms/cell/spufs/sched.c

328

list_for_each_entry(spu, &cbe_spu_info[node].spus, cbe_list) {

arch/powerpc/platforms/cell/spufs/sched.c

329

if ((!mem_aff || spu->has_mem_affinity) &&

arch/powerpc/platforms/cell/spufs/sched.c

330

sched_spu(spu)) {

arch/powerpc/platforms/cell/spufs/sched.c

332

return spu;

arch/powerpc/platforms/cell/spufs/sched.c

363

static struct spu *ctx_location(struct spu *ref, int offset, int node)

arch/powerpc/platforms/cell/spufs/sched.c

365

struct spu *spu;

arch/powerpc/platforms/cell/spufs/sched.c

367

spu = NULL;

arch/powerpc/platforms/cell/spufs/sched.c

369

list_for_each_entry(spu, ref->aff_list.prev, aff_list) {

arch/powerpc/platforms/cell/spufs/sched.c

370

BUG_ON(spu->node != node);

arch/powerpc/platforms/cell/spufs/sched.c

373

if (sched_spu(spu))

arch/powerpc/platforms/cell/spufs/sched.c

377

list_for_each_entry_reverse(spu, ref->aff_list.next, aff_list) {

arch/powerpc/platforms/cell/spufs/sched.c

378

BUG_ON(spu->node != node);

arch/powerpc/platforms/cell/spufs/sched.c

381

if (sched_spu(spu))

arch/powerpc/platforms/cell/spufs/sched.c

386

return spu;

arch/powerpc/platforms/cell/spufs/sched.c

419

static void spu_unbind_context(struct spu *spu, struct spu_context *ctx)

arch/powerpc/platforms/cell/spufs/sched.c

423

spu_context_trace(spu_unbind_context__enter, ctx, spu);

arch/powerpc/platforms/cell/spufs/sched.c

427

if (spu->ctx->flags & SPU_CREATE_NOSCHED)

arch/powerpc/platforms/cell/spufs/sched.c

428

atomic_dec(&cbe_spu_info[spu->node].reserved_spus);

arch/powerpc/platforms/cell/spufs/sched.c

439

spu_save(&ctx->csa, spu);

arch/powerpc/platforms/cell/spufs/sched.c

440

spu_switch_log_notify(spu, ctx, SWITCH_LOG_STOP, 0);

arch/powerpc/platforms/cell/spufs/sched.c

442

spin_lock_irq(&spu->register_lock);

arch/powerpc/platforms/cell/spufs/sched.c

443

spu->timestamp = jiffies;

arch/powerpc/platforms/cell/spufs/sched.c

445

spu->ibox_callback = NULL;

arch/powerpc/platforms/cell/spufs/sched.c

446

spu->wbox_callback = NULL;

arch/powerpc/platforms/cell/spufs/sched.c

447

spu->stop_callback = NULL;

arch/powerpc/platforms/cell/spufs/sched.c

448

spu->mfc_callback = NULL;

arch/powerpc/platforms/cell/spufs/sched.c

449

spu->pid = 0;

arch/powerpc/platforms/cell/spufs/sched.c

450

spu->tgid = 0;

arch/powerpc/platforms/cell/spufs/sched.c

452

spu->flags = 0;

arch/powerpc/platforms/cell/spufs/sched.c

453

spu->ctx = NULL;

arch/powerpc/platforms/cell/spufs/sched.c

454

spin_unlock_irq(&spu->register_lock);

arch/powerpc/platforms/cell/spufs/sched.c

456

spu_associate_mm(spu, NULL);

arch/powerpc/platforms/cell/spufs/sched.c

459

(spu->stats.slb_flt - ctx->stats.slb_flt_base);

arch/powerpc/platforms/cell/spufs/sched.c

461

(spu->stats.class2_intr - ctx->stats.class2_intr_base);

arch/powerpc/platforms/cell/spufs/sched.c

465

ctx->spu = NULL;

arch/powerpc/platforms/cell/spufs/sched.c

553

static struct spu *spu_get_idle(struct spu_context *ctx)

arch/powerpc/platforms/cell/spufs/sched.c

555

struct spu *spu, *aff_ref_spu;

arch/powerpc/platforms/cell/spufs/sched.c

569

spu = ctx_location(aff_ref_spu, ctx->aff_offset, node);

arch/powerpc/platforms/cell/spufs/sched.c

570

if (spu && spu->alloc_state == SPU_FREE)

arch/powerpc/platforms/cell/spufs/sched.c

586

list_for_each_entry(spu, &cbe_spu_info[node].spus, cbe_list) {

arch/powerpc/platforms/cell/spufs/sched.c

587

if (spu->alloc_state == SPU_FREE)

arch/powerpc/platforms/cell/spufs/sched.c

598

spu->alloc_state = SPU_USED;

arch/powerpc/platforms/cell/spufs/sched.c

600

spu_context_trace(spu_get_idle__found, ctx, spu);

arch/powerpc/platforms/cell/spufs/sched.c

601

spu_init_channels(spu);

arch/powerpc/platforms/cell/spufs/sched.c

602

return spu;

arch/powerpc/platforms/cell/spufs/sched.c

611

static struct spu *find_victim(struct spu_context *ctx)

arch/powerpc/platforms/cell/spufs/sched.c

614

struct spu *spu;

arch/powerpc/platforms/cell/spufs/sched.c

634

list_for_each_entry(spu, &cbe_spu_info[node].spus, cbe_list) {

arch/powerpc/platforms/cell/spufs/sched.c

635

struct spu_context *tmp = spu->ctx;

arch/powerpc/platforms/cell/spufs/sched.c

640

victim = spu->ctx;

arch/powerpc/platforms/cell/spufs/sched.c

664

spu = victim->spu;

arch/powerpc/platforms/cell/spufs/sched.c

665

if (!spu || victim->prio <= ctx->prio) {

arch/powerpc/platforms/cell/spufs/sched.c

677

spu_context_trace(__spu_deactivate__unload, ctx, spu);

arch/powerpc/platforms/cell/spufs/sched.c

681

spu_unbind_context(spu, victim);

arch/powerpc/platforms/cell/spufs/sched.c

685

spu->stats.invol_ctx_switch++;

arch/powerpc/platforms/cell/spufs/sched.c

692

return spu;

arch/powerpc/platforms/cell/spufs/sched.c

699

static void __spu_schedule(struct spu *spu, struct spu_context *ctx)

arch/powerpc/platforms/cell/spufs/sched.c

701

int node = spu->node;

arch/powerpc/platforms/cell/spufs/sched.c

707

if (spu->ctx == NULL) {

arch/powerpc/platforms/cell/spufs/sched.c

708

spu_bind_context(spu, ctx);

arch/powerpc/platforms/cell/spufs/sched.c

710

spu->alloc_state = SPU_USED;

arch/powerpc/platforms/cell/spufs/sched.c

721

static void spu_schedule(struct spu *spu, struct spu_context *ctx)

arch/powerpc/platforms/cell/spufs/sched.c

727

__spu_schedule(spu, ctx);

arch/powerpc/platforms/cell/spufs/sched.c

744

static void spu_unschedule(struct spu *spu, struct spu_context *ctx,

arch/powerpc/platforms/cell/spufs/sched.c

747

int node = spu->node;

arch/powerpc/platforms/cell/spufs/sched.c

752

spu->alloc_state = SPU_FREE;

arch/powerpc/platforms/cell/spufs/sched.c

753

spu_unbind_context(spu, ctx);

arch/powerpc/platforms/cell/spufs/sched.c

755

spu->stats.invol_ctx_switch++;

arch/powerpc/platforms/cell/spufs/sched.c

770

struct spu *spu;

arch/powerpc/platforms/cell/spufs/sched.c

778

if (ctx->spu)

arch/powerpc/platforms/cell/spufs/sched.c

785

spu = spu_get_idle(ctx);

arch/powerpc/platforms/cell/spufs/sched.c

790

if (!spu && rt_prio(ctx->prio))

arch/powerpc/platforms/cell/spufs/sched.c

791

spu = find_victim(ctx);

arch/powerpc/platforms/cell/spufs/sched.c

792

if (spu) {

arch/powerpc/platforms/cell/spufs/sched.c

796

__spu_schedule(spu, ctx);

arch/powerpc/platforms/cell/spufs/sched.c

846

struct spu *spu = ctx->spu;

arch/powerpc/platforms/cell/spufs/sched.c

849

if (spu) {

arch/powerpc/platforms/cell/spufs/sched.c

850

new = grab_runnable_context(max_prio, spu->node);

arch/powerpc/platforms/cell/spufs/sched.c

852

spu_unschedule(spu, ctx, new == NULL);

arch/powerpc/platforms/cell/spufs/sched.c

858

spu_schedule(spu, new);

arch/powerpc/platforms/cell/spufs/sched.c

904

struct spu *spu = NULL;

arch/powerpc/platforms/cell/spufs/sched.c

919

spu = ctx->spu;

arch/powerpc/platforms/cell/spufs/sched.c

921

spu_context_trace(spusched_tick__preempt, ctx, spu);

arch/powerpc/platforms/cell/spufs/sched.c

923

new = grab_runnable_context(ctx->prio + 1, spu->node);

arch/powerpc/platforms/cell/spufs/sched.c

925

spu_unschedule(spu, ctx, 0);

arch/powerpc/platforms/cell/spufs/sched.c

937

spu_schedule(spu, new);

arch/powerpc/platforms/cell/spufs/sched.c

990

struct spu *spu;

arch/powerpc/platforms/cell/spufs/spufs.h

152

struct spu *aff_ref_spu;

arch/powerpc/platforms/cell/spufs/spufs.h

257

struct spu *affinity_check(struct spu_context *ctx);

arch/powerpc/platforms/cell/spufs/spufs.h

286

void spu_switch_log_notify(struct spu *spu, struct spu_context *ctx,

arch/powerpc/platforms/cell/spufs/spufs.h

332

void spufs_ibox_callback(struct spu *spu);

arch/powerpc/platforms/cell/spufs/spufs.h

333

void spufs_wbox_callback(struct spu *spu);

arch/powerpc/platforms/cell/spufs/spufs.h

334

void spufs_stop_callback(struct spu *spu, int irq);

arch/powerpc/platforms/cell/spufs/spufs.h

335

void spufs_mfc_callback(struct spu *spu);

arch/powerpc/platforms/cell/spufs/spufs.h

336

void spufs_dma_callback(struct spu *spu, int type);

arch/powerpc/platforms/cell/spufs/spufs.h

348

extern int spu_save(struct spu_state *prev, struct spu *spu);

arch/powerpc/platforms/cell/spufs/spufs.h

349

extern int spu_restore(struct spu_state *new, struct spu *spu);

arch/powerpc/platforms/cell/spufs/spufs.h

351

struct spu *spu);

arch/powerpc/platforms/cell/spufs/spufs.h

68

struct spu *spu; /* pointer to a physical SPU */

arch/powerpc/platforms/cell/spufs/sputrace.h

12

TP_PROTO(struct spu_context *ctx, struct spu *spu, const char *name),

arch/powerpc/platforms/cell/spufs/sputrace.h

13

TP_ARGS(ctx, spu, name),

arch/powerpc/platforms/cell/spufs/sputrace.h

24

__entry->number = spu ? spu->number : -1;

arch/powerpc/platforms/cell/spufs/sputrace.h

31

#define spu_context_trace(name, ctx, spu) \

arch/powerpc/platforms/cell/spufs/sputrace.h

32

trace_spufs_context(ctx, spu, __stringify(name))

arch/powerpc/platforms/cell/spufs/switch.c

1031

static inline void clear_spu_status(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1033

struct spu_problem __iomem *prob = spu->problem;

arch/powerpc/platforms/cell/spufs/switch.c

1042

spu_mfc_sr1_set(spu,

arch/powerpc/platforms/cell/spufs/switch.c

1054

spu_mfc_sr1_set(spu,

arch/powerpc/platforms/cell/spufs/switch.c

1065

static inline void reset_ch_part1(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1067

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/switch.c

1090

static inline void reset_ch_part2(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1092

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/switch.c

110

spin_lock_irq(&spu->register_lock);

arch/powerpc/platforms/cell/spufs/switch.c

1111

struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

112

csa->priv1.int_mask_class0_RW = spu_int_mask_get(spu, 0);

arch/powerpc/platforms/cell/spufs/switch.c

113

csa->priv1.int_mask_class1_RW = spu_int_mask_get(spu, 1);

arch/powerpc/platforms/cell/spufs/switch.c

114

csa->priv1.int_mask_class2_RW = spu_int_mask_get(spu, 2);

arch/powerpc/platforms/cell/spufs/switch.c

116

spu_int_mask_set(spu, 0, 0ul);

arch/powerpc/platforms/cell/spufs/switch.c

117

spu_int_mask_set(spu, 1, 0ul);

arch/powerpc/platforms/cell/spufs/switch.c

118

spu_int_mask_set(spu, 2, 0ul);

arch/powerpc/platforms/cell/spufs/switch.c

120

spin_unlock_irq(&spu->register_lock);

arch/powerpc/platforms/cell/spufs/switch.c

1203

struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1226

static inline void restore_mfc_rag(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1232

spu_resource_allocation_groupID_set(spu,

arch/powerpc/platforms/cell/spufs/switch.c

1234

spu_resource_allocation_enable_set(spu,

arch/powerpc/platforms/cell/spufs/switch.c

1238

static inline void send_restore_code(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1251

send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);

arch/powerpc/platforms/cell/spufs/switch.c

1254

static inline void setup_decr(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

127

set_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags);

arch/powerpc/platforms/cell/spufs/switch.c

1279

static inline void setup_ppu_mb(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

128

clear_bit(SPU_CONTEXT_FAULT_PENDING, &spu->flags);

arch/powerpc/platforms/cell/spufs/switch.c

1287

static inline void setup_ppuint_mb(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

129

synchronize_irq(spu->irqs[0]);

arch/powerpc/platforms/cell/spufs/switch.c

1295

static inline int check_restore_status(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1297

struct spu_problem __iomem *prob = spu->problem;

arch/powerpc/platforms/cell/spufs/switch.c

130

synchronize_irq(spu->irqs[1]);

arch/powerpc/platforms/cell/spufs/switch.c

131

synchronize_irq(spu->irqs[2]);

arch/powerpc/platforms/cell/spufs/switch.c

1310

static inline void restore_spu_privcntl(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1312

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/switch.c

1321

static inline void restore_status_part1(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1323

struct spu_problem __iomem *prob = spu->problem;

arch/powerpc/platforms/cell/spufs/switch.c

134

static inline void set_watchdog_timer(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1341

static inline void restore_status_part2(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1343

struct spu_problem __iomem *prob = spu->problem;

arch/powerpc/platforms/cell/spufs/switch.c

1368

static inline void restore_ls_16kb(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1381

send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);

arch/powerpc/platforms/cell/spufs/switch.c

1384

static inline void suspend_mfc(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1386

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/switch.c

1396

static inline void clear_interrupts(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1406

spin_lock_irq(&spu->register_lock);

arch/powerpc/platforms/cell/spufs/switch.c

1407

spu_int_mask_set(spu, 0, 0ul);

arch/powerpc/platforms/cell/spufs/switch.c

1408

spu_int_mask_set(spu, 1, 0ul);

arch/powerpc/platforms/cell/spufs/switch.c

1409

spu_int_mask_set(spu, 2, 0ul);

arch/powerpc/platforms/cell/spufs/switch.c

1410

spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK);

arch/powerpc/platforms/cell/spufs/switch.c

1411

spu_int_stat_clear(spu, 1, CLASS1_INTR_MASK);

arch/powerpc/platforms/cell/spufs/switch.c

1412

spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK);

arch/powerpc/platforms/cell/spufs/switch.c

1413

spin_unlock_irq(&spu->register_lock);

arch/powerpc/platforms/cell/spufs/switch.c

1416

static inline void restore_mfc_queues(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1418

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/switch.c

1450

static inline void restore_ppu_querymask(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1452

struct spu_problem __iomem *prob = spu->problem;

arch/powerpc/platforms/cell/spufs/switch.c

1461

static inline void restore_ppu_querytype(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1463

struct spu_problem __iomem *prob = spu->problem;

arch/powerpc/platforms/cell/spufs/switch.c

147

static inline void inhibit_user_access(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1472

static inline void restore_mfc_csr_tsq(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1474

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/switch.c

1484

static inline void restore_mfc_csr_cmd(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1486

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/switch.c

1497

static inline void restore_mfc_csr_ato(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1499

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/switch.c

1507

static inline void restore_mfc_tclass_id(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1512

spu_mfc_tclass_id_set(spu, csa->priv1.mfc_tclass_id_RW);

arch/powerpc/platforms/cell/spufs/switch.c

1516

static inline void set_llr_event(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1539

static inline void restore_decr_wrapped(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1557

static inline void restore_ch_part1(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1559

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/switch.c

1576

static inline void restore_ch_part2(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1578

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/switch.c

158

static inline void set_switch_pending(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1599

static inline void restore_spu_lslr(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1601

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/switch.c

1610

static inline void restore_spu_cfg(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1612

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/switch.c

1621

static inline void restore_pm_trace(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1629

static inline void restore_spu_npc(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1631

struct spu_problem __iomem *prob = spu->problem;

arch/powerpc/platforms/cell/spufs/switch.c

1640

static inline void restore_spu_mb(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1642

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/switch.c

1657

static inline void check_ppu_mb_stat(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1659

struct spu_problem __iomem *prob = spu->problem;

arch/powerpc/platforms/cell/spufs/switch.c

167

static inline void save_mfc_cntl(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1671

static inline void check_ppuint_mb_stat(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1673

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/switch.c

1682

spu_int_stat_clear(spu, 2, CLASS2_ENABLE_MAILBOX_INTR);

arch/powerpc/platforms/cell/spufs/switch.c

1687

static inline void restore_mfc_sr1(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

169

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/switch.c

1692

spu_mfc_sr1_set(spu, csa->priv1.mfc_sr1_RW);

arch/powerpc/platforms/cell/spufs/switch.c

1696

static inline void set_int_route(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1698

struct spu_context *ctx = spu->ctx;

arch/powerpc/platforms/cell/spufs/switch.c

1700

spu_cpu_affinity_set(spu, ctx->last_ran);

arch/powerpc/platforms/cell/spufs/switch.c

1704

struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1711

static inline void restore_spu_runcntl(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1713

struct spu_problem __iomem *prob = spu->problem;

arch/powerpc/platforms/cell/spufs/switch.c

1725

static inline void restore_mfc_cntl(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1727

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/switch.c

1745

static inline void enable_user_access(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1755

static inline void reset_switch_active(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1763

static inline void reenable_interrupts(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1768

spin_lock_irq(&spu->register_lock);

arch/powerpc/platforms/cell/spufs/switch.c

1769

spu_int_mask_set(spu, 0, csa->priv1.int_mask_class0_RW);

arch/powerpc/platforms/cell/spufs/switch.c

1770

spu_int_mask_set(spu, 1, csa->priv1.int_mask_class1_RW);

arch/powerpc/platforms/cell/spufs/switch.c

1771

spu_int_mask_set(spu, 2, csa->priv1.int_mask_class2_RW);

arch/powerpc/platforms/cell/spufs/switch.c

1772

spin_unlock_irq(&spu->register_lock);

arch/powerpc/platforms/cell/spufs/switch.c

1775

static int quiece_spu(struct spu_state *prev, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1787

if (check_spu_isolate(prev, spu)) { /* Step 2. */

arch/powerpc/platforms/cell/spufs/switch.c

1790

disable_interrupts(prev, spu); /* Step 3. */

arch/powerpc/platforms/cell/spufs/switch.c

1791

set_watchdog_timer(prev, spu); /* Step 4. */

arch/powerpc/platforms/cell/spufs/switch.c

1792

inhibit_user_access(prev, spu); /* Step 5. */

arch/powerpc/platforms/cell/spufs/switch.c

1793

if (check_spu_isolate(prev, spu)) { /* Step 6. */

arch/powerpc/platforms/cell/spufs/switch.c

1796

set_switch_pending(prev, spu); /* Step 7. */

arch/powerpc/platforms/cell/spufs/switch.c

1797

save_mfc_cntl(prev, spu); /* Step 8. */

arch/powerpc/platforms/cell/spufs/switch.c

1798

save_spu_runcntl(prev, spu); /* Step 9. */

arch/powerpc/platforms/cell/spufs/switch.c

1799

save_mfc_sr1(prev, spu); /* Step 10. */

arch/powerpc/platforms/cell/spufs/switch.c

1800

save_spu_status(prev, spu); /* Step 11. */

arch/powerpc/platforms/cell/spufs/switch.c

1801

save_mfc_stopped_status(prev, spu); /* Step 12. */

arch/powerpc/platforms/cell/spufs/switch.c

1802

halt_mfc_decr(prev, spu); /* Step 13. */

arch/powerpc/platforms/cell/spufs/switch.c

1803

save_timebase(prev, spu); /* Step 14. */

arch/powerpc/platforms/cell/spufs/switch.c

1804

remove_other_spu_access(prev, spu); /* Step 15. */

arch/powerpc/platforms/cell/spufs/switch.c

1805

do_mfc_mssync(prev, spu); /* Step 16. */

arch/powerpc/platforms/cell/spufs/switch.c

1806

issue_mfc_tlbie(prev, spu); /* Step 17. */

arch/powerpc/platforms/cell/spufs/switch.c

1807

handle_pending_interrupts(prev, spu); /* Step 18. */

arch/powerpc/platforms/cell/spufs/switch.c

1812

static void save_csa(struct spu_state *prev, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1819

save_mfc_queues(prev, spu); /* Step 19. */

arch/powerpc/platforms/cell/spufs/switch.c

1820

save_ppu_querymask(prev, spu); /* Step 20. */

arch/powerpc/platforms/cell/spufs/switch.c

1821

save_ppu_querytype(prev, spu); /* Step 21. */

arch/powerpc/platforms/cell/spufs/switch.c

1822

save_ppu_tagstatus(prev, spu); /* NEW. */

arch/powerpc/platforms/cell/spufs/switch.c

1823

save_mfc_csr_tsq(prev, spu); /* Step 22. */

arch/powerpc/platforms/cell/spufs/switch.c

1824

save_mfc_csr_cmd(prev, spu); /* Step 23. */

arch/powerpc/platforms/cell/spufs/switch.c

1825

save_mfc_csr_ato(prev, spu); /* Step 24. */

arch/powerpc/platforms/cell/spufs/switch.c

1826

save_mfc_tclass_id(prev, spu); /* Step 25. */

arch/powerpc/platforms/cell/spufs/switch.c

1827

set_mfc_tclass_id(prev, spu); /* Step 26. */

arch/powerpc/platforms/cell/spufs/switch.c

1828

save_mfc_cmd(prev, spu); /* Step 26a - moved from 44. */

arch/powerpc/platforms/cell/spufs/switch.c

1829

purge_mfc_queue(prev, spu); /* Step 27. */

arch/powerpc/platforms/cell/spufs/switch.c

1830

wait_purge_complete(prev, spu); /* Step 28. */

arch/powerpc/platforms/cell/spufs/switch.c

1831

setup_mfc_sr1(prev, spu); /* Step 30. */

arch/powerpc/platforms/cell/spufs/switch.c

1832

save_spu_npc(prev, spu); /* Step 31. */

arch/powerpc/platforms/cell/spufs/switch.c

1833

save_spu_privcntl(prev, spu); /* Step 32. */

arch/powerpc/platforms/cell/spufs/switch.c

1834

reset_spu_privcntl(prev, spu); /* Step 33. */

arch/powerpc/platforms/cell/spufs/switch.c

1835

save_spu_lslr(prev, spu); /* Step 34. */

arch/powerpc/platforms/cell/spufs/switch.c

1836

reset_spu_lslr(prev, spu); /* Step 35. */

arch/powerpc/platforms/cell/spufs/switch.c

1837

save_spu_cfg(prev, spu); /* Step 36. */

arch/powerpc/platforms/cell/spufs/switch.c

1838

save_pm_trace(prev, spu); /* Step 37. */

arch/powerpc/platforms/cell/spufs/switch.c

1839

save_mfc_rag(prev, spu); /* Step 38. */

arch/powerpc/platforms/cell/spufs/switch.c

1840

save_ppu_mb_stat(prev, spu); /* Step 39. */

arch/powerpc/platforms/cell/spufs/switch.c

1841

save_ppu_mb(prev, spu); /* Step 40. */

arch/powerpc/platforms/cell/spufs/switch.c

1842

save_ppuint_mb(prev, spu); /* Step 41. */

arch/powerpc/platforms/cell/spufs/switch.c

1843

save_ch_part1(prev, spu); /* Step 42. */

arch/powerpc/platforms/cell/spufs/switch.c

1844

save_spu_mb(prev, spu); /* Step 43. */

arch/powerpc/platforms/cell/spufs/switch.c

1845

reset_ch(prev, spu); /* Step 45. */

arch/powerpc/platforms/cell/spufs/switch.c

1848

static void save_lscsa(struct spu_state *prev, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1856

resume_mfc_queue(prev, spu); /* Step 46. */

arch/powerpc/platforms/cell/spufs/switch.c

1858

setup_mfc_slbs(prev, spu, spu_save_code, sizeof(spu_save_code));

arch/powerpc/platforms/cell/spufs/switch.c

1859

set_switch_active(prev, spu); /* Step 48. */

arch/powerpc/platforms/cell/spufs/switch.c

1860

enable_interrupts(prev, spu); /* Step 49. */

arch/powerpc/platforms/cell/spufs/switch.c

1861

save_ls_16kb(prev, spu); /* Step 50. */

arch/powerpc/platforms/cell/spufs/switch.c

1862

set_spu_npc(prev, spu); /* Step 51. */

arch/powerpc/platforms/cell/spufs/switch.c

1863

set_signot1(prev, spu); /* Step 52. */

arch/powerpc/platforms/cell/spufs/switch.c

1864

set_signot2(prev, spu); /* Step 53. */

arch/powerpc/platforms/cell/spufs/switch.c

1865

send_save_code(prev, spu); /* Step 54. */

arch/powerpc/platforms/cell/spufs/switch.c

1866

set_ppu_querymask(prev, spu); /* Step 55. */

arch/powerpc/platforms/cell/spufs/switch.c

1867

wait_tag_complete(prev, spu); /* Step 56. */

arch/powerpc/platforms/cell/spufs/switch.c

1868

wait_spu_stopped(prev, spu); /* Step 57. */

arch/powerpc/platforms/cell/spufs/switch.c

1871

static void force_spu_isolate_exit(struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1873

struct spu_problem __iomem *prob = spu->problem;

arch/powerpc/platforms/cell/spufs/switch.c

1874

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/switch.c

1882

spu_mfc_sr1_set(spu, MFC_STATE1_MASTER_RUN_CONTROL_MASK);

arch/powerpc/platforms/cell/spufs/switch.c

1903

static void stop_spu_isolate(struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1905

struct spu_problem __iomem *prob = spu->problem;

arch/powerpc/platforms/cell/spufs/switch.c

1912

force_spu_isolate_exit(spu);

arch/powerpc/platforms/cell/spufs/switch.c

1916

static void harvest(struct spu_state *prev, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1924

disable_interrupts(prev, spu); /* Step 2. */

arch/powerpc/platforms/cell/spufs/switch.c

1925

inhibit_user_access(prev, spu); /* Step 3. */

arch/powerpc/platforms/cell/spufs/switch.c

1926

terminate_spu_app(prev, spu); /* Step 4. */

arch/powerpc/platforms/cell/spufs/switch.c

1927

set_switch_pending(prev, spu); /* Step 5. */

arch/powerpc/platforms/cell/spufs/switch.c

1928

stop_spu_isolate(spu); /* NEW. */

arch/powerpc/platforms/cell/spufs/switch.c

1929

remove_other_spu_access(prev, spu); /* Step 6. */

arch/powerpc/platforms/cell/spufs/switch.c

1930

suspend_mfc_and_halt_decr(prev, spu); /* Step 7. */

arch/powerpc/platforms/cell/spufs/switch.c

1931

wait_suspend_mfc_complete(prev, spu); /* Step 8. */

arch/powerpc/platforms/cell/spufs/switch.c

1932

if (!suspend_spe(prev, spu)) /* Step 9. */

arch/powerpc/platforms/cell/spufs/switch.c

1933

clear_spu_status(prev, spu); /* Step 10. */

arch/powerpc/platforms/cell/spufs/switch.c

1934

do_mfc_mssync(prev, spu); /* Step 11. */

arch/powerpc/platforms/cell/spufs/switch.c

1935

issue_mfc_tlbie(prev, spu); /* Step 12. */

arch/powerpc/platforms/cell/spufs/switch.c

1936

handle_pending_interrupts(prev, spu); /* Step 13. */

arch/powerpc/platforms/cell/spufs/switch.c

1937

purge_mfc_queue(prev, spu); /* Step 14. */

arch/powerpc/platforms/cell/spufs/switch.c

1938

wait_purge_complete(prev, spu); /* Step 15. */

arch/powerpc/platforms/cell/spufs/switch.c

1939

reset_spu_privcntl(prev, spu); /* Step 16. */

arch/powerpc/platforms/cell/spufs/switch.c

1940

reset_spu_lslr(prev, spu); /* Step 17. */

arch/powerpc/platforms/cell/spufs/switch.c

1941

setup_mfc_sr1(prev, spu); /* Step 18. */

arch/powerpc/platforms/cell/spufs/switch.c

1942

spu_invalidate_slbs(spu); /* Step 19. */

arch/powerpc/platforms/cell/spufs/switch.c

1943

reset_ch_part1(prev, spu); /* Step 20. */

arch/powerpc/platforms/cell/spufs/switch.c

1944

reset_ch_part2(prev, spu); /* Step 21. */

arch/powerpc/platforms/cell/spufs/switch.c

1945

enable_interrupts(prev, spu); /* Step 22. */

arch/powerpc/platforms/cell/spufs/switch.c

1946

set_switch_active(prev, spu); /* Step 23. */

arch/powerpc/platforms/cell/spufs/switch.c

1947

set_mfc_tclass_id(prev, spu); /* Step 24. */

arch/powerpc/platforms/cell/spufs/switch.c

1948

resume_mfc_queue(prev, spu); /* Step 25. */

arch/powerpc/platforms/cell/spufs/switch.c

1951

static void restore_lscsa(struct spu_state *next, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1959

set_watchdog_timer(next, spu); /* Step 26. */

arch/powerpc/platforms/cell/spufs/switch.c

1960

setup_spu_status_part1(next, spu); /* Step 27. */

arch/powerpc/platforms/cell/spufs/switch.c

1961

setup_spu_status_part2(next, spu); /* Step 28. */

arch/powerpc/platforms/cell/spufs/switch.c

1962

restore_mfc_rag(next, spu); /* Step 29. */

arch/powerpc/platforms/cell/spufs/switch.c

1964

setup_mfc_slbs(next, spu, spu_restore_code, sizeof(spu_restore_code));

arch/powerpc/platforms/cell/spufs/switch.c

1965

set_spu_npc(next, spu); /* Step 31. */

arch/powerpc/platforms/cell/spufs/switch.c

1966

set_signot1(next, spu); /* Step 32. */

arch/powerpc/platforms/cell/spufs/switch.c

1967

set_signot2(next, spu); /* Step 33. */

arch/powerpc/platforms/cell/spufs/switch.c

1968

setup_decr(next, spu); /* Step 34. */

arch/powerpc/platforms/cell/spufs/switch.c

1969

setup_ppu_mb(next, spu); /* Step 35. */

arch/powerpc/platforms/cell/spufs/switch.c

1970

setup_ppuint_mb(next, spu); /* Step 36. */

arch/powerpc/platforms/cell/spufs/switch.c

1971

send_restore_code(next, spu); /* Step 37. */

arch/powerpc/platforms/cell/spufs/switch.c

1972

set_ppu_querymask(next, spu); /* Step 38. */

arch/powerpc/platforms/cell/spufs/switch.c

1973

wait_tag_complete(next, spu); /* Step 39. */

arch/powerpc/platforms/cell/spufs/switch.c

1974

wait_spu_stopped(next, spu); /* Step 40. */

arch/powerpc/platforms/cell/spufs/switch.c

1977

static void restore_csa(struct spu_state *next, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

1984

restore_spu_privcntl(next, spu); /* Step 41. */

arch/powerpc/platforms/cell/spufs/switch.c

1985

restore_status_part1(next, spu); /* Step 42. */

arch/powerpc/platforms/cell/spufs/switch.c

1986

restore_status_part2(next, spu); /* Step 43. */

arch/powerpc/platforms/cell/spufs/switch.c

1987

restore_ls_16kb(next, spu); /* Step 44. */

arch/powerpc/platforms/cell/spufs/switch.c

1988

wait_tag_complete(next, spu); /* Step 45. */

arch/powerpc/platforms/cell/spufs/switch.c

1989

suspend_mfc(next, spu); /* Step 46. */

arch/powerpc/platforms/cell/spufs/switch.c

1990

wait_suspend_mfc_complete(next, spu); /* Step 47. */

arch/powerpc/platforms/cell/spufs/switch.c

1991

issue_mfc_tlbie(next, spu); /* Step 48. */

arch/powerpc/platforms/cell/spufs/switch.c

1992

clear_interrupts(next, spu); /* Step 49. */

arch/powerpc/platforms/cell/spufs/switch.c

1993

restore_mfc_queues(next, spu); /* Step 50. */

arch/powerpc/platforms/cell/spufs/switch.c

1994

restore_ppu_querymask(next, spu); /* Step 51. */

arch/powerpc/platforms/cell/spufs/switch.c

1995

restore_ppu_querytype(next, spu); /* Step 52. */

arch/powerpc/platforms/cell/spufs/switch.c

1996

restore_mfc_csr_tsq(next, spu); /* Step 53. */

arch/powerpc/platforms/cell/spufs/switch.c

1997

restore_mfc_csr_cmd(next, spu); /* Step 54. */

arch/powerpc/platforms/cell/spufs/switch.c

1998

restore_mfc_csr_ato(next, spu); /* Step 55. */

arch/powerpc/platforms/cell/spufs/switch.c

1999

restore_mfc_tclass_id(next, spu); /* Step 56. */

arch/powerpc/platforms/cell/spufs/switch.c

2000

set_llr_event(next, spu); /* Step 57. */

arch/powerpc/platforms/cell/spufs/switch.c

2001

restore_decr_wrapped(next, spu); /* Step 58. */

arch/powerpc/platforms/cell/spufs/switch.c

2002

restore_ch_part1(next, spu); /* Step 59. */

arch/powerpc/platforms/cell/spufs/switch.c

2003

restore_ch_part2(next, spu); /* Step 60. */

arch/powerpc/platforms/cell/spufs/switch.c

2004

restore_spu_lslr(next, spu); /* Step 61. */

arch/powerpc/platforms/cell/spufs/switch.c

2005

restore_spu_cfg(next, spu); /* Step 62. */

arch/powerpc/platforms/cell/spufs/switch.c

2006

restore_pm_trace(next, spu); /* Step 63. */

arch/powerpc/platforms/cell/spufs/switch.c

2007

restore_spu_npc(next, spu); /* Step 64. */

arch/powerpc/platforms/cell/spufs/switch.c

2008

restore_spu_mb(next, spu); /* Step 65. */

arch/powerpc/platforms/cell/spufs/switch.c

2009

check_ppu_mb_stat(next, spu); /* Step 66. */

arch/powerpc/platforms/cell/spufs/switch.c

201

static inline void save_spu_runcntl(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

2010

check_ppuint_mb_stat(next, spu); /* Step 67. */

arch/powerpc/platforms/cell/spufs/switch.c

2011

spu_invalidate_slbs(spu); /* Modified Step 68. */

arch/powerpc/platforms/cell/spufs/switch.c

2012

restore_mfc_sr1(next, spu); /* Step 69. */

arch/powerpc/platforms/cell/spufs/switch.c

2013

set_int_route(next, spu); /* NEW */

arch/powerpc/platforms/cell/spufs/switch.c

2014

restore_other_spu_access(next, spu); /* Step 70. */

arch/powerpc/platforms/cell/spufs/switch.c

2015

restore_spu_runcntl(next, spu); /* Step 71. */

arch/powerpc/platforms/cell/spufs/switch.c

2016

restore_mfc_cntl(next, spu); /* Step 72. */

arch/powerpc/platforms/cell/spufs/switch.c

2017

enable_user_access(next, spu); /* Step 73. */

arch/powerpc/platforms/cell/spufs/switch.c

2018

reset_switch_active(next, spu); /* Step 74. */

arch/powerpc/platforms/cell/spufs/switch.c

2019

reenable_interrupts(next, spu); /* Step 75. */

arch/powerpc/platforms/cell/spufs/switch.c

2022

static int __do_spu_save(struct spu_state *prev, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

203

struct spu_problem __iomem *prob = spu->problem;

arch/powerpc/platforms/cell/spufs/switch.c

2038

rc = quiece_spu(prev, spu); /* Steps 2-16. */

arch/powerpc/platforms/cell/spufs/switch.c

2043

harvest(prev, spu);

arch/powerpc/platforms/cell/spufs/switch.c

2049

save_csa(prev, spu); /* Steps 17-43. */

arch/powerpc/platforms/cell/spufs/switch.c

2050

save_lscsa(prev, spu); /* Steps 44-53. */

arch/powerpc/platforms/cell/spufs/switch.c

2051

return check_save_status(prev, spu); /* Step 54. */

arch/powerpc/platforms/cell/spufs/switch.c

2054

static int __do_spu_restore(struct spu_state *next, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

2069

restore_lscsa(next, spu); /* Steps 24-39. */

arch/powerpc/platforms/cell/spufs/switch.c

2070

rc = check_restore_status(next, spu); /* Step 40. */

arch/powerpc/platforms/cell/spufs/switch.c

2080

restore_csa(next, spu);

arch/powerpc/platforms/cell/spufs/switch.c

2092

int spu_save(struct spu_state *prev, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

2096

acquire_spu_lock(spu); /* Step 1. */

arch/powerpc/platforms/cell/spufs/switch.c

2097

rc = __do_spu_save(prev, spu); /* Steps 2-53. */

arch/powerpc/platforms/cell/spufs/switch.c

2098

release_spu_lock(spu);

arch/powerpc/platforms/cell/spufs/switch.c

2101

__func__, spu->number, rc);

arch/powerpc/platforms/cell/spufs/switch.c

2116

int spu_restore(struct spu_state *new, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

212

static inline void save_mfc_sr1(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

2120

acquire_spu_lock(spu);

arch/powerpc/platforms/cell/spufs/switch.c

2121

harvest(NULL, spu);

arch/powerpc/platforms/cell/spufs/switch.c

2122

spu->slb_replace = 0;

arch/powerpc/platforms/cell/spufs/switch.c

2123

rc = __do_spu_restore(new, spu);

arch/powerpc/platforms/cell/spufs/switch.c

2124

release_spu_lock(spu);

arch/powerpc/platforms/cell/spufs/switch.c

2127

__func__, spu->number, rc);

arch/powerpc/platforms/cell/spufs/switch.c

217

csa->priv1.mfc_sr1_RW = spu_mfc_sr1_get(spu);

arch/powerpc/platforms/cell/spufs/switch.c

220

static inline void save_spu_status(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

222

struct spu_problem __iomem *prob = spu->problem;

arch/powerpc/platforms/cell/spufs/switch.c

247

struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

249

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/switch.c

263

static inline void halt_mfc_decr(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

265

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/switch.c

276

static inline void save_timebase(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

286

struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

294

static inline void do_mfc_mssync(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

296

struct spu_problem __iomem *prob = spu->problem;

arch/powerpc/platforms/cell/spufs/switch.c

307

static inline void issue_mfc_tlbie(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

315

spu_tlb_invalidate(spu);

arch/powerpc/platforms/cell/spufs/switch.c

320

struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

333

static inline void save_mfc_queues(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

335

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/switch.c

366

static inline void save_ppu_querymask(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

368

struct spu_problem __iomem *prob = spu->problem;

arch/powerpc/platforms/cell/spufs/switch.c

377

static inline void save_ppu_querytype(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

379

struct spu_problem __iomem *prob = spu->problem;

arch/powerpc/platforms/cell/spufs/switch.c

388

static inline void save_ppu_tagstatus(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

390

struct spu_problem __iomem *prob = spu->problem;

arch/powerpc/platforms/cell/spufs/switch.c

401

static inline void save_mfc_csr_tsq(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

403

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/switch.c

413

static inline void save_mfc_csr_cmd(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

415

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/switch.c

425

static inline void save_mfc_csr_ato(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

427

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/switch.c

436

static inline void save_mfc_tclass_id(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

442

csa->priv1.mfc_tclass_id_RW = spu_mfc_tclass_id_get(spu);

arch/powerpc/platforms/cell/spufs/switch.c

445

static inline void set_mfc_tclass_id(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

452

spu_mfc_tclass_id_set(spu, 0x10000000);

arch/powerpc/platforms/cell/spufs/switch.c

456

static inline void purge_mfc_queue(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

458

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/switch.c

470

static inline void wait_purge_complete(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

472

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/switch.c

483

static inline void setup_mfc_sr1(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

496

spu_mfc_sr1_set(spu, (MFC_STATE1_MASTER_RUN_CONTROL_MASK |

arch/powerpc/platforms/cell/spufs/switch.c

501

static inline void save_spu_npc(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

503

struct spu_problem __iomem *prob = spu->problem;

arch/powerpc/platforms/cell/spufs/switch.c

511

static inline void save_spu_privcntl(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

513

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/switch.c

521

static inline void reset_spu_privcntl(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

523

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/switch.c

533

static inline void save_spu_lslr(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

535

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/switch.c

543

static inline void reset_spu_lslr(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

545

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/switch.c

555

static inline void save_spu_cfg(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

557

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/switch.c

565

static inline void save_pm_trace(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

573

static inline void save_mfc_rag(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

580

spu_resource_allocation_groupID_get(spu);

arch/powerpc/platforms/cell/spufs/switch.c

582

spu_resource_allocation_enable_get(spu);

arch/powerpc/platforms/cell/spufs/switch.c

585

static inline void save_ppu_mb_stat(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

587

struct spu_problem __iomem *prob = spu->problem;

arch/powerpc/platforms/cell/spufs/switch.c

595

static inline void save_ppu_mb(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

597

struct spu_problem __iomem *prob = spu->problem;

arch/powerpc/platforms/cell/spufs/switch.c

605

static inline void save_ppuint_mb(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

607

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/switch.c

615

static inline void save_ch_part1(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

617

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/switch.c

64

static inline void acquire_spu_lock(struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

641

static inline void save_spu_mb(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

643

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/switch.c

659

static inline void save_mfc_cmd(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

661

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/switch.c

672

static inline void reset_ch(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

674

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/switch.c

692

static inline void resume_mfc_queue(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

694

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/switch.c

703

static inline void setup_mfc_slbs(struct spu_state *csa, struct spu *spu,

arch/powerpc/platforms/cell/spufs/switch.c

720

spu_invalidate_slbs(spu);

arch/powerpc/platforms/cell/spufs/switch.c

721

spu_setup_kernel_slbs(spu, csa->lscsa, code, code_size);

arch/powerpc/platforms/cell/spufs/switch.c

724

static inline void set_switch_active(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

73

static inline void release_spu_lock(struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

735

if (test_bit(SPU_CONTEXT_FAULT_PENDING, &spu->flags))

arch/powerpc/platforms/cell/spufs/switch.c

737

clear_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags);

arch/powerpc/platforms/cell/spufs/switch.c

741

static inline void enable_interrupts(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

754

spin_lock_irq(&spu->register_lock);

arch/powerpc/platforms/cell/spufs/switch.c

755

spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK);

arch/powerpc/platforms/cell/spufs/switch.c

756

spu_int_stat_clear(spu, 1, CLASS1_INTR_MASK);

arch/powerpc/platforms/cell/spufs/switch.c

757

spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK);

arch/powerpc/platforms/cell/spufs/switch.c

758

spu_int_mask_set(spu, 0, 0ul);

arch/powerpc/platforms/cell/spufs/switch.c

759

spu_int_mask_set(spu, 1, class1_mask);

arch/powerpc/platforms/cell/spufs/switch.c

760

spu_int_mask_set(spu, 2, 0ul);

arch/powerpc/platforms/cell/spufs/switch.c

761

spin_unlock_irq(&spu->register_lock);

arch/powerpc/platforms/cell/spufs/switch.c

764

static inline int send_mfc_dma(struct spu *spu, unsigned long ea,

arch/powerpc/platforms/cell/spufs/switch.c

769

struct spu_problem __iomem *prob = spu->problem;

arch/powerpc/platforms/cell/spufs/switch.c

798

static inline void save_ls_16kb(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

81

static inline int check_spu_isolate(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

811

send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);

arch/powerpc/platforms/cell/spufs/switch.c

814

static inline void set_spu_npc(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

816

struct spu_problem __iomem *prob = spu->problem;

arch/powerpc/platforms/cell/spufs/switch.c

83

struct spu_problem __iomem *prob = spu->problem;

arch/powerpc/platforms/cell/spufs/switch.c

831

static inline void set_signot1(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

833

struct spu_problem __iomem *prob = spu->problem;

arch/powerpc/platforms/cell/spufs/switch.c

849

static inline void set_signot2(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

851

struct spu_problem __iomem *prob = spu->problem;

arch/powerpc/platforms/cell/spufs/switch.c

867

static inline void send_save_code(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

880

send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);

arch/powerpc/platforms/cell/spufs/switch.c

883

static inline void set_ppu_querymask(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

885

struct spu_problem __iomem *prob = spu->problem;

arch/powerpc/platforms/cell/spufs/switch.c

896

static inline void wait_tag_complete(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

898

struct spu_problem __iomem *prob = spu->problem;

arch/powerpc/platforms/cell/spufs/switch.c

914

spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK);

arch/powerpc/platforms/cell/spufs/switch.c

915

spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK);

arch/powerpc/platforms/cell/spufs/switch.c

919

static inline void wait_spu_stopped(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

921

struct spu_problem __iomem *prob = spu->problem;

arch/powerpc/platforms/cell/spufs/switch.c

933

spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK);

arch/powerpc/platforms/cell/spufs/switch.c

934

spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK);

arch/powerpc/platforms/cell/spufs/switch.c

938

static inline int check_save_status(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

940

struct spu_problem __iomem *prob = spu->problem;

arch/powerpc/platforms/cell/spufs/switch.c

953

static inline void terminate_spu_app(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

962

struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

964

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/switch.c

97

static inline void disable_interrupts(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

976

struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

978

struct spu_priv2 __iomem *priv2 = spu->priv2;

arch/powerpc/platforms/cell/spufs/switch.c

989

static inline int suspend_spe(struct spu_state *csa, struct spu *spu)

arch/powerpc/platforms/cell/spufs/switch.c

991

struct spu_problem __iomem *prob = spu->problem;

arch/powerpc/platforms/ps3/spu.c

116

static struct spu_pdata *spu_pdata(struct spu *spu)

arch/powerpc/platforms/ps3/spu.c

118

return spu->pdata;

arch/powerpc/platforms/ps3/spu.c

150

static int __init construct_spu(struct spu *spu)

arch/powerpc/platforms/ps3/spu.c

159

&spu_pdata(spu)->priv2_addr, &problem_phys,

arch/powerpc/platforms/ps3/spu.c

161

&spu_pdata(spu)->shadow_addr,

arch/powerpc/platforms/ps3/spu.c

162

&spu_pdata(spu)->spe_id);

arch/powerpc/platforms/ps3/spu.c

163

spu->problem_phys = problem_phys;

arch/powerpc/platforms/ps3/spu.c

164

spu->local_store_phys = local_store_phys;

arch/powerpc/platforms/ps3/spu.c

175

static void spu_unmap(struct spu *spu)

arch/powerpc/platforms/ps3/spu.c

177

iounmap(spu->priv2);

arch/powerpc/platforms/ps3/spu.c

178

iounmap(spu->problem);

arch/powerpc/platforms/ps3/spu.c

179

iounmap((__force u8 __iomem *)spu->local_store);

arch/powerpc/platforms/ps3/spu.c

180

iounmap(spu_pdata(spu)->shadow);

arch/powerpc/platforms/ps3/spu.c

190

static int __init setup_areas(struct spu *spu)

arch/powerpc/platforms/ps3/spu.c

194

spu_pdata(spu)->shadow = ioremap_prot(spu_pdata(spu)->shadow_addr,

arch/powerpc/platforms/ps3/spu.c

197

if (!spu_pdata(spu)->shadow) {

arch/powerpc/platforms/ps3/spu.c

202

spu->local_store = (__force void *)ioremap_wc(spu->local_store_phys, LS_SIZE);

arch/powerpc/platforms/ps3/spu.c

204

if (!spu->local_store) {

arch/powerpc/platforms/ps3/spu.c

210

spu->problem = ioremap(spu->problem_phys,

arch/powerpc/platforms/ps3/spu.c

213

if (!spu->problem) {

arch/powerpc/platforms/ps3/spu.c

218

spu->priv2 = ioremap(spu_pdata(spu)->priv2_addr,

arch/powerpc/platforms/ps3/spu.c

221

if (!spu->priv2) {

arch/powerpc/platforms/ps3/spu.c

226

dump_areas(spu_pdata(spu)->spe_id, spu_pdata(spu)->priv2_addr,

arch/powerpc/platforms/ps3/spu.c

227

spu->problem_phys, spu->local_store_phys,

arch/powerpc/platforms/ps3/spu.c

228

spu_pdata(spu)->shadow_addr);

arch/powerpc/platforms/ps3/spu.c

229

dump_areas(spu_pdata(spu)->spe_id, (unsigned long)spu->priv2,

arch/powerpc/platforms/ps3/spu.c

230

(unsigned long)spu->problem, (unsigned long)spu->local_store,

arch/powerpc/platforms/ps3/spu.c

231

(unsigned long)spu_pdata(spu)->shadow);

arch/powerpc/platforms/ps3/spu.c

236

spu_unmap(spu);

arch/powerpc/platforms/ps3/spu.c

241

static int __init setup_interrupts(struct spu *spu)

arch/powerpc/platforms/ps3/spu.c

245

result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id,

arch/powerpc/platforms/ps3/spu.c

246

0, &spu->irqs[0]);

arch/powerpc/platforms/ps3/spu.c

251

result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id,

arch/powerpc/platforms/ps3/spu.c

252

1, &spu->irqs[1]);

arch/powerpc/platforms/ps3/spu.c

257

result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id,

arch/powerpc/platforms/ps3/spu.c

258

2, &spu->irqs[2]);

arch/powerpc/platforms/ps3/spu.c

266

ps3_spe_irq_destroy(spu->irqs[1]);

arch/powerpc/platforms/ps3/spu.c

268

ps3_spe_irq_destroy(spu->irqs[0]);

arch/powerpc/platforms/ps3/spu.c

270

spu->irqs[0] = spu->irqs[1] = spu->irqs[2] = 0;

arch/powerpc/platforms/ps3/spu.c

274

static int __init enable_spu(struct spu *spu)

arch/powerpc/platforms/ps3/spu.c

278

result = lv1_enable_logical_spe(spu_pdata(spu)->spe_id,

arch/powerpc/platforms/ps3/spu.c

279

spu_pdata(spu)->resource_id);

arch/powerpc/platforms/ps3/spu.c

287

result = setup_areas(spu);

arch/powerpc/platforms/ps3/spu.c

292

result = setup_interrupts(spu);

arch/powerpc/platforms/ps3/spu.c

300

spu_unmap(spu);

arch/powerpc/platforms/ps3/spu.c

302

lv1_disable_logical_spe(spu_pdata(spu)->spe_id, 0);

arch/powerpc/platforms/ps3/spu.c

307

static int ps3_destroy_spu(struct spu *spu)

arch/powerpc/platforms/ps3/spu.c

311

pr_debug("%s:%d spu_%d\n", __func__, __LINE__, spu->number);

arch/powerpc/platforms/ps3/spu.c

313

result = lv1_disable_logical_spe(spu_pdata(spu)->spe_id, 0);

arch/powerpc/platforms/ps3/spu.c

316

ps3_spe_irq_destroy(spu->irqs[2]);

arch/powerpc/platforms/ps3/spu.c

317

ps3_spe_irq_destroy(spu->irqs[1]);

arch/powerpc/platforms/ps3/spu.c

318

ps3_spe_irq_destroy(spu->irqs[0]);

arch/powerpc/platforms/ps3/spu.c

320

spu->irqs[0] = spu->irqs[1] = spu->irqs[2] = 0;

arch/powerpc/platforms/ps3/spu.c

322

spu_unmap(spu);

arch/powerpc/platforms/ps3/spu.c

324

result = lv1_destruct_logical_spe(spu_pdata(spu)->spe_id);

arch/powerpc/platforms/ps3/spu.c

327

kfree(spu->pdata);

arch/powerpc/platforms/ps3/spu.c

328

spu->pdata = NULL;

arch/powerpc/platforms/ps3/spu.c

333

static int __init ps3_create_spu(struct spu *spu, void *data)

arch/powerpc/platforms/ps3/spu.c

337

pr_debug("%s:%d spu_%d\n", __func__, __LINE__, spu->number);

arch/powerpc/platforms/ps3/spu.c

339

spu->pdata = kzalloc_obj(struct spu_pdata);

arch/powerpc/platforms/ps3/spu.c

341

if (!spu->pdata) {

arch/powerpc/platforms/ps3/spu.c

346

spu_pdata(spu)->resource_id = (unsigned long)data;

arch/powerpc/platforms/ps3/spu.c

350

spu_pdata(spu)->cache.sr1 = 0x33;

arch/powerpc/platforms/ps3/spu.c

352

result = construct_spu(spu);

arch/powerpc/platforms/ps3/spu.c

359

result = enable_spu(spu);

arch/powerpc/platforms/ps3/spu.c

367

while (in_be64(&spu_pdata(spu)->shadow->spe_execution_status)

arch/powerpc/platforms/ps3/spu.c

375

ps3_destroy_spu(spu);

arch/powerpc/platforms/ps3/spu.c

461

static void int_mask_and(struct spu *spu, int class, u64 mask)

arch/powerpc/platforms/ps3/spu.c

466

old_mask = spu_int_mask_get(spu, class);

arch/powerpc/platforms/ps3/spu.c

467

spu_int_mask_set(spu, class, old_mask & mask);

arch/powerpc/platforms/ps3/spu.c

470

static void int_mask_or(struct spu *spu, int class, u64 mask)

arch/powerpc/platforms/ps3/spu.c

474

old_mask = spu_int_mask_get(spu, class);

arch/powerpc/platforms/ps3/spu.c

475

spu_int_mask_set(spu, class, old_mask | mask);

arch/powerpc/platforms/ps3/spu.c

478

static void int_mask_set(struct spu *spu, int class, u64 mask)

arch/powerpc/platforms/ps3/spu.c

480

spu_pdata(spu)->cache.masks[class] = mask;

arch/powerpc/platforms/ps3/spu.c

481

lv1_set_spe_interrupt_mask(spu_pdata(spu)->spe_id, class,

arch/powerpc/platforms/ps3/spu.c

482

spu_pdata(spu)->cache.masks[class]);

arch/powerpc/platforms/ps3/spu.c

485

static u64 int_mask_get(struct spu *spu, int class)

arch/powerpc/platforms/ps3/spu.c

487

return spu_pdata(spu)->cache.masks[class];

arch/powerpc/platforms/ps3/spu.c

490

static void int_stat_clear(struct spu *spu, int class, u64 stat)

arch/powerpc/platforms/ps3/spu.c

494

lv1_clear_spe_interrupt_status(spu_pdata(spu)->spe_id, class,

arch/powerpc/platforms/ps3/spu.c

498

static u64 int_stat_get(struct spu *spu, int class)

arch/powerpc/platforms/ps3/spu.c

502

lv1_get_spe_interrupt_status(spu_pdata(spu)->spe_id, class, &stat);

arch/powerpc/platforms/ps3/spu.c

506

static void cpu_affinity_set(struct spu *spu, int cpu)

arch/powerpc/platforms/ps3/spu.c

511

static u64 mfc_dar_get(struct spu *spu)

arch/powerpc/platforms/ps3/spu.c

513

return in_be64(&spu_pdata(spu)->shadow->mfc_dar_RW);

arch/powerpc/platforms/ps3/spu.c

516

static void mfc_dsisr_set(struct spu *spu, u64 dsisr)

arch/powerpc/platforms/ps3/spu.c

521

static u64 mfc_dsisr_get(struct spu *spu)

arch/powerpc/platforms/ps3/spu.c

523

return in_be64(&spu_pdata(spu)->shadow->mfc_dsisr_RW);

arch/powerpc/platforms/ps3/spu.c

526

static void mfc_sdr_setup(struct spu *spu)

arch/powerpc/platforms/ps3/spu.c

531

static void mfc_sr1_set(struct spu *spu, u64 sr1)

arch/powerpc/platforms/ps3/spu.c

538

BUG_ON((sr1 & allowed) != (spu_pdata(spu)->cache.sr1 & allowed));

arch/powerpc/platforms/ps3/spu.c

540

spu_pdata(spu)->cache.sr1 = sr1;

arch/powerpc/platforms/ps3/spu.c

542

spu_pdata(spu)->spe_id,

arch/powerpc/platforms/ps3/spu.c

544

spu_pdata(spu)->cache.sr1);

arch/powerpc/platforms/ps3/spu.c

547

static u64 mfc_sr1_get(struct spu *spu)

arch/powerpc/platforms/ps3/spu.c

549

return spu_pdata(spu)->cache.sr1;

arch/powerpc/platforms/ps3/spu.c

552

static void mfc_tclass_id_set(struct spu *spu, u64 tclass_id)

arch/powerpc/platforms/ps3/spu.c

554

spu_pdata(spu)->cache.tclass_id = tclass_id;

arch/powerpc/platforms/ps3/spu.c

556

spu_pdata(spu)->spe_id,

arch/powerpc/platforms/ps3/spu.c

558

spu_pdata(spu)->cache.tclass_id);

arch/powerpc/platforms/ps3/spu.c

561

static u64 mfc_tclass_id_get(struct spu *spu)

arch/powerpc/platforms/ps3/spu.c

563

return spu_pdata(spu)->cache.tclass_id;

arch/powerpc/platforms/ps3/spu.c

566

static void tlb_invalidate(struct spu *spu)

arch/powerpc/platforms/ps3/spu.c

571

static void resource_allocation_groupID_set(struct spu *spu, u64 id)

arch/powerpc/platforms/ps3/spu.c

576

static u64 resource_allocation_groupID_get(struct spu *spu)

arch/powerpc/platforms/ps3/spu.c

581

static void resource_allocation_enable_set(struct spu *spu, u64 enable)

arch/powerpc/platforms/ps3/spu.c

586

static u64 resource_allocation_enable_get(struct spu *spu)

drivers/crypto/bcm/cipher.c

1046

struct spu_hw *spu = &iproc_priv.spu;

drivers/crypto/bcm/cipher.c

1055

data_padlen = spu->spu_gcm_ccm_pad_len(ctx->cipher.mode,

drivers/crypto/bcm/cipher.c

1059

data_padlen = spu->spu_gcm_ccm_pad_len(ctx->cipher.mode,

drivers/crypto/bcm/cipher.c

1061

assoc_buf_len = spu->spu_assoc_resp_len(ctx->cipher.mode,

drivers/crypto/bcm/cipher.c

1068

data_padlen += spu->spu_wordalign_padlen(assoc_buf_len +

drivers/crypto/bcm/cipher.c

1076

mssg->spu.dst = kmalloc_objs(struct scatterlist, rx_frag_num, rctx->gfp);

drivers/crypto/bcm/cipher.c

1077

if (!mssg->spu.dst)

drivers/crypto/bcm/cipher.c

1080

sg = mssg->spu.dst;

drivers/crypto/bcm/cipher.c

110

return chan_idx % iproc_priv.spu.num_chan;

drivers/crypto/bcm/cipher.c

1125

sg_set_buf(sg, rctx->msg_buf.rx_stat, spu->spu_rx_status_len());

drivers/crypto/bcm/cipher.c

1168

struct spu_hw *spu = &iproc_priv.spu;

drivers/crypto/bcm/cipher.c

1177

mssg->spu.src = kmalloc_objs(struct scatterlist, tx_frag_num, rctx->gfp);

drivers/crypto/bcm/cipher.c

1178

if (!mssg->spu.src)

drivers/crypto/bcm/cipher.c

1181

sg = mssg->spu.src;

drivers/crypto/bcm/cipher.c

1228

stat_len = spu->spu_tx_status_len();

drivers/crypto/bcm/cipher.c

1255

struct spu_hw *spu = &iproc_priv.spu;

drivers/crypto/bcm/cipher.c

1348

if (spu->spu_assoc_resp_len(ctx->cipher.mode,

drivers/crypto/bcm/cipher.c

1354

aead_parms.iv_len = spu->spu_aead_ivlen(ctx->cipher.mode,

drivers/crypto/bcm/cipher.c

1361

aead_parms.aad_pad_len = spu->spu_gcm_ccm_pad_len(ctx->cipher.mode,

drivers/crypto/bcm/cipher.c

1365

aead_parms.data_pad_len = spu->spu_gcm_ccm_pad_len(ctx->cipher.mode,

drivers/crypto/bcm/cipher.c

1373

aead_parms.aad_pad_len = spu->spu_gcm_ccm_pad_len(

drivers/crypto/bcm/cipher.c

1383

spu->spu_gcm_ccm_pad_len(ctx->cipher.mode,

drivers/crypto/bcm/cipher.c

1387

spu->spu_ccm_update_iv(digestsize, &cipher_parms, req->assoclen,

drivers/crypto/bcm/cipher.c

139

struct spu_hw *spu = &iproc_priv.spu;

drivers/crypto/bcm/cipher.c

1399

aead_parms.data_pad_len = spu->spu_gcm_ccm_pad_len(

drivers/crypto/bcm/cipher.c

1404

aead_parms.data_pad_len = spu->spu_gcm_ccm_pad_len(

drivers/crypto/bcm/cipher.c

1427

spu_hdr_len = spu->spu_create_request(rctx->msg_buf.bcm_spu_req_hdr +

drivers/crypto/bcm/cipher.c

1437

stat_pad_len = spu->spu_wordalign_padlen(db_size);

drivers/crypto/bcm/cipher.c

144

mssg->spu.dst = kmalloc_objs(struct scatterlist, rx_frag_num, rctx->gfp);

drivers/crypto/bcm/cipher.c

1444

spu->spu_request_pad(rctx->msg_buf.spu_req_pad,

drivers/crypto/bcm/cipher.c

145

if (!mssg->spu.dst)

drivers/crypto/bcm/cipher.c

1450

spu->spu_dump_msg_hdr(rctx->msg_buf.bcm_spu_req_hdr + BCM_HDR_LEN,

drivers/crypto/bcm/cipher.c

148

sg = mssg->spu.dst;

drivers/crypto/bcm/cipher.c

1503

if (spu->spu_tx_status_len())

drivers/crypto/bcm/cipher.c

1525

struct spu_hw *spu = &iproc_priv.spu;

drivers/crypto/bcm/cipher.c

1535

payload_len = spu->spu_payload_length(rctx->msg_buf.spu_resp_hdr);

drivers/crypto/bcm/cipher.c

155

spu->spu_xts_tweak_in_payload())

drivers/crypto/bcm/cipher.c

1588

kfree(mssg->spu.src);

drivers/crypto/bcm/cipher.c

1589

kfree(mssg->spu.dst);

drivers/crypto/bcm/cipher.c

1621

struct spu_hw *spu = &iproc_priv.spu;

drivers/crypto/bcm/cipher.c

1635

err = spu->spu_status_process(rctx->msg_buf.rx_stat);

drivers/crypto/bcm/cipher.c

172

sg_set_buf(sg, rctx->msg_buf.rx_stat, spu->spu_rx_status_len());

drivers/crypto/bcm/cipher.c

1816

struct spu_hw *spu = &iproc_priv.spu;

drivers/crypto/bcm/cipher.c

1854

if (spu->spu_type == SPU_TYPE_SPUM)

drivers/crypto/bcm/cipher.c

1856

else if (spu->spu_type == SPU_TYPE_SPU2)

drivers/crypto/bcm/cipher.c

1872

spu->spu_cipher_req_init(ctx->bcm_spu_req_hdr + BCM_HDR_LEN,

drivers/crypto/bcm/cipher.c

1875

ctx->spu_resp_hdr_len = spu->spu_response_hdr_len(ctx->authkeylen,

drivers/crypto/bcm/cipher.c

1924

(iproc_priv.spu.spu_type == SPU_TYPE_SPU2)) {

drivers/crypto/bcm/cipher.c

1955

struct spu_hw *spu = &iproc_priv.spu;

drivers/crypto/bcm/cipher.c

1977

ctx->spu_resp_hdr_len = spu->spu_response_hdr_len(ctx->authkeylen, 0,

drivers/crypto/bcm/cipher.c

1998

struct spu_hw *spu = &iproc_priv.spu;

drivers/crypto/bcm/cipher.c

2000

if (spu->spu_type == SPU_TYPE_SPU2)

drivers/crypto/bcm/cipher.c

201

struct spu_hw *spu = &iproc_priv.spu;

drivers/crypto/bcm/cipher.c

207

mssg->spu.src = kmalloc_objs(struct scatterlist, tx_frag_num, rctx->gfp);

drivers/crypto/bcm/cipher.c

208

if (unlikely(!mssg->spu.src))

drivers/crypto/bcm/cipher.c

211

sg = mssg->spu.src;

drivers/crypto/bcm/cipher.c

219

spu->spu_xts_tweak_in_payload())

drivers/crypto/bcm/cipher.c

234

stat_len = spu->spu_tx_status_len();

drivers/crypto/bcm/cipher.c

2389

if (iproc_priv.spu.spu_type == SPU_TYPE_SPUM) {

drivers/crypto/bcm/cipher.c

2477

if (iproc_priv.spu.spu_type == SPU_TYPE_SPU2) {

drivers/crypto/bcm/cipher.c

2505

struct spu_hw *spu = &iproc_priv.spu;

drivers/crypto/bcm/cipher.c

2526

(spu->spu_type == SPU_TYPE_SPUM) &&

drivers/crypto/bcm/cipher.c

2539

(spu->spu_subtype == SPU_SUBTYPE_SPUM_NSP) &&

drivers/crypto/bcm/cipher.c

2560

if (spu->spu_type == SPU_TYPE_SPUM)

drivers/crypto/bcm/cipher.c

2720

struct spu_hw *spu = &iproc_priv.spu;

drivers/crypto/bcm/cipher.c

2796

ctx->spu_resp_hdr_len = spu->spu_response_hdr_len(ctx->authkeylen,

drivers/crypto/bcm/cipher.c

2815

struct spu_hw *spu = &iproc_priv.spu;

drivers/crypto/bcm/cipher.c

2864

ctx->spu_resp_hdr_len = spu->spu_response_hdr_len(ctx->authkeylen,

drivers/crypto/bcm/cipher.c

300

struct spu_hw *spu = &iproc_priv.spu;

drivers/crypto/bcm/cipher.c

400

spu->spu_cipher_req_finish(rctx->msg_buf.bcm_spu_req_hdr + BCM_HDR_LEN,

drivers/crypto/bcm/cipher.c

406

stat_pad_len = spu->spu_wordalign_padlen(chunksize);

drivers/crypto/bcm/cipher.c

4088

struct spu_hw *spu = &iproc_priv.spu;

drivers/crypto/bcm/cipher.c

4098

ctx->max_payload = spu->spu_ctx_max_payload(ctx->cipher.alg,

drivers/crypto/bcm/cipher.c

412

spu->spu_request_pad(rctx->msg_buf.spu_req_pad, 0,

drivers/crypto/bcm/cipher.c

417

spu->spu_dump_msg_hdr(rctx->msg_buf.bcm_spu_req_hdr + BCM_HDR_LEN,

drivers/crypto/bcm/cipher.c

4230

struct spu_hw *spu = &iproc_priv.spu;

drivers/crypto/bcm/cipher.c

4234

spu->spu_dump_msg_hdr = spum_dump_msg_hdr;

drivers/crypto/bcm/cipher.c

4235

spu->spu_payload_length = spum_payload_length;

drivers/crypto/bcm/cipher.c

4236

spu->spu_response_hdr_len = spum_response_hdr_len;

drivers/crypto/bcm/cipher.c

4237

spu->spu_hash_pad_len = spum_hash_pad_len;

drivers/crypto/bcm/cipher.c

4238

spu->spu_gcm_ccm_pad_len = spum_gcm_ccm_pad_len;

drivers/crypto/bcm/cipher.c

4239

spu->spu_assoc_resp_len = spum_assoc_resp_len;

drivers/crypto/bcm/cipher.c

4240

spu->spu_aead_ivlen = spum_aead_ivlen;

drivers/crypto/bcm/cipher.c

4241

spu->spu_hash_type = spum_hash_type;

drivers/crypto/bcm/cipher.c

4242

spu->spu_digest_size = spum_digest_size;

drivers/crypto/bcm/cipher.c

4243

spu->spu_create_request = spum_create_request;

drivers/crypto/bcm/cipher.c

4244

spu->spu_cipher_req_init = spum_cipher_req_init;

drivers/crypto/bcm/cipher.c

4245

spu->spu_cipher_req_finish = spum_cipher_req_finish;

drivers/crypto/bcm/cipher.c

4246

spu->spu_request_pad = spum_request_pad;

drivers/crypto/bcm/cipher.c

4247

spu->spu_tx_status_len = spum_tx_status_len;

drivers/crypto/bcm/cipher.c

4248

spu->spu_rx_status_len = spum_rx_status_len;

drivers/crypto/bcm/cipher.c

4249

spu->spu_status_process = spum_status_process;

drivers/crypto/bcm/cipher.c

4250

spu->spu_xts_tweak_in_payload = spum_xts_tweak_in_payload;

drivers/crypto/bcm/cipher.c

4251

spu->spu_ccm_update_iv = spum_ccm_update_iv;

drivers/crypto/bcm/cipher.c

4252

spu->spu_wordalign_padlen = spum_wordalign_padlen;

drivers/crypto/bcm/cipher.c

4254

spu->spu_ctx_max_payload = spum_ns2_ctx_max_payload;

drivers/crypto/bcm/cipher.c

4256

spu->spu_ctx_max_payload = spum_nsp_ctx_max_payload;

drivers/crypto/bcm/cipher.c

4259

spu->spu_dump_msg_hdr = spu2_dump_msg_hdr;

drivers/crypto/bcm/cipher.c

4260

spu->spu_ctx_max_payload = spu2_ctx_max_payload;

drivers/crypto/bcm/cipher.c

4261

spu->spu_payload_length = spu2_payload_length;

drivers/crypto/bcm/cipher.c

4262

spu->spu_response_hdr_len = spu2_response_hdr_len;

drivers/crypto/bcm/cipher.c

4263

spu->spu_hash_pad_len = spu2_hash_pad_len;

drivers/crypto/bcm/cipher.c

4264

spu->spu_gcm_ccm_pad_len = spu2_gcm_ccm_pad_len;

drivers/crypto/bcm/cipher.c

4265

spu->spu_assoc_resp_len = spu2_assoc_resp_len;

drivers/crypto/bcm/cipher.c

4266

spu->spu_aead_ivlen = spu2_aead_ivlen;

drivers/crypto/bcm/cipher.c

4267

spu->spu_hash_type = spu2_hash_type;

drivers/crypto/bcm/cipher.c

4268

spu->spu_digest_size = spu2_digest_size;

drivers/crypto/bcm/cipher.c

4269

spu->spu_create_request = spu2_create_request;

drivers/crypto/bcm/cipher.c

4270

spu->spu_cipher_req_init = spu2_cipher_req_init;

drivers/crypto/bcm/cipher.c

4271

spu->spu_cipher_req_finish = spu2_cipher_req_finish;

drivers/crypto/bcm/cipher.c

4272

spu->spu_request_pad = spu2_request_pad;

drivers/crypto/bcm/cipher.c

4273

spu->spu_tx_status_len = spu2_tx_status_len;

drivers/crypto/bcm/cipher.c

4274

spu->spu_rx_status_len = spu2_rx_status_len;

drivers/crypto/bcm/cipher.c

4275

spu->spu_status_process = spu2_status_process;

drivers/crypto/bcm/cipher.c

4276

spu->spu_xts_tweak_in_payload = spu2_xts_tweak_in_payload;

drivers/crypto/bcm/cipher.c

4277

spu->spu_ccm_update_iv = spu2_ccm_update_iv;

drivers/crypto/bcm/cipher.c

4278

spu->spu_wordalign_padlen = spu2_wordalign_padlen;

drivers/crypto/bcm/cipher.c

4295

iproc_priv.mbox = devm_kcalloc(dev, iproc_priv.spu.num_chan,

drivers/crypto/bcm/cipher.c

4307

for (i = 0; i < iproc_priv.spu.num_chan; i++) {

drivers/crypto/bcm/cipher.c

4321

for (i = 0; i < iproc_priv.spu.num_chan; i++) {

drivers/crypto/bcm/cipher.c

4333

for (i = 0; i < iproc_priv.spu.num_chan; i++)

drivers/crypto/bcm/cipher.c

4344

atomic_set(&iproc_priv.next_chan, (int)iproc_priv.spu.num_chan);

drivers/crypto/bcm/cipher.c

435

spu->spu_xts_tweak_in_payload())

drivers/crypto/bcm/cipher.c

4396

struct spu_hw *spu = &iproc_priv.spu;

drivers/crypto/bcm/cipher.c

4403

(spu->spu_type == SPU_TYPE_SPUM))

drivers/crypto/bcm/cipher.c

4408

(spu->spu_subtype != SPU_SUBTYPE_SPU2_V2))

drivers/crypto/bcm/cipher.c

445

if (spu->spu_tx_status_len())

drivers/crypto/bcm/cipher.c

449

spu->spu_xts_tweak_in_payload())

drivers/crypto/bcm/cipher.c

4577

struct spu_hw *spu = &iproc_priv.spu;

drivers/crypto/bcm/cipher.c

4584

spu->num_chan = of_count_phandle_with_args(dn, "mboxes", "#mbox-cells");

drivers/crypto/bcm/cipher.c

4592

spu->spu_type = matched_spu_type->type;

drivers/crypto/bcm/cipher.c

4593

spu->spu_subtype = matched_spu_type->subtype;

drivers/crypto/bcm/cipher.c

4598

spu->reg_vbase[i] = devm_ioremap_resource(dev, spu_ctrl_regs);

drivers/crypto/bcm/cipher.c

4599

if (IS_ERR(spu->reg_vbase[i])) {

drivers/crypto/bcm/cipher.c

4600

err = PTR_ERR(spu->reg_vbase[i]);

drivers/crypto/bcm/cipher.c

4603

spu->reg_vbase[i] = NULL;

drivers/crypto/bcm/cipher.c

4607

spu->num_spu = i;

drivers/crypto/bcm/cipher.c

4608

dev_dbg(dev, "Device has %d SPUs", spu->num_spu);

drivers/crypto/bcm/cipher.c

4616

struct spu_hw *spu = &iproc_priv.spu;

drivers/crypto/bcm/cipher.c

4631

if (spu->spu_type == SPU_TYPE_SPUM)

drivers/crypto/bcm/cipher.c

4633

else if (spu->spu_type == SPU_TYPE_SPU2)

drivers/crypto/bcm/cipher.c

4636

spu_functions_register(dev, spu->spu_type, spu->spu_subtype);

drivers/crypto/bcm/cipher.c

471

struct spu_hw *spu = &iproc_priv.spu;

drivers/crypto/bcm/cipher.c

478

payload_len = spu->spu_payload_length(rctx->msg_buf.spu_resp_hdr);

drivers/crypto/bcm/cipher.c

485

spu->spu_xts_tweak_in_payload() &&

drivers/crypto/bcm/cipher.c

529

struct spu_hw *spu = &iproc_priv.spu;

drivers/crypto/bcm/cipher.c

533

mssg->spu.dst = kmalloc_objs(struct scatterlist, rx_frag_num, rctx->gfp);

drivers/crypto/bcm/cipher.c

534

if (!mssg->spu.dst)

drivers/crypto/bcm/cipher.c

537

sg = mssg->spu.dst;

drivers/crypto/bcm/cipher.c

549

sg_set_buf(sg, rctx->msg_buf.rx_stat, spu->spu_rx_status_len());

drivers/crypto/bcm/cipher.c

582

struct spu_hw *spu = &iproc_priv.spu;

drivers/crypto/bcm/cipher.c

587

mssg->spu.src = kmalloc_objs(struct scatterlist, tx_frag_num, rctx->gfp);

drivers/crypto/bcm/cipher.c

588

if (!mssg->spu.src)

drivers/crypto/bcm/cipher.c

591

sg = mssg->spu.src;

drivers/crypto/bcm/cipher.c

614

stat_len = spu->spu_tx_status_len();

drivers/crypto/bcm/cipher.c

651

struct spu_hw *spu = &iproc_priv.spu;

drivers/crypto/bcm/cipher.c

772

hash_parms.type = spu->spu_hash_type(rctx->total_sent);

drivers/crypto/bcm/cipher.c

774

digestsize = spu->spu_digest_size(ctx->digestsize, ctx->auth.alg,

drivers/crypto/bcm/cipher.c

784

hash_parms.pad_len = spu->spu_hash_pad_len(hash_parms.alg,

drivers/crypto/bcm/cipher.c

815

spu_hdr_len = spu->spu_create_request(rctx->msg_buf.bcm_spu_req_hdr +

drivers/crypto/bcm/cipher.c

830

data_pad_len = spu->spu_gcm_ccm_pad_len(ctx->cipher.mode, chunksize);

drivers/crypto/bcm/cipher.c

833

if (spu->spu_tx_status_len())

drivers/crypto/bcm/cipher.c

834

stat_pad_len = spu->spu_wordalign_padlen(db_size);

drivers/crypto/bcm/cipher.c

840

spu->spu_request_pad(rctx->msg_buf.spu_req_pad, data_pad_len,

drivers/crypto/bcm/cipher.c

846

spu->spu_dump_msg_hdr(rctx->msg_buf.bcm_spu_req_hdr + BCM_HDR_LEN,

drivers/crypto/bcm/cipher.c

869

if (spu->spu_tx_status_len())

drivers/crypto/bcm/cipher.c

942

struct spu_hw *spu = &iproc_priv.spu;

drivers/crypto/bcm/cipher.c

950

if (spu->spu_type == SPU_TYPE_SPUM) {

drivers/crypto/bcm/cipher.h

423

struct spu_hw spu;

drivers/crypto/bcm/util.c

373

ipriv->spu.num_spu);

drivers/crypto/bcm/util.c

455

if (ipriv->spu.spu_type == SPU_TYPE_SPUM)

drivers/crypto/bcm/util.c

456

for (i = 0; i < ipriv->spu.num_spu; i++) {

drivers/crypto/bcm/util.c

457

spu_ofifo_ctrl = ioread32(ipriv->spu.reg_vbase[i] +

drivers/mailbox/bcm-flexrm-mailbox.c

567

if (!msg->spu.src || !msg->spu.dst)

drivers/mailbox/bcm-flexrm-mailbox.c

569

for (sg = msg->spu.src; sg; sg = sg_next(sg)) {

drivers/mailbox/bcm-flexrm-mailbox.c

578

for (sg = msg->spu.dst; sg; sg = sg_next(sg)) {

drivers/mailbox/bcm-flexrm-mailbox.c

595

struct scatterlist *src_sg = msg->spu.src, *dst_sg = msg->spu.dst;

drivers/mailbox/bcm-flexrm-mailbox.c

622

rc = dma_map_sg(dev, msg->spu.src, sg_nents(msg->spu.src),

drivers/mailbox/bcm-flexrm-mailbox.c

627

rc = dma_map_sg(dev, msg->spu.dst, sg_nents(msg->spu.dst),

drivers/mailbox/bcm-flexrm-mailbox.c

630

dma_unmap_sg(dev, msg->spu.src, sg_nents(msg->spu.src),

drivers/mailbox/bcm-flexrm-mailbox.c

640

dma_unmap_sg(dev, msg->spu.dst, sg_nents(msg->spu.dst),

drivers/mailbox/bcm-flexrm-mailbox.c

642

dma_unmap_sg(dev, msg->spu.src, sg_nents(msg->spu.src),

drivers/mailbox/bcm-flexrm-mailbox.c

654

struct scatterlist *src_sg = msg->spu.src, *dst_sg = msg->spu.dst;

drivers/mailbox/bcm-pdc-mailbox.c

1205

src_nent = sg_nents(mssg->spu.src);

drivers/mailbox/bcm-pdc-mailbox.c

1207

nent = dma_map_sg(dev, mssg->spu.src, src_nent, DMA_TO_DEVICE);

drivers/mailbox/bcm-pdc-mailbox.c

1212

dst_nent = sg_nents(mssg->spu.dst);

drivers/mailbox/bcm-pdc-mailbox.c

1214

nent = dma_map_sg(dev, mssg->spu.dst, dst_nent,

drivers/mailbox/bcm-pdc-mailbox.c

1217

dma_unmap_sg(dev, mssg->spu.src, src_nent,

drivers/mailbox/bcm-pdc-mailbox.c

1232

tx_desc_req = pdc_desc_count(mssg->spu.src);

drivers/mailbox/bcm-pdc-mailbox.c

1233

rx_desc_req = pdc_desc_count(mssg->spu.dst);

drivers/mailbox/bcm-pdc-mailbox.c

1238

err = pdc_rx_list_init(pdcs, mssg->spu.dst, mssg->ctx);

drivers/mailbox/bcm-pdc-mailbox.c

1239

err |= pdc_rx_list_sg_add(pdcs, mssg->spu.dst);

drivers/mailbox/bcm-pdc-mailbox.c

1242

err |= pdc_tx_list_sg_add(pdcs, mssg->spu.src);

include/linux/mailbox/brcm-message.h

49

} spu;