scu_base
int scu_get_cpu_power_mode(void __iomem *scu_base, unsigned int logical_cpu);
static inline unsigned int scu_get_core_count(void __iomem *scu_base)
static inline int scu_power_mode(void __iomem *scu_base, unsigned int mode)
static inline int scu_cpu_power_enable(void __iomem *scu_base,
static inline int scu_get_cpu_power_mode(void __iomem *scu_base,
void scu_enable(void __iomem *scu_base);
static inline void scu_enable(void __iomem *scu_base) {}
return scu_set_power_mode_internal(scu_base, smp_processor_id(), mode);
int scu_cpu_power_enable(void __iomem *scu_base, unsigned int cpu)
return scu_set_power_mode_internal(scu_base, cpu, SCU_PM_NORMAL);
int scu_get_cpu_power_mode(void __iomem *scu_base, unsigned int logical_cpu)
val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu);
unsigned int __init scu_get_core_count(void __iomem *scu_base)
unsigned int ncores = readl_relaxed(scu_base + SCU_CONFIG);
void scu_enable(void __iomem *scu_base)
scu_ctrl = readl_relaxed(scu_base + 0x30);
writel_relaxed(scu_ctrl | 0x1, scu_base + 0x30);
scu_ctrl = readl_relaxed(scu_base + SCU_CTRL);
writel_relaxed(scu_ctrl, scu_base + SCU_CTRL);
static int scu_set_power_mode_internal(void __iomem *scu_base,
val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu);
writeb_relaxed(val, scu_base + SCU_CPU_STATUS + cpu);
int scu_power_mode(void __iomem *scu_base, unsigned int mode)
void __iomem *scu_base;
scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE);
if (!scu_base) {
scu_enable(scu_base);
ncores = scu_base ? scu_get_core_count(scu_base) : 1;
iounmap(scu_base); /* That's the last we'll need of this */
void __iomem *scu_base;
scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE);
if (!scu_base) {
scu_enable(scu_base);
iounmap(scu_base); /* That's the last we'll need of this */
void __iomem *scu_base;
scu_base = of_iomap(np, 0);
if (!scu_base)
scu_enable(scu_base);
iounmap(scu_base);
static void __iomem *scu_base;
if (!scu_base) {
scu_base = of_iomap(np, 0);
scu_base = ioremap(scu_a9_get_base(), SZ_4K);
scu_enable(scu_base);
void __iomem *scu_base = NULL;
scu_base = ioremap(base, SZ_4K);
if (!scu_base) {
scu_enable(scu_base);
iounmap(scu_base);
static void __iomem *scu_base;
scu_base = IMX_IO_ADDRESS(base);
ncores = scu_get_core_count(scu_base);
scu_enable(scu_base);
scu_enable(scu_base);
scu_cpu_power_enable(scu_base, cpu);
scu_power_mode(scu_base, SCU_PM_POWEROFF);
power_mode = scu_get_cpu_power_mode(scu_base, cpu);
static void __iomem *scu_base;
power_mode = scu_get_cpu_power_mode(scu_base, cpu);
scu_base = of_iomap(node, 0);
if (!scu_base) {
static void __iomem *scu_base;
scu_base = of_iomap(np, 0);
scu_enable(scu_base);
return scu_base;
void __iomem *scu_base;
scu_base = of_iomap(scu_np, 0);
if (!scu_base) {
scu_enable(scu_base);
iounmap(scu_base);
cfg.scu_base = OMAP2_L4_IO_ADDRESS(scu_a9_get_base());
BUG_ON(!cfg.scu_base);
ncores = scu_get_core_count(cfg.scu_base);
if (cfg.scu_base)
scu_enable(cfg.scu_base);
void __iomem *scu_base;
return cfg.scu_base;
scu_power_mode(scu_base, SCU_PM_POWEROFF);
scu_power_mode(scu_base, SCU_PM_NORMAL);
if (!scu_base)
scu_power_mode(scu_base, SCU_PM_DORMANT);
scu_power_mode(scu_base, SCU_PM_NORMAL);
static void __iomem *scu_base;
scu_base = ioremap(scu_a9_get_base(), SZ_256);
if (!scu_base)
unsigned int i, ncores = scu_get_core_count(scu_base);
scu_enable(scu_base);
static void __iomem *scu_base = IOMEM(VA_SCU_BASE);
void __iomem *scu_base;
scu_base = of_iomap(np, 0);
scu_enable(scu_base);
static void __iomem *scu_base;
scu_base = of_iomap(np, 0);
if (!scu_base) {
scu_enable(scu_base);
ncores = scu_get_core_count(scu_base);
iounmap(scu_base);
void __iomem *scu_base;
scu_base = of_iomap(np, 0);
if (!scu_base) {
scu_enable(scu_base);
ncores = scu_get_core_count(scu_base);
iounmap(scu_base);
static void __iomem *scu_base;
scu_base + ASPEED_CLK_SELECTION, 15, 0,
0, scu_base + ASPEED_CLK_SELECTION, 12, 3, 0,
scu_base + ASPEED_CLK_SELECTION, 16, 3, 0,
scu_base + ASPEED_MAC_CLK_DLY, 29, 0,
scu_base + ASPEED_MAC_CLK_DLY, 30, 0,
scu_base + ASPEED_CLK_SELECTION, 20, 3, 0,
scu_base + ASPEED_CLK_SELECTION_2, 0, 2, 0,
scu_base + ASPEED_CLK_SELECTION, 2, 0x3, 0,
scu_base + ASPEED_CLK_SELECTION, 28,
scu_base + ASPEED_CLK_SELECTION, 23, 3, 0,
scu_base = of_iomap(np, 0);
if (!scu_base)
static void scu_busy_loop(void __iomem *scu_base)
status = readl(scu_base + 0x04);
status = readl(scu_base + 0x04);
void __iomem *scu_base,
ihost->scu_registers = scu_base;
status = sci_controller_construct(ihost, scu_base(ihost), smu_base(ihost));
struct regmap *scu_base;
scu_base = syscon_regmap_lookup_by_compatible(scu.compatible);
if (IS_ERR(scu_base)) {
ret = regmap_read(scu_base, scu.reset_status_reg, &status);
ret = regmap_read(scu_base, scu.reset_status_reg, &status);
regmap_write(scu_base, scu.reset_status_reg, status);
regmap_write(scu_base, scu.reset_status_reg,