set_speed
set_speed(dce_i2c_hw, dce_i2c_hw->ctx->dc->caps.i2c_speed_in_khz);
set_speed(dce_i2c_hw, dce_i2c_hw->ctx->dc->caps.i2c_speed_in_khz_hdcp);
set_speed(dce_i2c_hw, cmd->speed);
if (master->ops->set_speed) {
ret = master->ops->set_speed(master, I3C_OPEN_DRAIN_SLOW_SPEED);
if (master->ops->set_speed) {
ret = master->ops->set_speed(master, I3C_OPEN_DRAIN_NORMAL_SPEED);
.set_speed = svc_i3c_master_set_speed,
hw_if->set_speed = xgbe_set_speed;
pdata->hw_if.set_speed(pdata, SPEED_10000);
pdata->hw_if.set_speed(pdata, SPEED_2500);
pdata->hw_if.set_speed(pdata, SPEED_1000);
pdata->hw_if.set_speed(pdata, SPEED_10000);
pdata->hw_if.set_speed(pdata, SPEED_1000);
pdata->hw_if.set_speed(pdata, SPEED_1000);
pdata->hw_if.set_speed(pdata, SPEED_10);
pdata->hw_if.set_speed(pdata, SPEED_1000);
int (*set_speed)(struct xgbe_prv_data *, int);
mac_ops->set_speed(pdata);
.set_speed = xgene_gmac_set_speed,
void (*set_speed)(struct xgene_enet_pdata *pdata);
.set_speed = xgene_sgmac_set_speed,
goto set_speed;
goto set_speed;
goto set_speed;
goto set_speed;
set_speed:
void (*set_speed)(void __iomem *ioaddr, unsigned char speed);
.set_speed = sxgbe_core_set_speed,
priv->hw->mac->set_speed(priv->ioaddr, speed);
.set_speed = rk_set_clk_mac_speed,
if (bsp_priv->ops->set_speed) {
ret = bsp_priv->ops->set_speed(bsp_priv, interface, speed);
.set_speed = rk_set_clk_mac_speed,
int (*set_speed)(struct rk_priv_data *bsp_priv,
.set_speed = rk_set_clk_mac_speed,
set_speed(scc);
set_speed(scc); /* set baudrate */
.set_speed = imx_hsio_set_speed,
.set_speed = serdes_set_speed,
.set_speed = sparx5_serdes_set_speed,
if (!phy || !phy->ops->set_speed)
ret = phy->ops->set_speed(phy, speed);
.set_speed = qcom_dwmac_sgmii_phy_set_speed,
.set_speed = r8a779f0_eth_serdes_set_speed,
set_speed:
goto set_speed;
int (*set_speed)(struct i3c_master_controller *master, enum i3c_open_drain_speed speed);
int (*set_speed)(struct phy *phy, int speed);