set_reg_val
kvmppc_set_dar(vcpu, set_reg_val(id, *val));
kvmppc_set_dsisr(vcpu, set_reg_val(id, *val));
kvmppc_set_fpr(vcpu, i, set_reg_val(id, *val));
vcpu->arch.fp.fpscr = set_reg_val(id, *val);
r = kvmppc_xive_set_icp(vcpu, set_reg_val(id, *val));
r = kvmppc_xics_set_icp(vcpu, set_reg_val(id, *val));
kvmppc_set_fpscr(vcpu, set_reg_val(id, *val));
kvmppc_set_tar(vcpu, set_reg_val(id, *val));
kvmppc_set_ebbhr(vcpu, set_reg_val(id, *val));
kvmppc_set_ebbrr(vcpu, set_reg_val(id, *val));
kvmppc_set_bescr(vcpu, set_reg_val(id, *val));
kvmppc_set_ic(vcpu, set_reg_val(id, *val));
if (set_reg_val(id, *val))
vcpu->arch.dabr = set_reg_val(id, *val);
vcpu->arch.dabrx = set_reg_val(id, *val) & ~DABRX_HYP;
kvmppc_set_dscr_hv(vcpu, set_reg_val(id, *val));
kvmppc_set_purr_hv(vcpu, set_reg_val(id, *val));
kvmppc_set_spurr_hv(vcpu, set_reg_val(id, *val));
kvmppc_set_amr_hv(vcpu, set_reg_val(id, *val));
kvmppc_set_uamor_hv(vcpu, set_reg_val(id, *val));
kvmppc_set_mmcr_hv(vcpu, i, set_reg_val(id, *val));
kvmppc_set_mmcr_hv(vcpu, 2, set_reg_val(id, *val));
kvmppc_set_mmcra_hv(vcpu, set_reg_val(id, *val));
vcpu->arch.mmcrs = set_reg_val(id, *val);
kvmppc_set_mmcr_hv(vcpu, 3, set_reg_val(id, *val));
kvmppc_set_pmc_hv(vcpu, i, set_reg_val(id, *val));
vcpu->arch.spmc[i] = set_reg_val(id, *val);
kvmppc_set_siar_hv(vcpu, set_reg_val(id, *val));
kvmppc_set_sdar_hv(vcpu, set_reg_val(id, *val));
kvmppc_set_sier_hv(vcpu, 0, set_reg_val(id, *val));
kvmppc_set_sier_hv(vcpu, 1, set_reg_val(id, *val));
kvmppc_set_sier_hv(vcpu, 2, set_reg_val(id, *val));
kvmppc_set_iamr_hv(vcpu, set_reg_val(id, *val));
kvmppc_set_pspb_hv(vcpu, set_reg_val(id, *val));
vcpu->arch.doorbell_request = set_reg_val(id, *val) & 1;
vcpu->arch.vcore->dpdes = set_reg_val(id, *val);
kvmppc_set_vtb(vcpu, set_reg_val(id, *val));
kvmppc_set_dawr0_hv(vcpu, set_reg_val(id, *val));
kvmppc_set_dawrx0_hv(vcpu, set_reg_val(id, *val) & ~DAWRX_HYP);
kvmppc_set_dawr1_hv(vcpu, set_reg_val(id, *val));
kvmppc_set_dawrx1_hv(vcpu, set_reg_val(id, *val) & ~DAWRX_HYP);
kvmppc_set_dexcr_hv(vcpu, set_reg_val(id, *val));
kvmppc_set_hashkeyr_hv(vcpu, set_reg_val(id, *val));
kvmppc_set_hashpkeyr_hv(vcpu, set_reg_val(id, *val));
kvmppc_set_ciabr_hv(vcpu, set_reg_val(id, *val));
vcpu->arch.csigr = set_reg_val(id, *val);
vcpu->arch.tacr = set_reg_val(id, *val);
vcpu->arch.tcscr = set_reg_val(id, *val);
kvmppc_set_pid(vcpu, set_reg_val(id, *val));
vcpu->arch.acop = set_reg_val(id, *val);
kvmppc_set_wort_hv(vcpu, set_reg_val(id, *val));
vcpu->arch.tid = set_reg_val(id, *val);
vcpu->arch.psscr = set_reg_val(id, *val) & PSSCR_GUEST_VIS;
addr = set_reg_val(id, *val);
u64 tb_offset = ALIGN(set_reg_val(id, *val), 1UL << 24);
kvmppc_set_lpcr(vcpu, set_reg_val(id, *val), true);
kvmppc_set_lpcr(vcpu, set_reg_val(id, *val), false);
kvmppc_set_ppr_hv(vcpu, set_reg_val(id, *val));
vcpu->arch.tfhar = set_reg_val(id, *val);
vcpu->arch.tfiar = set_reg_val(id, *val);
vcpu->arch.texasr = set_reg_val(id, *val);
vcpu->arch.gpr_tm[i] = set_reg_val(id, *val);
vcpu->arch.cr_tm = set_reg_val(id, *val);
vcpu->arch.xer_tm = set_reg_val(id, *val);
vcpu->arch.lr_tm = set_reg_val(id, *val);
vcpu->arch.ctr_tm = set_reg_val(id, *val);
vcpu->arch.fp_tm.fpscr = set_reg_val(id, *val);
vcpu->arch.amr_tm = set_reg_val(id, *val);
vcpu->arch.ppr_tm = set_reg_val(id, *val);
vcpu->arch.vrsave_tm = set_reg_val(id, *val);
vcpu->arch.vr.vscr.u[3] = set_reg_val(id, *val);
vcpu->arch.dscr_tm = set_reg_val(id, *val);
vcpu->arch.tar_tm = set_reg_val(id, *val);
r = kvmppc_set_arch_compat(vcpu, set_reg_val(id, *val));
kvmppc_set_dec_expires(vcpu, set_reg_val(id, *val));
i = set_reg_val(id, *val);
vcpu->kvm->arch.l1_ptcr = set_reg_val(id, *val);
kvmppc_set_fscr_hv(vcpu, set_reg_val(id, *val));
to_book3s(vcpu)->hior = set_reg_val(id, *val);
to_book3s(vcpu)->vtb = set_reg_val(id, *val);
kvmppc_set_lpcr_pr(vcpu, set_reg_val(id, *val));
vcpu->arch.tfhar = set_reg_val(id, *val);
vcpu->arch.tfiar = set_reg_val(id, *val);
vcpu->arch.texasr = set_reg_val(id, *val);
set_reg_val(id, *val);
vcpu->arch.cr_tm = set_reg_val(id, *val);
vcpu->arch.xer_tm = set_reg_val(id, *val);
vcpu->arch.lr_tm = set_reg_val(id, *val);
vcpu->arch.ctr_tm = set_reg_val(id, *val);
vcpu->arch.fp_tm.fpscr = set_reg_val(id, *val);
vcpu->arch.amr_tm = set_reg_val(id, *val);
vcpu->arch.ppr_tm = set_reg_val(id, *val);
vcpu->arch.vrsave_tm = set_reg_val(id, *val);
vcpu->arch.vr.vscr.u[3] = set_reg_val(id, *val);
vcpu->arch.dscr_tm = set_reg_val(id, *val);
vcpu->arch.tar_tm = set_reg_val(id, *val);
vcpu->arch.dbg_reg.iac1 = set_reg_val(id, *val);
vcpu->arch.dbg_reg.iac2 = set_reg_val(id, *val);
vcpu->arch.dbg_reg.iac3 = set_reg_val(id, *val);
vcpu->arch.dbg_reg.iac4 = set_reg_val(id, *val);
vcpu->arch.dbg_reg.dac1 = set_reg_val(id, *val);
vcpu->arch.dbg_reg.dac2 = set_reg_val(id, *val);
u32 new_epr = set_reg_val(id, *val);
u32 new_epcr = set_reg_val(id, *val);
u32 tsr_bits = set_reg_val(id, *val);
u32 tsr_bits = set_reg_val(id, *val);
u32 tsr = set_reg_val(id, *val);
u32 tcr = set_reg_val(id, *val);
vcpu->arch.vrsave = set_reg_val(id, *val);
vcpu->arch.shared->mas0 = set_reg_val(id, *val);
vcpu->arch.shared->mas1 = set_reg_val(id, *val);
vcpu->arch.shared->mas2 = set_reg_val(id, *val);
vcpu->arch.shared->mas7_3 = set_reg_val(id, *val);
vcpu->arch.shared->mas4 = set_reg_val(id, *val);
vcpu->arch.shared->mas6 = set_reg_val(id, *val);
u32 reg = set_reg_val(id, *val);
u32 reg = set_reg_val(id, *val);
u32 reg = set_reg_val(id, *val);
u32 reg = set_reg_val(id, *val);
vcpu->arch.sprg9 = set_reg_val(id, *val);
kvmppc_set_vscr(vcpu, set_reg_val(reg->id, val));
kvmppc_set_vrsave(vcpu, set_reg_val(reg->id, val));