sdhci_writew
sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
sdhci_writew(host, ctl, F_SDH30_AHB_CONFIG);
sdhci_writew(host, ctl, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, val, PHY_CMDPAD_CNFG_R);
sdhci_writew(host, val, PHY_DATAPAD_CNFG_R);
sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R);
sdhci_writew(host, val, PHY_CLKPAD_CNFG_R);
sdhci_writew(host, val, PHY_STBPAD_CNFG_R);
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, val, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
sdhci_writew(host, val, PHY_CMDPAD_CNFG_R);
sdhci_writew(host, val, PHY_DATAPAD_CNFG_R);
sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R);
sdhci_writew(host, val, PHY_CLKPAD_CNFG_R);
sdhci_writew(host, val, PHY_STBPAD_CNFG_R);
sdhci_writew(host, i, priv->vendor_specific_area1 + DWCMSHC_AT_STAT);
sdhci_writew(host, 0, priv->vendor_specific_area1 + DWCMSHC_AT_STAT);
sdhci_writew(host, phase_code, priv->vendor_specific_area1 + DWCMSHC_AT_STAT);
sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
sdhci_writew(host, val, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
sdhci_writew(host, 0, priv->vendor_specific_area1 + DWCMSHC_AT_STAT);
sdhci_writew(host, 0x0, SDHCI_CMD_DATA);
sdhci_writew(host, val, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
sdhci_writew(host, 0xffff, PHY_DLLBT_CNFG_R);
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, val, PHY_CMDPAD_CNFG_R);
sdhci_writew(host, val, PHY_DATAPAD_CNFG_R);
sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R);
sdhci_writew(host, val, PHY_CLKPAD_CNFG_R);
sdhci_writew(host, val, PHY_STBPAD_CNFG_R);
sdhci_writew(host, emmc_ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
sdhci_writew(host, ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
sdhci_writew(host, DWCMSHC_SDHCI_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE);
sdhci_writew(host, DWCMSHC_SDHCI_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE);
sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
sdhci_writew(host, ctl, MA35_SDHCI_MSHCCTL);
sdhci_writew(host, regs[idx], restore_data[idx].reg);
sdhci_writew(host, ctl, MA35_SDHCI_MBIUCTL);
sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, data, PHY_DAT_REG);
sdhci_writew(host, (PHY_WRITE | offset), PHY_ADDR_REG);
sdhci_writew(host, 0, PHY_DAT_REG);
sdhci_writew(host, offset, PHY_ADDR_REG);
sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
sdhci_writew(host, clk & ~SDHCI_CLOCK_CARD_EN, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, SDHCI_CLOCK_INT_EN, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, SDHCI_CTRL_V4_MODE, SDHCI_HOST_CONTROL2);
sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, value, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, value, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
sdhci_writew(host, GLI_9763E_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE);
sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, reg, O2_SD_VENDOR_SETTING);
sdhci_writew(host, scratch, O2_SD_MISC_CTRL);
sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, scratch, O2_SD_MISC_CTRL);
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, scratch16, O2_SD_PCIE_SWITCH);
sdhci_writew(host, 0, SDHCI_TRANSFER_MODE);
sdhci_writew(host, SDHCI_MAKE_CMD(MMC_GO_IDLE_STATE, SDHCI_CMD_RESP_NONE),
sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
sdhci_writew(host, SDHCI_TEGRA_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE);
sdhci_writew(host, SDHCI_TEGRA_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE);
sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, data->blksz, SDHCI_UHS2_BLOCK_SIZE);
sdhci_writew(host, data->blocks, SDHCI_UHS2_BLOCK_COUNT);
sdhci_writew(host, mode, SDHCI_UHS2_TRANS_MODE);
sdhci_writew(host, mode, SDHCI_UHS2_TRANS_MODE);
sdhci_writew(host, cmd_reg, SDHCI_UHS2_CMD);
sdhci_writew(host, mask, SDHCI_UHS2_SW_RESET);
sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
sdhci_writew(host,
sdhci_writew(host, 0, SDHCI_BLOCK_COUNT);
sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT);
sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 128), SDHCI_BLOCK_SIZE);
sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 64), SDHCI_BLOCK_SIZE);
sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, 512),
sdhci_writew(host, ctrl, F_SDH30_AHB_CONFIG);
sdhci_writew(host, 0xBC01, SDHCI_CLOCK_CONTROL);