sdhci_readw
preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
ctl = sdhci_readw(host, F_SDH30_AHB_CONFIG);
ctl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
if (read_poll_timeout(sdhci_readw, clk, (clk & SDHCI_CLOCK_INT_STABLE),
clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
val = sdhci_readw(host, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
sdhci_readw(host, DWCMSHC_P_VENDOR_AREA2);
ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
emmc_ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
command = SDHCI_GET_CMD(sdhci_readw(host,
sdhci_readw(host, SDHCI_BLOCK_COUNT) &&
host_ver = sdhci_readw(host, SDHCI_HOST_VERSION);
regs[idx] = sdhci_readw(host, restore_data[idx].reg);
ctl = sdhci_readw(host, MA35_SDHCI_MBIUCTL);
ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
ctl = sdhci_readw(host, MA35_SDHCI_MSHCCTL);
val = sdhci_readw(host, PHY_ADDR_REG);
*data = sdhci_readw(host, PHY_DAT_REG) & DATA_MASK;
val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
u16 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
vendor_ptr = sdhci_readw(host, SDHCI_VENDOR_PTR_R);
ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
value = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
value = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
clock = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
clock = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
if (read_poll_timeout(sdhci_readw, clock, (clock & SDHCI_CLOCK_INT_STABLE),
ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
if (read_poll_timeout_atomic(sdhci_readw, clk, (clk & SDHCI_CLOCK_INT_STABLE),
scratch = sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1);
if (!(sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1) & O2_PLL_LOCK_STATUS))
reg = sdhci_readw(host, O2_SD_VENDOR_SETTING);
u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
scratch = sdhci_readw(host, O2_SD_MISC_CTRL);
reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
scratch = sdhci_readw(host, O2_SD_MISC_CTRL);
scratch16 = sdhci_readw(host, O2_SD_PCIE_SWITCH);
ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
u16 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
if (read_poll_timeout_atomic(sdhci_readw, val, !(val & mask), 10,
ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
caps_ptr = sdhci_readw(host, SDHCI_UHS2_CAPS_PTR);
sdhci_readw(host, SDHCI_UHS2_BLOCK_SIZE),
u16 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
u16 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
if (read_poll_timeout(sdhci_readw, val, (val & SDHCI_CLOCK_INT_STABLE),
sdhci_readw(host, SDHCI_UHS2_CMD),
u16 sdhci_uhs2_set_ptr = sdhci_readw(host, SDHCI_UHS2_SETTINGS_PTR);
sdhci_readw(host, SDHCI_UHS2_TRANS_MODE));
sdhci_readw(host, SDHCI_UHS2_DEV_INT_STATUS),
sdhci_readw(host, SDHCI_UHS2_SW_RESET),
sdhci_readw(host, SDHCI_UHS2_TIMER_CTRL));
mode = sdhci_readw(host, SDHCI_UHS2_TRANS_MODE);
err = read_poll_timeout(sdhci_readw, reg, reg & SDHCI_CLOCK_INT_STABLE,
if (sdhci_readw(host, XENON_SLOT_EXT_PRESENT_STATE) &
ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
if (sdhci_readw(host, SDHCI_BLOCK_COUNT))
ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
preset = sdhci_readw(host, SDHCI_PRESET_FOR_HIGH_SPEED);
preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
preset = sdhci_readw(host, SDHCI_PRESET_FOR_UHS2);
preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
if (mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)))) {
ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))))
SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))))
u16 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))))
if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))))
v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
sdhci_readw(host, SDHCI_HOST_VERSION),
sdhci_readw(host, SDHCI_HOST_VERSION));
sdhci_readw(host, SDHCI_BLOCK_SIZE),
sdhci_readw(host, SDHCI_BLOCK_COUNT));
sdhci_readw(host, SDHCI_TRANSFER_MODE));
sdhci_readw(host, SDHCI_CLOCK_CONTROL));
sdhci_readw(host, SDHCI_AUTO_CMD_STATUS),
sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
sdhci_readw(host, SDHCI_COMMAND),
sdhci_readw(host, SDHCI_HOST_CONTROL2));
ctrl = sdhci_readw(host, F_SDH30_AHB_CONFIG);
if (sdhci_readw(host, SDHCI_CLOCK_CONTROL) == 0)