sck
static const struct sck at91rm9200_systemck[] = {
.sck = at91sam9260_systemck,
.sck = at91sam9260_systemck,
static const struct sck at91sam9261_systemck[] = {
.sck = at91sam9261_systemck,
const struct sck *sck;
static const struct sck at91sam9263_systemck[] = {
.sck = at91sam9263_systemck,
ndck(data->sck, data->num_sck),
hw = at91_clk_register_system(regmap, data->sck[i].n,
data->sck[i].p, NULL,
data->sck[i].id, 0);
at91sam9260_pmc->shws[data->sck[i].id] = hw;
static const struct sck at91sam9260_systemck[] = {
struct gpio_desc *sck;
gpiod_set_value(data->sck, 0);
gpiod_set_value(data->sck, 1);
gpiod_set_value(data->sck, 0);
gpiod_set_value(data->sck, 1);
gpiod_set_value(data->sck, 0);
gpiod_set_value(data->sck, 0);
gpiod_set_value(data->sck, 1);
gpiod_set_value(data->sck, 0);
gpiod_set_value(data->sck, 1);
gpiod_set_value(data->sck, 0);
gpiod_set_value(data->sck, 1);
gpiod_set_value(data->sck, 0);
gpiod_set_value(data->sck, 0);
gpiod_set_value(data->sck, 1);
gpiod_set_value(data->sck, 0);
gpiod_set_value(data->sck, 1);
gpiod_set_value(data->sck, 0);
gpiod_set_value(data->sck, 1);
gpiod_set_value(data->sck, 0);
data->sck = devm_gpiod_get(&pdev->dev, "clk", GPIOD_OUT_LOW);
if (IS_ERR(data->sck)) {
ret = PTR_ERR(data->sck);
#define SCIF_PFC_CLK(name, sck) SH_PFC_MUX1(name, sck)
#define SSI_PFC_CTRL(name, sck, ws) SH_PFC_MUX2(name, sck, ws)
gpiod_set_value_cansleep(spi_gpio->sck, spi->mode & SPI_CPOL);
gpiod_set_value_cansleep(spi_gpio->sck,
gpiod_set_value_cansleep(spi_gpio->sck,
spi_gpio->sck = devm_gpiod_get(dev, "sck", GPIOD_OUT_LOW);
return PTR_ERR_OR_ZERO(spi_gpio->sck);
struct gpio_desc *sck;
gpiod_set_value_cansleep(spi_gpio->sck, is_on);
unsigned int sck; /* Rate requested (vs actual) */
if (hz != spi->sck) {
spi->sck = hz;
static int pic32_sqi_set_clk_rate(struct pic32_sqi *sqi, u32 sck)
div = clk_get_rate(sqi->base_clk) / (2 * sck);