rtw89_read32_mask
cv = rtw89_read32_mask(rtwdev, R_AX_SYS_CFG1, B_AX_CHIP_VER_MASK);
rtw89_read32_mask(rtwdev, R_BE_SYS_CHIPINFO, B_BE_HW_ID_MASK);
val32 = rtw89_read32_mask(rtwdev,
val = rtw89_read32_mask(rtwdev, R_AX_EFUSE_CTRL_1,
val = rtw89_read32_mask(rtwdev, R_AX_EFUSE_CTRL_1,
ret = read_poll_timeout(rtw89_read32_mask, val,
if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K))
boot_mode = rtw89_read32_mask(rtwdev, R_AX_GPIO_MUXCFG, B_AX_BOOT_MODE);
val = rtw89_read32_mask(rtwdev, R_AX_SEC_ENG_CTRL,
ret = read_poll_timeout_atomic(rtw89_read32_mask, val32, val32 == 0,
val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK);
ret = read_poll_timeout(rtw89_read32_mask, val, val == 0, 1000, 100000,
cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK);
*tx_time = rtw89_read32_mask(rtwdev, reg, mac->agg_limit.mask) << 5;
*tx_retry = rtw89_read32_mask(rtwdev, reg, mac->txcnt_limit.mask);
return rtw89_read32_mask(rtwdev, reg, mask);
val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE,
ret = read_poll_timeout_atomic(rtw89_read32_mask, val, val == S_BE_BACAM_RST_DONE,
cnt = rtw89_read32_mask(rtwdev, reg, B_BE_BT_PLT_PKT_CNT_MASK);
ret = read_poll_timeout(rtw89_read32_mask, val32, val32 == WLAN_FSM_IDLE,
val32 = rtw89_read32_mask(rtwdev, R_BE_IC_PWR_STATE, B_BE_WLMAC_PWR_STE_MASK);
ret = read_poll_timeout(rtw89_read32_mask, val32, !val32,
ret = read_poll_timeout(rtw89_read32_mask, val32, !val32,
ret = read_poll_timeout(rtw89_read32_mask, val32, !val32,
ret = read_poll_timeout(rtw89_read32_mask, val32, !val32,
ret = read_poll_timeout(rtw89_read32_mask, val32, val32 == MAC_AX_MAC_OFF,
ret = read_poll_timeout(rtw89_read32_mask, val32, !val32,
ret = read_poll_timeout(rtw89_read32_mask, val32, !val32,
ret = read_poll_timeout(rtw89_read32_mask, val32, val32 == MAC_AX_MAC_ON,
ret = read_poll_timeout(rtw89_read32_mask, val32, val32 == MAC_AX_MAC_OFF,
val = rtw89_read32_mask(rtwdev, R_AX_PCIE_MIX_CFG_V1, B_AX_ASPM_CTRL_MASK);
val = rtw89_read32_mask(rtwdev, R_BE_IC_PWR_STATE, B_BE_WLMAC_PWR_STE_MASK);
rpt = rtw89_read32_mask(rtwdev, addr, mask);
return (u8)rtw89_read32_mask(rtwdev, xtal->xcap_reg, reg_mask);
return rtw89_read32_mask(rtwdev, addr + phy->cr_base, mask);
ret = read_poll_timeout_atomic(rtw89_read32_mask, polling, !polling,
val32 = rtw89_read32_mask(rtwdev, R_AX_SYS_STATUS1, B_AX_PAD_HCI_SEL_V2_MASK);