sbus_readb
return sbus_readb(&sun_fdc->status_82077) & ~STATUS_DMA;
return sbus_readb(&sun_fdc->data_82077);
return sbus_readb(&sun_fdc->dir_82077);
if (sbus_readb(&sun_fdc->status1_82077) == 0xff) {
char tmp = sbus_readb(src);
char tmp = sbus_readb(src);
#define apc_readb(offs) (sbus_readb(regs+offs))
return sbus_readb(auxio_register);
regval = sbus_readb(auxio_register);
sbus_readb(auxio_register));
#define pmc_readb(offs) (sbus_readb(regs+offs))
u8 power_register = sbus_readb(auxio_power_register);
sbus_writeb(sbus_readb(info->enable_reg) | 3, info->enable_reg);
sbus_writeb(sbus_readb(info->enable_reg) & 0xFC, info->enable_reg);
*p8 = sbus_readb(pbuf);
!((bits = sbus_readb(&rd->rmd1_bits)) & LE_R1_OWN);
u8 bits = sbus_readb(&td->tmd1_bits);
while ((sbus_readb(mregs + MREGS_IACONFIG) & MREGS_IACONFIG_ACHNGE) != 0)
while ((sbus_readb(mregs + MREGS_IACONFIG) & MREGS_IACONFIG_ACHNGE) != 0)
if (!(sbus_readb(mregs + MREGS_PHYCONFIG) & MREGS_PHYCONFIG_LTESTDIS)) {
tmp = sbus_readb(mregs + MREGS_PHYCONFIG);
sbus_readb(mregs + MREGS_MPCNT);
while ((sbus_readb(qep->mregs + MREGS_IACONFIG) & MREGS_IACONFIG_ACHNGE) != 0)
while ((sbus_readb(qep->mregs + MREGS_IACONFIG) & MREGS_IACONFIG_ACHNGE) != 0)
phyconfig = sbus_readb(mregs + MREGS_PHYCONFIG);
u8 tmp = sbus_readb(mregs + MREGS_BCONFIG);
unsigned char value_tcr = sbus_readb(®s->p_tcr);
unsigned char value_or = sbus_readb(®s->p_or);
unsigned char value_tcr = sbus_readb(®s->p_tcr);
unsigned char value_or = sbus_readb(®s->p_or);
unsigned char value_tcr = sbus_readb(®s->p_tcr);
u8 val = sbus_readb(®s->p_tcr);
value_tcr = sbus_readb(®s->p_tcr);
return sbus_readb(®s->p_dr);
unsigned char value_tcr = sbus_readb(®s->p_tcr);
unsigned char value_ir = sbus_readb(®s->p_ir);
int curstat = sbus_readb(qpti->sreg);
return sbus_readb(esp->regs + (reg * 4UL));
#define ZS_CLEARFIFO(channel) do { sbus_readb(&channel->data); \
sbus_readb(&channel->data); \
sbus_readb(&channel->data); \
val = sbus_readb(®s->control);
val = sbus_readb(®s->control);
status = sbus_readb(&par->regs->status);
val = sbus_readb(®s->mcr);
cur_mode = sbus_readb(®s->mcr);
val = sbus_readb(®s->control);
val = sbus_readb(®s->control);
u8 status = sbus_readb(&par->regs->status), mon;
ir = sbus_readb(amd->regs + AMD7930_IR);
byte = sbus_readb(amd->regs + AMD7930_BBRB);
return sbus_readb(reg_addr);