reg_status
ack = kw_read_reg(reg_status);
kw_write_reg(reg_status, 0);
ack = kw_read_reg(reg_status);
ack = kw_read_reg(reg_status);
kw_write_reg(reg_status, 0);
cmd_q->q_status = ioread32(cmd_q->reg_status);
cmd_q->reg_status = ccp->io_regs + CMD_Q_STATUS_BASE +
ioread32(cmd_q->reg_status);
ioread32(cmd_q->reg_status);
return CMD_Q_DEPTH(ioread32(cmd_q->reg_status));
ioread32(cmd_q->reg_status);
cmd_q->q_status = ioread32(cmd_q->reg_status);
cmd_q->reg_status = cmd_q->reg_control + CMD5_Q_STATUS_BASE;
ioread32(cmd_q->reg_status);
void __iomem *reg_status;
int reg_status;
reg_status = CRYPTO_READ(dev, RK_CRYPTO_CTRL) |
CRYPTO_WRITE(dev, RK_CRYPTO_CTRL, reg_status);
reg_status = CRYPTO_READ(dev, RK_CRYPTO_CTRL);
reg_status &= (~RK_CRYPTO_HASH_FLUSH);
reg_status |= _SBF(0xffff, 16);
CRYPTO_WRITE(dev, RK_CRYPTO_CTRL, reg_status);
uint32_t reg_status;
reg_status = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35);
if (reg_status & 0x80000000)
if ((reg_status & 0xFFFF) != 0) {
reg_status & 0xFFFF);
uint32_t reg_status;
reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35);
if (reg_status & 0x80000000)
if ((reg_status & 0xFFFF) != 0) {
reg_status & 0xFFFF);
uint32_t reg_status = 0, reg_val = 0;
reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
if ((reg_status & 0xFFFF) != 0) {
cmd, reg_status & 0xFFFF);
uint32_t reg_status;
reg_status = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35);
if (reg_status & 0x80000000)
if ((reg_status & 0xFFFF) != 0) {
reg_status & 0xFFFF);
uint32_t reg_status = 0, reg_val = 0;
reg_status = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_115);
if ((reg_status & 0xFFFF) != 0) {
cmd, reg_status & 0xFFFF);
u32 reg_status;
reg_status = ixGNB_CLK3_STATUS;
reg_status = ixCG_ECLK_STATUS;
if (RREG32_SMC(reg_status) & status_mask)
if (RREG32_SMC(reg_status) & status_mask)
u32 reg_status = adreno_is_a8xx(adreno_gpu) ?
OUT_RING(ring, CP_WAIT_REG_MEM_POLL_ADDR_LO(reg_status));
unsigned int reg_high, reg_low, hyst, reg_status;
reg_status, !(reg_status & MCP9982_STATUS_BUSY),
unsigned int reg_status;
®_status);
if (reg_status & MMC35240_STATUS_MEAS_DONE_BIT)
unsigned int reg_status, val;
ret = regmap_read_poll_timeout(data->regmap, MMC5633_REG_STATUS1, reg_status,
reg_status & val,
unsigned int reg_status;
ret = regmap_read_poll_timeout(data->regmap, MLX90632_REG_STATUS, reg_status,
!(reg_status & MLX90632_STAT_DATA_RDY), 10000,
return (reg_status & MLX90632_STAT_CYCLE_POS) >> 2;
unsigned int reg_status;
reg_status,
(reg_status & MLX90632_STAT_BUSY) == 0,
unsigned int reg_status;
ret = regmap_read_poll_timeout(data->regmap, MLX90635_REG_STATUS, reg_status,
(!(reg_status & MLX90635_STAT_END_CONV)) == 0,
unsigned int reg_status;
.reg_status = TPS65217_REG_STATUS,
.reg_status = TPS65218_REG_STATUS,
error = regmap_read(pwr->regmap, tps_data->reg_status, ®);
int (*state_parse)(struct cyapa *cyapa, u8 *reg_status, int len);
pending = __raw_readl(cpu->map_base + reg_status(intc, idx));
pending = l1_readl(cpu->map_base + reg_status(intc, idx)) &
status = readl_relaxed(data->reg_status) & ~mask;
icu_data[i].reg_status = mmp_icu_base + reg[0];
void __iomem *reg_status;
const u32 reg_status = msg->reg_status;
const u8 rxerr = reg_status;
const u8 txerr = (reg_status >> 8);
const u32 reg_status = msg->reg_status;
const u8 rxerr = reg_status;
const u8 txerr = (reg_status >> 8);
if (reg_status & ACC_REG_STATUS_MASK_STATUS_BS) {
} else if (reg_status & ACC_REG_STATUS_MASK_STATUS_EP) {
} else if (reg_status & ACC_REG_STATUS_MASK_STATUS_ES) {
u32 reg_status;
u32 reg_status;
ret = ksz_read8(dev, kirq->reg_status, &data);
girq->reg_status = REG_SW_PORT_INT_STATUS__1;
pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS);
u16 reg_status;
ret = ksz_read16(dev, ptpirq->reg_status, &data);
ret = ksz_write16(dev, ptpirq->reg_status, data);
ptpirq->reg_status = ops->get_port_addr(p,
void __iomem *reg_status = data->status + offset * sizeof(u32);
ret = readl_poll_timeout_atomic(reg_status, value, (value & mask) == done, 0, 1000);
void __iomem *reg_status = data->status + offset * sizeof(u32);
u32 value = readl(reg_status);
void __iomem *reg_status;
qmgr->reg_status =
(IS_ERR(qmgr->reg_status) || IS_ERR(qmgr->reg_pop))) ||
if (!IS_ERR(qmgr->reg_status))
devm_iounmap(dev, qmgr->reg_status);
qmgr->reg_peek, qmgr->reg_status,
if ((readl(ep->reg_status) & EPxSTATUS_EP_MASK)
tmp = readl(ep->reg_status);
ep->reg_status = &dev->regs->ep_status [i];
readl(ep->reg_status);
u32 __iomem *reg_status;
u8 reg_status;
ret = max_tcpci_read8(chip, TCPC_FAULT_STATUS, ®_status);
ret = max_tcpci_write8(chip, TCPC_FAULT_STATUS, reg_status);
if (reg_status & TCPC_FAULT_STATUS_VCONN_OC) {
ret = max_tcpci_read8(chip, TCPC_ALERT_EXTENDED, ®_status);
ret = max_tcpci_write8(chip, TCPC_ALERT_EXTENDED, reg_status);
if (reg_status & TCPC_SINK_FAST_ROLE_SWAP) {
ret = max_tcpci_read8(chip, TCPC_EXTENDED_STATUS, (u8 *)®_status);
if (ret >= 0 && (reg_status & TCPC_EXTENDED_STATUS_VSAFE0V))