rio_write_config_32
rio_write_config_32(rdev, RIO_HOST_DID_LOCK_CSR,
rio_write_config_32(rdev,
rio_write_config_32(rdev,
rio_write_config_32(dev, off, val);
rio_write_config_32(rdev,
rio_write_config_32(rdev,
rio_write_config_32(nextdev,
rio_write_config_32(rdev,
rio_write_config_32(rdev,
rio_write_config_32(rdev,
rio_write_config_32(rdev,
rio_write_config_32(rdev,
rio_write_config_32(rdev, RIO_DEV_PORT_N_ERR_STS_CSR(rdev, portnum),
rio_write_config_32(rdev,
rio_write_config_32(rdev, IDT_PW_INFO_CSR, 0x0000e000);
rio_write_config_32(rdev, IDT_LT_ERR_REPORT_EN,
rio_write_config_32(rdev, IDT_DEV_CTRL_1,
rio_write_config_32(rdev, IDT_PORT_ERR_REPORT_EN_BC, 0x807e8037);
rio_write_config_32(rdev, IDT_PORT_ISERR_REPORT_EN_BC,
rio_write_config_32(rdev,
rio_write_config_32(rdev, IDT_ERR_CAP, IDT_ERR_CAP_LOG_OVERWR);
rio_write_config_32(rdev, IDT_LANE_ERR_REPORT_EN_BC, 0);
rio_write_config_32(rdev, IDT_LANE_CTRL(i),
rio_write_config_32(rdev, IDT_AUX_PORT_ERR_CAP_EN, 0);
rio_write_config_32(rdev, IDT_AUX_ERR_REPORT_EN, 0);
rio_write_config_32(rdev, IDT_JTAG_CTRL, 0);
rio_write_config_32(rdev, IDT_I2C_MCTRL, regval & ~IDT_I2C_MCTRL_GENPW);
rio_write_config_32(rdev, IDT_CFGBLK_ERR_CAPTURE_EN, 0);
rio_write_config_32(rdev, IDT_CFGBLK_ERR_REPORT,
rio_write_config_32(rdev,
rio_write_config_32(rdev, IDT_ISLTL_ADDRESS_CAP, 0);
rio_write_config_32(rdev,
rio_write_config_32(rdev,
rio_write_config_32(rdev, RIO_EM_DEV_INT_EN, 0);
rio_write_config_32(rdev, rdev->em_efptr + RIO_EM_PW_TX_CTRL,
rio_write_config_32(rdev,
rio_write_config_32(rdev,
rio_write_config_32(rdev, RIO_PLM_SPx_PW_EN(i),
rio_write_config_32(rdev, RIO_PW_ROUTE, 1 << tmp);
rio_write_config_32(rdev, rdev->em_efptr + RIO_EM_PW_TX_CTRL, 0);
rio_write_config_32(rdev,
rio_write_config_32(rdev, RIO_PLM_SPx_IMP_SPEC_CTL(pnum),
rio_write_config_32(rdev, RIO_PLM_SPx_IMP_SPEC_CTL(pnum), rval);
rio_write_config_32(rdev, 0x5000 + RIO_BC_RT_CTL_CSR, 0);
rio_write_config_32(rdev,
rio_write_config_32(rdev,
rio_write_config_32(rdev,