reset_control_bulk_assert
reset_control_bulk_assert(ARRAY_SIZE(core->resets), core->resets);
err = reset_control_bulk_assert(gr3d->nresets, gr3d->resets);
err = reset_control_bulk_assert(host->nresets, host->resets);
ret = reset_control_bulk_assert(ARRAY_SIZE(resets), resets);
reset_control_bulk_assert(ARRAY_SIZE(resets), resets);
reset_control_bulk_assert(ARRAY_SIZE(mali_c55->resets), mali_c55->resets);
reset_control_bulk_assert(xo_rst_tbl_size, core->controller_resets);
reset_control_bulk_assert(ARRAY_SIZE(ivc->resets), ivc->resets);
reset_control_bulk_assert(ARRAY_SIZE(ivc->resets), ivc->resets);
reset_control_bulk_assert(HDMIRX_NUM_RST, hdmirx_dev->resets);
reset_control_bulk_assert(HDMIRX_NUM_RST, hdmirx_dev->resets);
err = reset_control_bulk_assert(eth->soc->num_xsi_rsts, eth->xsi_rsts);
err = reset_control_bulk_assert(ARRAY_SIZE(eth->rsts), eth->rsts);
ret = reset_control_bulk_assert(miic->of_data->reset_count, miic->rsts);
ret = reset_control_bulk_assert(DW_PCIE_NUM_CORE_RSTS, pci->core_rsts);
reset_control_bulk_assert(res->num_resets, res->resets);
ret = reset_control_bulk_assert(res->num_resets, res->resets);
reset_control_bulk_assert(res->num_resets, res->resets);
ret = reset_control_bulk_assert(res->num_resets, res->resets);
reset_control_bulk_assert(res->num_resets, res->resets);
ret = reset_control_bulk_assert(ARRAY_SIZE(res->rst), res->rst);
reset_control_bulk_assert(ARRAY_SIZE(res->rst), res->rst);
reset_control_bulk_assert(ARRAY_SIZE(pci->app_rsts), pci->app_rsts);
reset_control_bulk_assert(pcie->soc->phy_resets.num_resets,
reset_control_bulk_assert(pcie->soc->phy_resets.num_resets,
reset_control_bulk_assert(pcie->soc->phy_resets.num_resets,
reset_control_bulk_assert(pcie->soc->phy_resets.num_resets,
reset_control_bulk_assert(pcie->soc->phy_resets.num_resets,
err = reset_control_bulk_assert(ROCKCHIP_NUM_PM_RSTS,
err = reset_control_bulk_assert(ROCKCHIP_NUM_CORE_RSTS,
reset_control_bulk_assert(host->data->num_cfg_resets,
reset_control_bulk_assert(host->data->num_power_resets,
ret = reset_control_bulk_assert(data->num_power_resets,
ret = reset_control_bulk_assert(data->num_cfg_resets,
reset_control_bulk_assert(data->num_power_resets,
reset_control_bulk_assert(inst->num_rsts, inst->rsts);
reset_control_bulk_assert(ARRAY_SIZE(resets), resets);
ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets);
reset_control_bulk_assert(cfg->num_resets, qmp->resets);
reset_control_bulk_assert(cfg->num_resets, qmp->resets);
ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets);
reset_control_bulk_assert(cfg->num_resets, qmp->resets);
reset_control_bulk_assert(cfg->num_resets, qmp->resets);
ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets);
reset_control_bulk_assert(cfg->num_resets, qmp->resets);
reset_control_bulk_assert(cfg->num_resets, qmp->resets);
ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets);
reset_control_bulk_assert(cfg->num_resets, qmp->resets);
reset_control_bulk_assert(cfg->num_resets, qmp->resets);
ret = reset_control_bulk_assert(qmp->num_resets, qmp->resets);
reset_control_bulk_assert(qmp->num_resets, qmp->resets);
reset_control_bulk_assert(qmp->num_resets, qmp->resets);
ret = reset_control_bulk_assert(qmp->num_resets, qmp->resets);
reset_control_bulk_assert(qmp->num_resets, qmp->resets);
reset_control_bulk_assert(qmp->num_resets, qmp->resets);
return reset_control_bulk_assert(udphy->num_rsts, udphy->rsts);
reset_control_bulk_assert(devres->num_rstcs, devres->rstcs);
EXPORT_SYMBOL_GPL(reset_control_bulk_assert);
ret = reset_control_bulk_assert(stfcamss->nrsts, stfcamss->sys_rst);
reset_control_bulk_assert(google->num_rsts, google->rsts);
reset_control_bulk_assert(google->num_rsts, google->rsts);
reset_control_bulk_assert(google->num_rsts, google->rsts);
int reset_control_bulk_assert(int num_rstcs, struct reset_control_bulk_data *rstcs);
rc = reset_control_bulk_assert(hda->nresets, hda->resets);
ret = reset_control_bulk_assert(ahub->nresets, ahub->resets);