arch/x86/math-emu/fpu_emu.h

146

#define fpu_register(x) ( * ((FPU_REG *)( register_base + 10 * (x & 7) )) )

arch/x86/math-emu/fpu_emu.h

147

#define st(x) ( * ((FPU_REG *)( register_base + 10 * ((top+x) & 7) )) )

arch/x86/math-emu/reg_ld_str.c

1129

FPU_copy_from_user(register_base + offset, s, other);

arch/x86/math-emu/reg_ld_str.c

1131

FPU_copy_from_user(register_base, s + other, offset);

arch/x86/math-emu/reg_ld_str.c

1210

if (__copy_to_user(d, register_base + offset, other))

arch/x86/math-emu/reg_ld_str.c

1213

if (__copy_to_user(d + other, register_base, offset))

drivers/gpio/gpio-octeon.c

100

gpio->register_base = (u64)reg_base;

drivers/gpio/gpio-octeon.c

39

u64 register_base;

drivers/gpio/gpio-octeon.c

46

cvmx_write_csr(gpio->register_base + bit_cfg_reg(offset), 0);

drivers/gpio/gpio-octeon.c

55

u64 reg = gpio->register_base + (value ? TX_SET : TX_CLEAR);

drivers/gpio/gpio-octeon.c

72

cvmx_write_csr(gpio->register_base + bit_cfg_reg(offset), cfgx.u64);

drivers/gpio/gpio-octeon.c

79

u64 read_bits = cvmx_read_csr(gpio->register_base + RX_DAT);

drivers/gpio/gpio-thunderx.c

114

txgpio->register_base + bit_cfg_reg(line));

drivers/gpio/gpio-thunderx.c

126

void __iomem *reg = txgpio->register_base +

drivers/gpio/gpio-thunderx.c

153

writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line));

drivers/gpio/gpio-thunderx.c

172

bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));

drivers/gpio/gpio-thunderx.c

191

void __iomem *reg = txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET;

drivers/gpio/gpio-thunderx.c

202

bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));

drivers/gpio/gpio-thunderx.c

241

writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line));

drivers/gpio/gpio-thunderx.c

265

u64 read_bits = readq(txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_RX_DAT);

drivers/gpio/gpio-thunderx.c

285

writeq(set_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET);

drivers/gpio/gpio-thunderx.c

286

writeq(clear_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_CLR);

drivers/gpio/gpio-thunderx.c

298

txgpio->register_base + intr_reg(irqd_to_hwirq(d)));

drivers/gpio/gpio-thunderx.c

307

txgpio->register_base + intr_reg(irqd_to_hwirq(d)));

drivers/gpio/gpio-thunderx.c

316

txgpio->register_base + intr_reg(irqd_to_hwirq(d)));

drivers/gpio/gpio-thunderx.c

325

txgpio->register_base + intr_reg(irqd_to_hwirq(d)));

drivers/gpio/gpio-thunderx.c

356

writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(txline->line));

drivers/gpio/gpio-thunderx.c

464

txgpio->register_base = tbl[0];

drivers/gpio/gpio-thunderx.c

465

if (!txgpio->register_base) {

drivers/gpio/gpio-thunderx.c

476

u64 c = readq(txgpio->register_base + GPIO_CONST);

drivers/gpio/gpio-thunderx.c

500

u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(i));

drivers/gpio/gpio-thunderx.c

55

u8 __iomem *register_base;

drivers/gpio/gpio-thunderx.c

77

u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));

drivers/net/mdio/mdio-cavium.c

107

oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD);

drivers/net/mdio/mdio-cavium.c

114

smi_rd.u64 = oct_mdio_readq(p->register_base + SMI_RD_DAT);

drivers/net/mdio/mdio-cavium.c

136

oct_mdio_writeq(smi_wr.u64, p->register_base + SMI_WR_DAT);

drivers/net/mdio/mdio-cavium.c

142

oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD);

drivers/net/mdio/mdio-cavium.c

149

smi_wr.u64 = oct_mdio_readq(p->register_base + SMI_WR_DAT);

drivers/net/mdio/mdio-cavium.c

174

oct_mdio_writeq(smi_wr.u64, p->register_base + SMI_WR_DAT);

drivers/net/mdio/mdio-cavium.c

180

oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD);

drivers/net/mdio/mdio-cavium.c

187

smi_wr.u64 = oct_mdio_readq(p->register_base + SMI_WR_DAT);

drivers/net/mdio/mdio-cavium.c

21

smi_clk.u64 = oct_mdio_readq(p->register_base + SMI_CLK);

drivers/net/mdio/mdio-cavium.c

24

oct_mdio_writeq(smi_clk.u64, p->register_base + SMI_CLK);

drivers/net/mdio/mdio-cavium.c

39

oct_mdio_writeq(smi_wr.u64, p->register_base + SMI_WR_DAT);

drivers/net/mdio/mdio-cavium.c

45

oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD);

drivers/net/mdio/mdio-cavium.c

52

smi_wr.u64 = oct_mdio_readq(p->register_base + SMI_WR_DAT);

drivers/net/mdio/mdio-cavium.c

73

oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD);

drivers/net/mdio/mdio-cavium.c

80

smi_rd.u64 = oct_mdio_readq(p->register_base + SMI_RD_DAT);

drivers/net/mdio/mdio-cavium.h

93

void __iomem *register_base;

drivers/net/mdio/mdio-octeon.c

30

bus->register_base = devm_platform_ioremap_resource(pdev, 0);

drivers/net/mdio/mdio-octeon.c

31

if (IS_ERR(bus->register_base)) {

drivers/net/mdio/mdio-octeon.c

33

return PTR_ERR(bus->register_base);

drivers/net/mdio/mdio-octeon.c

38

oct_mdio_writeq(smi_en.u64, bus->register_base + SMI_EN);

drivers/net/mdio/mdio-octeon.c

41

snprintf(bus->mii_bus->id, MII_BUS_ID_SIZE, "%px", bus->register_base);

drivers/net/mdio/mdio-octeon.c

60

oct_mdio_writeq(smi_en.u64, bus->register_base + SMI_EN);

drivers/net/mdio/mdio-octeon.c

73

oct_mdio_writeq(smi_en.u64, bus->register_base + SMI_EN);

drivers/net/mdio/mdio-thunder.c

127

oct_mdio_writeq(0, bus->register_base + SMI_EN);

drivers/net/mdio/mdio-thunder.c

86

bus->register_base = nexus->bar0 +

drivers/net/mdio/mdio-thunder.c

91

oct_mdio_writeq(smi_en.u64, bus->register_base + SMI_EN);

drivers/spi/spi-cavium-octeon.c

38

p->register_base = reg_base;

drivers/spi/spi-cavium-octeon.c

77

writeq(0, p->register_base + OCTEON_SPI_CFG(p));

drivers/spi/spi-cavium-thunderx.c

41

p->register_base = pcim_iomap(pdev, 0, pci_resource_len(pdev, 0));

drivers/spi/spi-cavium-thunderx.c

42

if (!p->register_base) {

drivers/spi/spi-cavium-thunderx.c

94

writeq(0, p->register_base + OCTEON_SPI_CFG(p));

drivers/spi/spi-cavium.c

102

writeq(d, p->register_base + OCTEON_SPI_DAT0(p) + (8 * i));

drivers/spi/spi-cavium.c

113

writeq(mpi_tx.u64, p->register_base + OCTEON_SPI_TX(p));

drivers/spi/spi-cavium.c

118

u64 v = readq(p->register_base + OCTEON_SPI_DAT0(p) + (8 * i));

drivers/spi/spi-cavium.c

24

mpi_sts.u64 = readq(p->register_base + OCTEON_SPI_STS(p));

drivers/spi/spi-cavium.c

66

writeq(mpi_cfg.u64, p->register_base + OCTEON_SPI_CFG(p));

drivers/spi/spi-cavium.c

78

writeq(d, p->register_base + OCTEON_SPI_DAT0(p) + (8 * i));

drivers/spi/spi-cavium.c

85

writeq(mpi_tx.u64, p->register_base + OCTEON_SPI_TX(p));

drivers/spi/spi-cavium.c

90

u64 v = readq(p->register_base + OCTEON_SPI_DAT0(p) + (8 * i));

drivers/spi/spi-cavium.h

18

void __iomem *register_base;