arch/nios2/kernel/misaligned.c

214

reg_offsets[r] = offset;

arch/nios2/kernel/misaligned.c

222

reg_offsets[r] = offset;

arch/nios2/kernel/misaligned.c

49

static int reg_offsets[32];

arch/nios2/kernel/misaligned.c

53

u8 *p = ((u8 *)fp) + reg_offsets[reg];

arch/nios2/kernel/misaligned.c

59

u8 *p = ((u8 *)fp) + reg_offsets[reg];

arch/x86/um/ptrace_32.c

148

return mask & child->thread.regs.regs.gp[reg_offsets[regno]];

arch/x86/um/ptrace_32.c

31

static const int reg_offsets[] = {

arch/x86/um/ptrace_32.c

96

child->thread.regs.regs.gp[reg_offsets[regno]] = value;

arch/x86/um/ptrace_64.c

108

child->thread.regs.regs.gp[reg_offsets[regno >> 3]] = value;

arch/x86/um/ptrace_64.c

169

return mask & child->thread.regs.regs.gp[reg_offsets[regno >> 3]];

arch/x86/um/ptrace_64.c

24

static const int reg_offsets[] =

drivers/cpufreq/mediatek-cpufreq-hw.c

276

data->reg_bases[i] = base + priv->variant->reg_offsets[i];

drivers/cpufreq/mediatek-cpufreq-hw.c

57

const u16 reg_offsets[REG_ARRAY_SIZE];

drivers/cpufreq/mediatek-cpufreq-hw.c

62

.reg_offsets = {

drivers/cpufreq/mediatek-cpufreq-hw.c

84

.reg_offsets = {

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

304

cp110->offsets = reg_offsets[params->inst];

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

44

static const struct dce110_compressor_reg_offsets reg_offsets[] = {

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

78

cp110->offsets = reg_offsets[crtc_inst];

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

402

cp110->offsets = reg_offsets[params->inst];

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

43

static const struct dce112_compressor_reg_offsets reg_offsets[] = {

drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c

254

tg110->derived_offsets = reg_offsets[instance];

drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c

51

static const struct dce110_timing_generator_offsets reg_offsets[] = {

drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c

236

tg110->derived_offsets = reg_offsets[instance];

drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c

51

static const struct dce110_timing_generator_offsets reg_offsets[] = {

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

43

static const struct dce100_hw_seq_reg_offsets reg_offsets[] = {

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

65

(reg + reg_offsets[id].crtc)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

104

static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

120

(reg + reg_offsets[id].blnd)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

123

(reg + reg_offsets[id].crtc)

drivers/gpu/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c

42

static const struct dce112_hw_seq_reg_offsets reg_offsets[] = {

drivers/gpu/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c

63

(reg + reg_offsets[id].crtc)

drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

55

static const struct dce120_hw_seq_reg_offsets reg_offsets[] = {

drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

77

(reg + reg_offsets[id].crtc)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1234

inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt;

drivers/gpu/drm/i915/gt/intel_lrc.c

1579

set_offsets(ce->lrc_reg_state, reg_offsets(engine), engine, false);

drivers/gpu/drm/i915/gt/intel_lrc.c

943

set_offsets(regs, reg_offsets(engine), engine, inhibit);

drivers/gpu/drm/msm/adreno/adreno_gpu.h

252

const unsigned int *reg_offsets;

drivers/gpu/drm/xe/xe_lrc.c

969

set_offsets(regs, reg_offsets(gt_to_xe(gt), hwe->class), hwe);

drivers/i2c/busses/i2c-mv64xxx.c

1025

memcpy(&drv_data->reg_offsets, &mv64xxx_i2c_regs_mv64xxx, sizeof(drv_data->reg_offsets));

drivers/i2c/busses/i2c-mv64xxx.c

127

struct mv64xxx_i2c_regs reg_offsets;

drivers/i2c/busses/i2c-mv64xxx.c

214

writel(0, drv_data->reg_base + drv_data->reg_offsets.soft_reset);

drivers/i2c/busses/i2c-mv64xxx.c

216

drv_data->reg_base + drv_data->reg_offsets.clock);

drivers/i2c/busses/i2c-mv64xxx.c

217

writel(0, drv_data->reg_base + drv_data->reg_offsets.addr);

drivers/i2c/busses/i2c-mv64xxx.c

218

writel(0, drv_data->reg_base + drv_data->reg_offsets.ext_addr);

drivers/i2c/busses/i2c-mv64xxx.c

220

drv_data->reg_base + drv_data->reg_offsets.control);

drivers/i2c/busses/i2c-mv64xxx.c

347

drv_data->reg_base + drv_data->reg_offsets.control);

drivers/i2c/busses/i2c-mv64xxx.c

375

drv_data->reg_base + drv_data->reg_offsets.control);

drivers/i2c/busses/i2c-mv64xxx.c

380

drv_data->reg_base + drv_data->reg_offsets.data);

drivers/i2c/busses/i2c-mv64xxx.c

382

drv_data->reg_base + drv_data->reg_offsets.control);

drivers/i2c/busses/i2c-mv64xxx.c

387

drv_data->reg_base + drv_data->reg_offsets.data);

drivers/i2c/busses/i2c-mv64xxx.c

389

drv_data->reg_base + drv_data->reg_offsets.control);

drivers/i2c/busses/i2c-mv64xxx.c

394

drv_data->reg_base + drv_data->reg_offsets.data);

drivers/i2c/busses/i2c-mv64xxx.c

396

drv_data->reg_base + drv_data->reg_offsets.control);

drivers/i2c/busses/i2c-mv64xxx.c

401

readl(drv_data->reg_base + drv_data->reg_offsets.data);

drivers/i2c/busses/i2c-mv64xxx.c

403

drv_data->reg_base + drv_data->reg_offsets.control);

drivers/i2c/busses/i2c-mv64xxx.c

408

readl(drv_data->reg_base + drv_data->reg_offsets.data);

drivers/i2c/busses/i2c-mv64xxx.c

412

drv_data->reg_base + drv_data->reg_offsets.control);

drivers/i2c/busses/i2c-mv64xxx.c

431

drv_data->reg_base + drv_data->reg_offsets.control);

drivers/i2c/busses/i2c-mv64xxx.c

514

while (readl(drv_data->reg_base + drv_data->reg_offsets.control) &

drivers/i2c/busses/i2c-mv64xxx.c

527

status = readl(drv_data->reg_base + drv_data->reg_offsets.status);

drivers/i2c/busses/i2c-mv64xxx.c

533

drv_data->reg_base + drv_data->reg_offsets.control);

drivers/i2c/busses/i2c-mv64xxx.c

896

memcpy(&drv_data->reg_offsets, data, sizeof(drv_data->reg_offsets));

drivers/mtd/nand/raw/brcmnand/brcmnand.c

1512

offset0 = ctrl->reg_offsets[BRCMNAND_OOB_READ_BASE];

drivers/mtd/nand/raw/brcmnand/brcmnand.c

1513

offset10 = ctrl->reg_offsets[BRCMNAND_OOB_READ_10_BASE];

drivers/mtd/nand/raw/brcmnand/brcmnand.c

1531

offset0 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_BASE];

drivers/mtd/nand/raw/brcmnand/brcmnand.c

1532

offset10 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_10_BASE];

drivers/mtd/nand/raw/brcmnand/brcmnand.c

297

const u16 *reg_offsets;

drivers/mtd/nand/raw/brcmnand/brcmnand.c

3376

ctrl->reg_offsets[BRCMNAND_FC_BASE];

drivers/mtd/nand/raw/brcmnand/brcmnand.c

712

ctrl->reg_offsets = brcmnand_regs_v72;

drivers/mtd/nand/raw/brcmnand/brcmnand.c

714

ctrl->reg_offsets = brcmnand_regs_v71;

drivers/mtd/nand/raw/brcmnand/brcmnand.c

716

ctrl->reg_offsets = brcmnand_regs_v60;

drivers/mtd/nand/raw/brcmnand/brcmnand.c

718

ctrl->reg_offsets = brcmnand_regs_v50;

drivers/mtd/nand/raw/brcmnand/brcmnand.c

720

ctrl->reg_offsets = brcmnand_regs_v33;

drivers/mtd/nand/raw/brcmnand/brcmnand.c

722

ctrl->reg_offsets = brcmnand_regs_v21;

drivers/mtd/nand/raw/brcmnand/brcmnand.c

830

u16 offs = ctrl->reg_offsets[reg];

drivers/mtd/nand/raw/brcmnand/brcmnand.c

841

u16 offs = ctrl->reg_offsets[reg];

drivers/mtd/nand/raw/brcmnand/brcmnand.c

955

u16 offs_cs0 = ctrl->reg_offsets[BRCMNAND_CS0_BASE];

drivers/mtd/nand/raw/brcmnand/brcmnand.c

956

u16 offs_cs1 = ctrl->reg_offsets[BRCMNAND_CS1_BASE];

drivers/mtd/nand/raw/brcmnand/brcmnand.c

984

if (!ctrl->reg_offsets[reg])

drivers/net/dsa/bcm_sf2.c

1265

const u16 *reg_offsets;

drivers/net/dsa/bcm_sf2.c

1295

.reg_offsets = bcm_sf2_4908_reg_offsets,

drivers/net/dsa/bcm_sf2.c

1321

.reg_offsets = bcm_sf2_7445_reg_offsets,

drivers/net/dsa/bcm_sf2.c

1344

.reg_offsets = bcm_sf2_7278_reg_offsets,

drivers/net/dsa/bcm_sf2.c

1406

priv->reg_offsets = data->reg_offsets;

drivers/net/dsa/bcm_sf2.h

196

return readl_relaxed(priv->reg + priv->reg_offsets[off]);

drivers/net/dsa/bcm_sf2.h

201

writel_relaxed(val, priv->reg + priv->reg_offsets[off]);

drivers/net/dsa/bcm_sf2.h

215

return readl_relaxed(priv->reg + priv->reg_offsets[off] + reg);

drivers/net/dsa/bcm_sf2.h

220

writel_relaxed(val, priv->reg + priv->reg_offsets[off] + reg);

drivers/net/dsa/bcm_sf2.h

74

const u16 *reg_offsets;

drivers/net/ethernet/8390/ax88796.c

894

if (ax->plat->reg_offsets)

drivers/net/ethernet/8390/ax88796.c

895

ei_local->reg_offset = ax->plat->reg_offsets;

drivers/net/ethernet/8390/ax88796.c

897

ei_local->reg_offset = ax->reg_offsets;

drivers/net/ethernet/8390/ax88796.c

899

ax->reg_offsets[ret] = (mem_size / 0x18) * ret;

drivers/net/ethernet/8390/ax88796.c

921

if (!ax->plat->reg_offsets) {

drivers/net/ethernet/8390/ax88796.c

923

ax->reg_offsets[ret] = (mem_size / 0x20) * ret;

drivers/net/ethernet/8390/ax88796.c

95

u32 reg_offsets[0x20];

drivers/net/ethernet/8390/xsurf100.c

254

static u32 reg_offsets[32];

drivers/net/ethernet/8390/xsurf100.c

277

reg_offsets[reg] = 4 * reg;

drivers/net/ethernet/8390/xsurf100.c

284

ax88796_data.ax.reg_offsets = reg_offsets;

drivers/pci/controller/dwc/pcie-al.c

136

struct al_pcie_reg_offsets reg_offsets;

drivers/pci/controller/dwc/pcie-al.c

188

pcie->reg_offsets.ob_ctrl = OB_CTRL_REV1_2_OFFSET;

drivers/pci/controller/dwc/pcie-al.c

192

pcie->reg_offsets.ob_ctrl = OB_CTRL_REV3_5_OFFSET;

drivers/pci/controller/dwc/pcie-al.c

213

pcie->reg_offsets.ob_ctrl + CFG_TARGET_BUS,

drivers/pci/controller/dwc/pcie-al.c

284

cfg_control_offset = AXI_BASE_OFFSET + pcie->reg_offsets.ob_ctrl +

drivers/pci/controller/pcie-iproc-msi.c

133

return readl_relaxed(pcie->base + msi->reg_offsets[eq][reg]);

drivers/pci/controller/pcie-iproc-msi.c

142

writel_relaxed(val, pcie->base + msi->reg_offsets[eq][reg]);

drivers/pci/controller/pcie-iproc-msi.c

570

msi->reg_offsets = iproc_msi_reg_paxb;

drivers/pci/controller/pcie-iproc-msi.c

575

msi->reg_offsets = iproc_msi_reg_paxc;

drivers/pci/controller/pcie-iproc-msi.c

95

const u16 (*reg_offsets)[IPROC_MSI_REG_SIZE];

drivers/pci/controller/pcie-iproc.c

1429

pcie->reg_offsets = devm_kcalloc(dev, IPROC_PCIE_MAX_NUM_REG,

drivers/pci/controller/pcie-iproc.c

1430

sizeof(*pcie->reg_offsets),

drivers/pci/controller/pcie-iproc.c

1432

if (!pcie->reg_offsets)

drivers/pci/controller/pcie-iproc.c

1436

pcie->reg_offsets[0] = (pcie->type == IPROC_PCIE_PAXC_V2) ?

drivers/pci/controller/pcie-iproc.c

1439

pcie->reg_offsets[reg_idx] = regs[reg_idx] ?

drivers/pci/controller/pcie-iproc.c

413

return pcie->reg_offsets[reg];

drivers/pci/controller/pcie-iproc.h

89

u16 *reg_offsets;

drivers/spi/spi-bcm63xx.c

141

const unsigned long *reg_offsets;

drivers/spi/spi-bcm63xx.c

157

return readb(bs->regs + bs->reg_offsets[offset]);

drivers/spi/spi-bcm63xx.c

163

writeb(value, bs->regs + bs->reg_offsets[offset]);

drivers/spi/spi-bcm63xx.c

170

iowrite16be(value, bs->regs + bs->reg_offsets[offset]);

drivers/spi/spi-bcm63xx.c

172

writew(value, bs->regs + bs->reg_offsets[offset]);

drivers/spi/spi-bcm63xx.c

564

bs->reg_offsets = bcm63xx_spireg;

drivers/spi/spi-bcm63xx.c

565

bs->fifo_size = bs->reg_offsets[SPI_MSG_DATA_SIZE];

drivers/spi/spi-bcm63xx.c

582

bs->msg_type_shift = bs->reg_offsets[SPI_MSG_TYPE_SHIFT];

drivers/spi/spi-bcm63xx.c

583

bs->msg_ctl_width = bs->reg_offsets[SPI_MSG_CTL_WIDTH];

drivers/spi/spi-bcm63xx.c

584

bs->tx_io = bs->regs + bs->reg_offsets[SPI_MSG_DATA];

drivers/spi/spi-bcm63xx.c

585

bs->rx_io = bs->regs + bs->reg_offsets[SPI_RX_DATA];

include/net/ax88796.h

28

u32 *reg_offsets; /* register offsets */