arch/arm64/include/asm/kvm_emulate.h

168

u8 reg_num)

arch/arm64/include/asm/kvm_emulate.h

170

return (reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];

arch/arm64/include/asm/kvm_emulate.h

173

static __always_inline void vcpu_set_reg(struct kvm_vcpu *vcpu, u8 reg_num,

arch/arm64/include/asm/kvm_emulate.h

176

if (reg_num != 31)

arch/arm64/include/asm/kvm_emulate.h

177

vcpu_gp_regs(vcpu)->regs[reg_num] = val;

arch/arm64/kvm/guest.c

432

unsigned int reg_num;

arch/arm64/kvm/guest.c

448

reg_num = (reg->id & SVE_REG_ID_MASK) >> SVE_REG_ID_SHIFT;

arch/arm64/kvm/guest.c

456

reqoffset = SVE_SIG_ZREG_OFFSET(vq, reg_num) -

arch/arm64/kvm/guest.c

466

reqoffset = SVE_SIG_PREG_OFFSET(vq, reg_num) -

arch/powerpc/include/asm/mpic_msgr.h

33

extern struct mpic_msgr *mpic_msgr_get(unsigned int reg_num);

arch/powerpc/platforms/powernv/opal-fadump.h

141

be32_to_cpu(reg_entry->reg_num),

arch/powerpc/platforms/powernv/opal-fadump.h

82

__be32 reg_num;

arch/powerpc/platforms/powernv/opal-fadump.h

87

u32 reg_type, u32 reg_num,

arch/powerpc/platforms/powernv/opal-fadump.h

91

if (reg_num < 32)

arch/powerpc/platforms/powernv/opal-fadump.h

92

regs->gpr[reg_num] = reg_val;

arch/powerpc/platforms/powernv/opal-fadump.h

96

switch (reg_num) {

arch/powerpc/sysdev/mpic_msgr.c

49

struct mpic_msgr *mpic_msgr_get(unsigned int reg_num)

arch/powerpc/sysdev/mpic_msgr.c

57

if (reg_num >= mpic_msgr_count)

arch/powerpc/sysdev/mpic_msgr.c

61

msgr = mpic_msgrs[reg_num];

arch/riscv/include/asm/kvm_aia.h

133

unsigned long reg_num,

arch/riscv/include/asm/kvm_aia.h

136

unsigned long reg_num,

arch/riscv/include/asm/kvm_vcpu_sbi.h

66

int (*get_state_reg)(struct kvm_vcpu *vcpu, unsigned long reg_num,

arch/riscv/include/asm/kvm_vcpu_sbi.h

68

int (*set_state_reg)(struct kvm_vcpu *vcpu, unsigned long reg_num,

arch/riscv/kvm/aia.c

182

unsigned long reg_num,

arch/riscv/kvm/aia.c

190

if (reg_num >= regs_max)

arch/riscv/kvm/aia.c

193

reg_num = array_index_nospec(reg_num, regs_max);

arch/riscv/kvm/aia.c

197

*out_val = ((unsigned long *)csr)[reg_num];

arch/riscv/kvm/aia.c

203

unsigned long reg_num,

arch/riscv/kvm/aia.c

211

if (reg_num >= regs_max)

arch/riscv/kvm/aia.c

214

reg_num = array_index_nospec(reg_num, regs_max);

arch/riscv/kvm/aia.c

217

((unsigned long *)csr)[reg_num] = val;

arch/riscv/kvm/aia.c

220

if (reg_num == KVM_REG_RISCV_CSR_AIA_REG(siph))

arch/riscv/kvm/vcpu_fp.c

100

reg_val = &cntx->fp.f.f[reg_num];

arch/riscv/kvm/vcpu_fp.c

105

if (reg_num == KVM_REG_RISCV_FP_D_REG(fcsr)) {

arch/riscv/kvm/vcpu_fp.c

109

} else if ((KVM_REG_RISCV_FP_D_REG(f[0]) <= reg_num) &&

arch/riscv/kvm/vcpu_fp.c

110

reg_num <= KVM_REG_RISCV_FP_D_REG(f[31])) {

arch/riscv/kvm/vcpu_fp.c

113

reg_num = array_index_nospec(reg_num,

arch/riscv/kvm/vcpu_fp.c

115

reg_val = &cntx->fp.d.f[reg_num];

arch/riscv/kvm/vcpu_fp.c

134

unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |

arch/riscv/kvm/vcpu_fp.c

143

if (reg_num == KVM_REG_RISCV_FP_F_REG(fcsr))

arch/riscv/kvm/vcpu_fp.c

145

else if ((KVM_REG_RISCV_FP_F_REG(f[0]) <= reg_num) &&

arch/riscv/kvm/vcpu_fp.c

146

reg_num <= KVM_REG_RISCV_FP_F_REG(f[31])) {

arch/riscv/kvm/vcpu_fp.c

147

reg_num = array_index_nospec(reg_num,

arch/riscv/kvm/vcpu_fp.c

149

reg_val = &cntx->fp.f.f[reg_num];

arch/riscv/kvm/vcpu_fp.c

154

if (reg_num == KVM_REG_RISCV_FP_D_REG(fcsr)) {

arch/riscv/kvm/vcpu_fp.c

158

} else if ((KVM_REG_RISCV_FP_D_REG(f[0]) <= reg_num) &&

arch/riscv/kvm/vcpu_fp.c

159

reg_num <= KVM_REG_RISCV_FP_D_REG(f[31])) {

arch/riscv/kvm/vcpu_fp.c

162

reg_num = array_index_nospec(reg_num,

arch/riscv/kvm/vcpu_fp.c

164

reg_val = &cntx->fp.d.f[reg_num];

arch/riscv/kvm/vcpu_fp.c

85

unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |

arch/riscv/kvm/vcpu_fp.c

94

if (reg_num == KVM_REG_RISCV_FP_F_REG(fcsr))

arch/riscv/kvm/vcpu_fp.c

96

else if ((KVM_REG_RISCV_FP_F_REG(f[0]) <= reg_num) &&

arch/riscv/kvm/vcpu_fp.c

97

reg_num <= KVM_REG_RISCV_FP_F_REG(f[31])) {

arch/riscv/kvm/vcpu_fp.c

98

reg_num = array_index_nospec(reg_num,

arch/riscv/kvm/vcpu_onereg.c

280

unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |

arch/riscv/kvm/vcpu_onereg.c

288

switch (reg_num) {

arch/riscv/kvm/vcpu_onereg.c

334

unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |

arch/riscv/kvm/vcpu_onereg.c

345

switch (reg_num) {

arch/riscv/kvm/vcpu_onereg.c

445

unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |

arch/riscv/kvm/vcpu_onereg.c

453

if (reg_num >= regs_max)

arch/riscv/kvm/vcpu_onereg.c

456

reg_num = array_index_nospec(reg_num, regs_max);

arch/riscv/kvm/vcpu_onereg.c

458

if (reg_num == KVM_REG_RISCV_CORE_REG(regs.pc))

arch/riscv/kvm/vcpu_onereg.c

460

else if (KVM_REG_RISCV_CORE_REG(regs.pc) < reg_num &&

arch/riscv/kvm/vcpu_onereg.c

461

reg_num <= KVM_REG_RISCV_CORE_REG(regs.t6))

arch/riscv/kvm/vcpu_onereg.c

462

reg_val = ((unsigned long *)cntx)[reg_num];

arch/riscv/kvm/vcpu_onereg.c

463

else if (reg_num == KVM_REG_RISCV_CORE_REG(mode))

arch/riscv/kvm/vcpu_onereg.c

481

unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |

arch/riscv/kvm/vcpu_onereg.c

489

if (reg_num >= regs_max)

arch/riscv/kvm/vcpu_onereg.c

492

reg_num = array_index_nospec(reg_num, regs_max);

arch/riscv/kvm/vcpu_onereg.c

497

if (reg_num == KVM_REG_RISCV_CORE_REG(regs.pc))

arch/riscv/kvm/vcpu_onereg.c

499

else if (KVM_REG_RISCV_CORE_REG(regs.pc) < reg_num &&

arch/riscv/kvm/vcpu_onereg.c

500

reg_num <= KVM_REG_RISCV_CORE_REG(regs.t6))

arch/riscv/kvm/vcpu_onereg.c

501

((unsigned long *)cntx)[reg_num] = reg_val;

arch/riscv/kvm/vcpu_onereg.c

502

else if (reg_num == KVM_REG_RISCV_CORE_REG(mode)) {

arch/riscv/kvm/vcpu_onereg.c

514

unsigned long reg_num,

arch/riscv/kvm/vcpu_onereg.c

520

if (reg_num >= regs_max)

arch/riscv/kvm/vcpu_onereg.c

523

reg_num = array_index_nospec(reg_num, regs_max);

arch/riscv/kvm/vcpu_onereg.c

525

if (reg_num == KVM_REG_RISCV_CSR_REG(sip)) {

arch/riscv/kvm/vcpu_onereg.c

530

*out_val = ((unsigned long *)csr)[reg_num];

arch/riscv/kvm/vcpu_onereg.c

536

unsigned long reg_num,

arch/riscv/kvm/vcpu_onereg.c

542

if (reg_num >= regs_max)

arch/riscv/kvm/vcpu_onereg.c

545

reg_num = array_index_nospec(reg_num, regs_max);

arch/riscv/kvm/vcpu_onereg.c

547

if (reg_num == KVM_REG_RISCV_CSR_REG(sip)) {

arch/riscv/kvm/vcpu_onereg.c

552

((unsigned long *)csr)[reg_num] = reg_val;

arch/riscv/kvm/vcpu_onereg.c

554

if (reg_num == KVM_REG_RISCV_CSR_REG(sip))

arch/riscv/kvm/vcpu_onereg.c

561

unsigned long reg_num,

arch/riscv/kvm/vcpu_onereg.c

570

if (reg_num >= regs_max)

arch/riscv/kvm/vcpu_onereg.c

573

reg_num = array_index_nospec(reg_num, regs_max);

arch/riscv/kvm/vcpu_onereg.c

575

((unsigned long *)csr)[reg_num] = reg_val;

arch/riscv/kvm/vcpu_onereg.c

580

unsigned long reg_num,

arch/riscv/kvm/vcpu_onereg.c

589

if (reg_num >= regs_max)

arch/riscv/kvm/vcpu_onereg.c

592

reg_num = array_index_nospec(reg_num, regs_max);

arch/riscv/kvm/vcpu_onereg.c

594

*out_val = ((unsigned long *)csr)[reg_num];

arch/riscv/kvm/vcpu_onereg.c

604

unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |

arch/riscv/kvm/vcpu_onereg.c

612

reg_subtype = reg_num & KVM_REG_RISCV_SUBTYPE_MASK;

arch/riscv/kvm/vcpu_onereg.c

613

reg_num &= ~KVM_REG_RISCV_SUBTYPE_MASK;

arch/riscv/kvm/vcpu_onereg.c

616

rc = kvm_riscv_vcpu_general_get_csr(vcpu, reg_num, &reg_val);

arch/riscv/kvm/vcpu_onereg.c

619

rc = kvm_riscv_vcpu_aia_get_csr(vcpu, reg_num, &reg_val);

arch/riscv/kvm/vcpu_onereg.c

622

rc = kvm_riscv_vcpu_smstateen_get_csr(vcpu, reg_num, &reg_val);

arch/riscv/kvm/vcpu_onereg.c

643

unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |

arch/riscv/kvm/vcpu_onereg.c

654

reg_subtype = reg_num & KVM_REG_RISCV_SUBTYPE_MASK;

arch/riscv/kvm/vcpu_onereg.c

655

reg_num &= ~KVM_REG_RISCV_SUBTYPE_MASK;

arch/riscv/kvm/vcpu_onereg.c

658

rc = kvm_riscv_vcpu_general_set_csr(vcpu, reg_num, reg_val);

arch/riscv/kvm/vcpu_onereg.c

661

rc = kvm_riscv_vcpu_aia_set_csr(vcpu, reg_num, reg_val);

arch/riscv/kvm/vcpu_onereg.c

664

rc = kvm_riscv_vcpu_smstateen_set_csr(vcpu, reg_num, reg_val);

arch/riscv/kvm/vcpu_onereg.c

677

unsigned long reg_num,

arch/riscv/kvm/vcpu_onereg.c

683

ret = kvm_riscv_vcpu_isa_check_host(reg_num, &guest_ext);

arch/riscv/kvm/vcpu_onereg.c

695

unsigned long reg_num,

arch/riscv/kvm/vcpu_onereg.c

701

ret = kvm_riscv_vcpu_isa_check_host(reg_num, &guest_ext);

arch/riscv/kvm/vcpu_onereg.c

714

kvm_riscv_vcpu_isa_enable_allowed(reg_num))

arch/riscv/kvm/vcpu_onereg.c

717

kvm_riscv_vcpu_isa_disable_allowed(reg_num))

arch/riscv/kvm/vcpu_onereg.c

730

unsigned long reg_num,

arch/riscv/kvm/vcpu_onereg.c

735

if (reg_num > KVM_REG_RISCV_ISA_MULTI_REG_LAST)

arch/riscv/kvm/vcpu_onereg.c

739

ext_id = i + reg_num * BITS_PER_LONG;

arch/riscv/kvm/vcpu_onereg.c

753

unsigned long reg_num,

arch/riscv/kvm/vcpu_onereg.c

758

if (reg_num > KVM_REG_RISCV_ISA_MULTI_REG_LAST)

arch/riscv/kvm/vcpu_onereg.c

762

ext_id = i + reg_num * BITS_PER_LONG;

arch/riscv/kvm/vcpu_onereg.c

778

unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |

arch/riscv/kvm/vcpu_onereg.c

786

reg_subtype = reg_num & KVM_REG_RISCV_SUBTYPE_MASK;

arch/riscv/kvm/vcpu_onereg.c

787

reg_num &= ~KVM_REG_RISCV_SUBTYPE_MASK;

arch/riscv/kvm/vcpu_onereg.c

792

rc = riscv_vcpu_get_isa_ext_single(vcpu, reg_num, &reg_val);

arch/riscv/kvm/vcpu_onereg.c

796

rc = riscv_vcpu_get_isa_ext_multi(vcpu, reg_num, &reg_val);

arch/riscv/kvm/vcpu_onereg.c

817

unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |

arch/riscv/kvm/vcpu_onereg.c

825

reg_subtype = reg_num & KVM_REG_RISCV_SUBTYPE_MASK;

arch/riscv/kvm/vcpu_onereg.c

826

reg_num &= ~KVM_REG_RISCV_SUBTYPE_MASK;

arch/riscv/kvm/vcpu_onereg.c

833

return riscv_vcpu_set_isa_ext_single(vcpu, reg_num, reg_val);

arch/riscv/kvm/vcpu_onereg.c

835

return riscv_vcpu_set_isa_ext_multi(vcpu, reg_num, reg_val, true);

arch/riscv/kvm/vcpu_onereg.c

837

return riscv_vcpu_set_isa_ext_multi(vcpu, reg_num, reg_val, false);

arch/riscv/kvm/vcpu_sbi.c

219

unsigned long reg_num,

arch/riscv/kvm/vcpu_sbi.c

228

sext = riscv_vcpu_get_sbi_ext(vcpu, reg_num);

arch/riscv/kvm/vcpu_sbi.c

240

unsigned long reg_num,

arch/riscv/kvm/vcpu_sbi.c

246

sext = riscv_vcpu_get_sbi_ext(vcpu, reg_num);

arch/riscv/kvm/vcpu_sbi.c

257

unsigned long reg_num,

arch/riscv/kvm/vcpu_sbi.c

262

if (reg_num > KVM_REG_RISCV_SBI_MULTI_REG_LAST)

arch/riscv/kvm/vcpu_sbi.c

266

ext_id = i + reg_num * BITS_PER_LONG;

arch/riscv/kvm/vcpu_sbi.c

277

unsigned long reg_num,

arch/riscv/kvm/vcpu_sbi.c

282

if (reg_num > KVM_REG_RISCV_SBI_MULTI_REG_LAST)

arch/riscv/kvm/vcpu_sbi.c

286

ext_id = i + reg_num * BITS_PER_LONG;

arch/riscv/kvm/vcpu_sbi.c

329

unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |

arch/riscv/kvm/vcpu_sbi.c

340

reg_subtype = reg_num & KVM_REG_RISCV_SUBTYPE_MASK;

arch/riscv/kvm/vcpu_sbi.c

341

reg_num &= ~KVM_REG_RISCV_SUBTYPE_MASK;

arch/riscv/kvm/vcpu_sbi.c

348

return riscv_vcpu_set_sbi_ext_single(vcpu, reg_num, reg_val);

arch/riscv/kvm/vcpu_sbi.c

350

return riscv_vcpu_set_sbi_ext_multi(vcpu, reg_num, reg_val, true);

arch/riscv/kvm/vcpu_sbi.c

352

return riscv_vcpu_set_sbi_ext_multi(vcpu, reg_num, reg_val, false);

arch/riscv/kvm/vcpu_sbi.c

366

unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |

arch/riscv/kvm/vcpu_sbi.c

374

reg_subtype = reg_num & KVM_REG_RISCV_SUBTYPE_MASK;

arch/riscv/kvm/vcpu_sbi.c

375

reg_num &= ~KVM_REG_RISCV_SUBTYPE_MASK;

arch/riscv/kvm/vcpu_sbi.c

380

rc = riscv_vcpu_get_sbi_ext_single(vcpu, reg_num, &reg_val);

arch/riscv/kvm/vcpu_sbi.c

384

rc = riscv_vcpu_get_sbi_ext_multi(vcpu, reg_num, &reg_val);

arch/riscv/kvm/vcpu_sbi.c

471

unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |

arch/riscv/kvm/vcpu_sbi.c

502

reg_subtype = reg_num & KVM_REG_RISCV_SUBTYPE_MASK;

arch/riscv/kvm/vcpu_sbi.c

503

reg_num &= ~KVM_REG_RISCV_SUBTYPE_MASK;

arch/riscv/kvm/vcpu_sbi.c

509

return ext->set_state_reg(vcpu, reg_num, KVM_REG_SIZE(reg->id), reg_val);

arch/riscv/kvm/vcpu_sbi.c

516

unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |

arch/riscv/kvm/vcpu_sbi.c

545

reg_subtype = reg_num & KVM_REG_RISCV_SUBTYPE_MASK;

arch/riscv/kvm/vcpu_sbi.c

546

reg_num &= ~KVM_REG_RISCV_SUBTYPE_MASK;

arch/riscv/kvm/vcpu_sbi.c

552

ret = ext->get_state_reg(vcpu, reg_num, KVM_REG_SIZE(reg->id), reg_val);

arch/riscv/kvm/vcpu_sbi_fwft.c

241

static const struct kvm_sbi_fwft_feature *kvm_sbi_fwft_regnum_to_feature(unsigned long reg_num)

arch/riscv/kvm/vcpu_sbi_fwft.c

248

if (feature->first_reg_num <= reg_num && reg_num < (feature->first_reg_num + 3))

arch/riscv/kvm/vcpu_sbi_fwft.c

449

static int kvm_sbi_ext_fwft_get_reg(struct kvm_vcpu *vcpu, unsigned long reg_num,

arch/riscv/kvm/vcpu_sbi_fwft.c

461

feature = kvm_sbi_fwft_regnum_to_feature(reg_num);

arch/riscv/kvm/vcpu_sbi_fwft.c

469

switch (reg_num - feature->first_reg_num) {

arch/riscv/kvm/vcpu_sbi_fwft.c

486

static int kvm_sbi_ext_fwft_set_reg(struct kvm_vcpu *vcpu, unsigned long reg_num,

arch/riscv/kvm/vcpu_sbi_fwft.c

498

feature = kvm_sbi_fwft_regnum_to_feature(reg_num);

arch/riscv/kvm/vcpu_sbi_fwft.c

506

switch (reg_num - feature->first_reg_num) {

arch/riscv/kvm/vcpu_sbi_sta.c

154

static int kvm_sbi_ext_sta_get_reg(struct kvm_vcpu *vcpu, unsigned long reg_num,

arch/riscv/kvm/vcpu_sbi_sta.c

163

switch (reg_num) {

arch/riscv/kvm/vcpu_sbi_sta.c

180

static int kvm_sbi_ext_sta_set_reg(struct kvm_vcpu *vcpu, unsigned long reg_num,

arch/riscv/kvm/vcpu_sbi_sta.c

189

switch (reg_num) {

arch/riscv/kvm/vcpu_timer.c

166

unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |

arch/riscv/kvm/vcpu_timer.c

173

if (reg_num >= sizeof(struct kvm_riscv_timer) / sizeof(u64))

arch/riscv/kvm/vcpu_timer.c

176

switch (reg_num) {

arch/riscv/kvm/vcpu_timer.c

206

unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |

arch/riscv/kvm/vcpu_timer.c

214

if (reg_num >= sizeof(struct kvm_riscv_timer) / sizeof(u64))

arch/riscv/kvm/vcpu_timer.c

220

switch (reg_num) {

arch/riscv/kvm/vcpu_vector.c

104

if (reg_num < KVM_REG_RISCV_VECTOR_REG(0)) {

arch/riscv/kvm/vcpu_vector.c

107

switch (reg_num) {

arch/riscv/kvm/vcpu_vector.c

127

} else if (reg_num <= KVM_REG_RISCV_VECTOR_REG(31)) {

arch/riscv/kvm/vcpu_vector.c

131

(reg_num - KVM_REG_RISCV_VECTOR_REG(0)) * vlenb;

arch/riscv/kvm/vcpu_vector.c

145

unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |

arch/riscv/kvm/vcpu_vector.c

155

rc = kvm_riscv_vcpu_vreg_addr(vcpu, reg_num, reg_size, &reg_addr);

arch/riscv/kvm/vcpu_vector.c

171

unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |

arch/riscv/kvm/vcpu_vector.c

181

if (reg_num == KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)) {

arch/riscv/kvm/vcpu_vector.c

195

rc = kvm_riscv_vcpu_vreg_addr(vcpu, reg_num, reg_size, &reg_addr);

arch/riscv/kvm/vcpu_vector.c

97

unsigned long reg_num,

arch/sh/kernel/dwarf.c

105

unsigned int reg_num)

arch/sh/kernel/dwarf.c

110

if (reg->number == reg_num)

arch/sh/kernel/dwarf.c

63

unsigned int reg_num)

arch/sh/kernel/dwarf.c

77

reg->number = reg_num;

arch/sparc/include/asm/hypervisor.h

3445

unsigned long sun4v_vt_get_perfreg(unsigned long reg_num,

arch/sparc/include/asm/hypervisor.h

3447

unsigned long sun4v_vt_set_perfreg(unsigned long reg_num,

arch/sparc/include/asm/hypervisor.h

3455

unsigned long sun4v_t5_get_perfreg(unsigned long reg_num,

arch/sparc/include/asm/hypervisor.h

3457

unsigned long sun4v_t5_set_perfreg(unsigned long reg_num,

arch/sparc/include/asm/hypervisor.h

3466

unsigned long sun4v_m7_get_perfreg(unsigned long reg_num,

arch/sparc/include/asm/hypervisor.h

3468

unsigned long sun4v_m7_set_perfreg(unsigned long reg_num,

arch/sparc/kernel/pcr.c

111

static void n2_pcr_write(unsigned long reg_num, u64 val)

arch/sparc/kernel/pcr.c

115

WARN_ON_ONCE(reg_num != 0);

arch/sparc/kernel/pcr.c

119

direct_pcr_write(reg_num, val);

arch/sparc/kernel/pcr.c

121

direct_pcr_write(reg_num, val);

arch/sparc/kernel/pcr.c

144

static u64 n4_pcr_read(unsigned long reg_num)

arch/sparc/kernel/pcr.c

148

(void) sun4v_vt_get_perfreg(reg_num, &val);

arch/sparc/kernel/pcr.c

153

static void n4_pcr_write(unsigned long reg_num, u64 val)

arch/sparc/kernel/pcr.c

155

(void) sun4v_vt_set_perfreg(reg_num, val);

arch/sparc/kernel/pcr.c

158

static u64 n4_pic_read(unsigned long reg_num)

arch/sparc/kernel/pcr.c

164

: "r" (reg_num * 0x8UL), "i" (ASI_PIC));

arch/sparc/kernel/pcr.c

169

static void n4_pic_write(unsigned long reg_num, u64 val)

arch/sparc/kernel/pcr.c

173

: "r" (val), "r" (reg_num * 0x8UL), "i" (ASI_PIC));

arch/sparc/kernel/pcr.c

195

static u64 n5_pcr_read(unsigned long reg_num)

arch/sparc/kernel/pcr.c

199

(void) sun4v_t5_get_perfreg(reg_num, &val);

arch/sparc/kernel/pcr.c

204

static void n5_pcr_write(unsigned long reg_num, u64 val)

arch/sparc/kernel/pcr.c

206

(void) sun4v_t5_set_perfreg(reg_num, val);

arch/sparc/kernel/pcr.c

221

static u64 m7_pcr_read(unsigned long reg_num)

arch/sparc/kernel/pcr.c

225

(void) sun4v_m7_get_perfreg(reg_num, &val);

arch/sparc/kernel/pcr.c

230

static void m7_pcr_write(unsigned long reg_num, u64 val)

arch/sparc/kernel/pcr.c

232

(void) sun4v_m7_set_perfreg(reg_num, val);

arch/sparc/kernel/pcr.c

55

static u64 direct_pcr_read(unsigned long reg_num)

arch/sparc/kernel/pcr.c

59

WARN_ON_ONCE(reg_num != 0);

arch/sparc/kernel/pcr.c

64

static void direct_pcr_write(unsigned long reg_num, u64 val)

arch/sparc/kernel/pcr.c

66

WARN_ON_ONCE(reg_num != 0);

arch/sparc/kernel/pcr.c

70

static u64 direct_pic_read(unsigned long reg_num)

arch/sparc/kernel/pcr.c

74

WARN_ON_ONCE(reg_num != 0);

arch/sparc/kernel/pcr.c

79

static void direct_pic_write(unsigned long reg_num, u64 val)

arch/sparc/kernel/pcr.c

81

WARN_ON_ONCE(reg_num != 0);

arch/sparc/kernel/unaligned_32.c

180

static int do_int_store(int reg_num, int size, unsigned long *dst_addr,

arch/sparc/kernel/unaligned_32.c

186

if (reg_num)

arch/sparc/kernel/unaligned_32.c

187

src_val = fetch_reg_addr(reg_num, regs);

arch/sparc/kernel/unaligned_64.c

203

static inline int do_int_store(int reg_num, int size, unsigned long *dst_addr,

arch/sparc/kernel/unaligned_64.c

212

zero = (((long)(reg_num ?

arch/sparc/kernel/unaligned_64.c

213

(unsigned int)fetch_reg(reg_num, regs) : 0)) << 32) |

arch/sparc/kernel/unaligned_64.c

214

(unsigned int)fetch_reg(reg_num + 1, regs);

arch/sparc/kernel/unaligned_64.c

215

} else if (reg_num) {

arch/sparc/kernel/unaligned_64.c

216

src_val_p = fetch_reg_addr(reg_num, regs);

drivers/crypto/intel/qat/qat_common/adf_common_drv.h

164

unsigned short reg_num, unsigned int regdata);

drivers/crypto/intel/qat/qat_common/adf_common_drv.h

168

unsigned short reg_num, unsigned int regdata);

drivers/crypto/intel/qat/qat_common/adf_common_drv.h

172

unsigned short reg_num, unsigned int regdata);

drivers/crypto/intel/qat/qat_common/adf_common_drv.h

175

unsigned short reg_num, unsigned int regdata);

drivers/crypto/intel/qat/qat_common/qat_hal.c

1120

unsigned short reg_num, unsigned int *data)

drivers/crypto/intel/qat/qat_common/qat_hal.c

1128

reg_addr = qat_hal_get_reg_addr(reg_type, reg_num);

drivers/crypto/intel/qat/qat_common/qat_hal.c

1181

unsigned short reg_num, unsigned int data)

drivers/crypto/intel/qat/qat_common/qat_hal.c

1193

dest_addr = qat_hal_get_reg_addr(reg_type, reg_num);

drivers/crypto/intel/qat/qat_common/qat_hal.c

1335

unsigned short reg_num, unsigned int val)

drivers/crypto/intel/qat/qat_common/qat_hal.c

1354

if (reg_num & ~mask)

drivers/crypto/intel/qat/qat_common/qat_hal.c

1356

reg_addr = reg_num + (ctx << 0x5);

drivers/crypto/intel/qat/qat_common/qat_hal.c

1376

unsigned short reg_num, unsigned int data)

drivers/crypto/intel/qat/qat_common/qat_hal.c

1403

if (reg_num & reg_mask)

drivers/crypto/intel/qat/qat_common/qat_hal.c

1405

xfr_addr = qat_hal_get_reg_addr(reg_type, reg_num);

drivers/crypto/intel/qat/qat_common/qat_hal.c

1474

unsigned short reg_num, unsigned int regdata)

drivers/crypto/intel/qat/qat_common/qat_hal.c

1481

if (reg_num >= ICP_QAT_UCLO_MAX_GPR_REG)

drivers/crypto/intel/qat/qat_common/qat_hal.c

1486

qat_hal_convert_abs_to_rel(handle, ae, reg_num, &reg,

drivers/crypto/intel/qat/qat_common/qat_hal.c

1490

reg = reg_num;

drivers/crypto/intel/qat/qat_common/qat_hal.c

1508

unsigned short reg_num, unsigned int regdata)

drivers/crypto/intel/qat/qat_common/qat_hal.c

1515

if (reg_num >= ICP_QAT_UCLO_MAX_XFER_REG)

drivers/crypto/intel/qat/qat_common/qat_hal.c

1520

qat_hal_convert_abs_to_rel(handle, ae, reg_num, &reg,

drivers/crypto/intel/qat/qat_common/qat_hal.c

1524

reg = reg_num;

drivers/crypto/intel/qat/qat_common/qat_hal.c

1543

unsigned short reg_num, unsigned int regdata)

drivers/crypto/intel/qat/qat_common/qat_hal.c

1550

if (reg_num >= ICP_QAT_UCLO_MAX_XFER_REG)

drivers/crypto/intel/qat/qat_common/qat_hal.c

1555

qat_hal_convert_abs_to_rel(handle, ae, reg_num, &reg,

drivers/crypto/intel/qat/qat_common/qat_hal.c

1559

reg = reg_num;

drivers/crypto/intel/qat/qat_common/qat_hal.c

1577

unsigned short reg_num, unsigned int regdata)

drivers/crypto/intel/qat/qat_common/qat_hal.c

1593

stat = qat_hal_put_rel_nn(handle, ae, ctx, reg_num, regdata);

drivers/crypto/intel/qat/qat_common/qat_hal.c

248

unsigned short reg_num)

drivers/crypto/intel/qat/qat_common/qat_hal.c

255

reg_addr = 0x80 | (reg_num & 0x7f);

drivers/crypto/intel/qat/qat_common/qat_hal.c

259

reg_addr = reg_num & 0x1f;

drivers/crypto/intel/qat/qat_common/qat_hal.c

264

reg_addr = 0x180 | (reg_num & 0x1f);

drivers/crypto/intel/qat/qat_common/qat_hal.c

267

reg_addr = 0x140 | ((reg_num & 0x3) << 1);

drivers/crypto/intel/qat/qat_common/qat_hal.c

272

reg_addr = 0x1c0 | (reg_num & 0x1f);

drivers/crypto/intel/qat/qat_common/qat_hal.c

275

reg_addr = 0x100 | ((reg_num & 0x3) << 1);

drivers/crypto/intel/qat/qat_common/qat_hal.c

278

reg_addr = 0x280 | (reg_num & 0x1f);

drivers/crypto/intel/qat/qat_common/qat_hal.c

293

reg_addr = 0x300 | (reg_num & 0xff);

drivers/edac/i10nm_base.c

106

.reg_num = 6,

drivers/edac/i10nm_base.c

128

.reg_num = 6,

drivers/edac/i10nm_base.c

149

.reg_num = 6,

drivers/edac/i10nm_base.c

170

.reg_num = 6,

drivers/edac/i10nm_base.c

353

for (j = 0; j < rrl->reg_num && len - n > 0; j++) {

drivers/edac/i10nm_base.c

85

.reg_num = 6,

drivers/edac/skx_common.h

99

int set_num, reg_num;

drivers/gpu/drm/amd/display/dc/dm_services.h

165

#define get_reg_field_value_soc15(reg_value, block, reg_num, reg_name, reg_field)\

drivers/gpu/drm/amd/display/dc/dm_services.h

168

block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\

drivers/gpu/drm/amd/display/dc/dm_services.h

169

block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT)

drivers/gpu/drm/amd/display/dc/dm_services.h

171

#define set_reg_field_value_soc15(reg_value, value, block, reg_num, reg_name, reg_field)\

drivers/gpu/drm/amd/display/dc/dm_services.h

175

block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\

drivers/gpu/drm/amd/display/dc/dm_services.h

176

block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT)

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

100

.status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

104

#define hpd_rx_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

105

[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

106

.enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

111

.ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

114

.status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

117

#define pflip_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

118

[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

119

.enable_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_CONTROL,\

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

125

.ack_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_STATUS,\

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

128

.status_reg = mmDCP ## reg_num ##_GRPH_INTERRUPT_STATUS,\

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

132

#define vupdate_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

133

[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

134

.enable_reg = mmCRTC ## reg_num ## _CRTC_INTERRUPT_CONTROL,\

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

140

.ack_reg = mmCRTC ## reg_num ## _CRTC_V_UPDATE_INT_STATUS,\

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

148

#define vblank_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

149

[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

150

.enable_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

156

.ack_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

162

.src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

170

#define i2c_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

171

[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

173

#define dp_sink_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

174

[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

176

#define gpio_pad_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

177

[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

179

#define dc_underflow_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

180

[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

89

#define hpd_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

90

[DC_IRQ_SOURCE_HPD1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

91

.enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

97

.ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

100

[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

101

IRQ_REG_ENTRY(HPD, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

104

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

107

#define pflip_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

108

[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

109

IRQ_REG_ENTRY(DCP, reg_num, \

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

112

.status_reg = SRI(GRPH_INTERRUPT_STATUS, DCP, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

116

#define vupdate_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

117

[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

118

IRQ_REG_ENTRY(CRTC, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

124

#define vblank_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

125

[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

126

IRQ_REG_ENTRY(CRTC, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

130

.src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

138

#define i2c_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

139

[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

141

#define dp_sink_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

142

[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

144

#define gpio_pad_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

145

[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

147

#define dc_underflow_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

148

[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

76

#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

77

.enable_reg = SRI(reg1, block, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

79

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

81

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

82

~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

84

.ack_reg = SRI(reg2, block, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

86

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

88

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

90

#define hpd_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

91

[DC_IRQ_SOURCE_HPD1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

92

IRQ_REG_ENTRY(HPD, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

95

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

99

#define hpd_rx_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

103

#define pflip_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

104

[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

105

.enable_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_CONTROL,\

drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

111

.ack_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_STATUS,\

drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

114

.status_reg = mmDCP ## reg_num ##_GRPH_INTERRUPT_STATUS,\

drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

118

#define vupdate_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

119

[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

120

.enable_reg = mmCRTC ## reg_num ## _CRTC_INTERRUPT_CONTROL,\

drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

126

.ack_reg = mmCRTC ## reg_num ## _CRTC_V_UPDATE_INT_STATUS,\

drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

134

#define vblank_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

135

[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

136

.enable_reg = mmLB ## reg_num ## _INT_MASK,\

drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

142

.ack_reg = mmLB ## reg_num ## _VBLANK_STATUS,\

drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

155

#define i2c_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

156

[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

158

#define dp_sink_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

159

[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

161

#define gpio_pad_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

162

[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

164

#define dc_underflow_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

165

[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

74

#define hpd_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

75

[DC_IRQ_SOURCE_INVALID + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

76

.enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\

drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

82

.ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\

drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

85

.status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\

drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

89

#define hpd_rx_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

90

[DC_IRQ_SOURCE_HPD6 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

91

.enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\

drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

96

.ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\

drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

99

.status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\

drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

102

.ack_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_STATUS,\

drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

105

.status_reg = mmDCP ## reg_num ##_GRPH_INTERRUPT_STATUS,\

drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

109

#define vupdate_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

110

[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

111

.enable_reg = mmCRTC ## reg_num ## _CRTC_INTERRUPT_CONTROL,\

drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

117

.ack_reg = mmCRTC ## reg_num ## _CRTC_V_UPDATE_INT_STATUS,\

drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

125

#define vblank_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

126

[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

127

.enable_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\

drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

133

.ack_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\

drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

139

.src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\

drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

147

#define i2c_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

148

[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

150

#define dp_sink_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

151

[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

153

#define gpio_pad_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

154

[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

156

#define dc_underflow_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

157

[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

65

#define hpd_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

66

[DC_IRQ_SOURCE_INVALID + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

67

.enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\

drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

73

.ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\

drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

76

.status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\

drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

80

#define hpd_rx_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

81

[DC_IRQ_SOURCE_HPD6 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

82

.enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\

drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

87

.ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\

drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

90

.status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\

drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

94

#define pflip_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

95

[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

96

.enable_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_CONTROL,\

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

173

#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

174

.enable_reg = SRI(reg1, block, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

176

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

178

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

179

~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

181

.ack_reg = SRI(reg2, block, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

183

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

185

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

187

#define hpd_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

188

[DC_IRQ_SOURCE_HPD1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

189

IRQ_REG_ENTRY(HPD, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

192

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

196

#define hpd_rx_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

197

[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

198

IRQ_REG_ENTRY(HPD, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

201

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

204

#define pflip_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

205

[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

206

IRQ_REG_ENTRY(HUBPREQ, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

215

#define vupdate_no_lock_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

216

[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

217

IRQ_REG_ENTRY(OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

223

#define vblank_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

224

[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

225

IRQ_REG_ENTRY(OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

231

#define vline0_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

232

[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

233

IRQ_REG_ENTRY(OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

244

#define i2c_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

245

[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

247

#define dp_sink_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

248

[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

250

#define gpio_pad_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

251

[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

253

#define dc_underflow_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

254

[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

176

#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

177

.enable_reg = SRI(reg1, block, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

179

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

181

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

182

~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

184

.ack_reg = SRI(reg2, block, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

186

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

188

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

192

#define hpd_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

193

[DC_IRQ_SOURCE_HPD1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

194

IRQ_REG_ENTRY(HPD, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

197

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

201

#define hpd_rx_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

202

[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

203

IRQ_REG_ENTRY(HPD, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

206

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

209

#define pflip_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

210

[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

211

IRQ_REG_ENTRY(HUBPREQ, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

220

#define vupdate_no_lock_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

221

[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

222

IRQ_REG_ENTRY(OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

228

#define vblank_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

229

[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

230

IRQ_REG_ENTRY(OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

236

#define vline0_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

237

[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

238

IRQ_REG_ENTRY(OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

249

#define i2c_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

250

[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

252

#define dp_sink_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

253

[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

255

#define gpio_pad_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

256

[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

258

#define dc_underflow_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

259

[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

125

#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

126

.enable_reg = SRI(reg1, block, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

128

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

130

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

131

~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

133

.ack_reg = SRI(reg2, block, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

135

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

137

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

139

#define hpd_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

140

[DC_IRQ_SOURCE_HPD1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

141

IRQ_REG_ENTRY(HPD, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

144

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

148

#define hpd_rx_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

149

[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

150

IRQ_REG_ENTRY(HPD, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

153

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

156

#define pflip_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

157

[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

158

IRQ_REG_ENTRY(HUBPREQ, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

164

#define vupdate_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

165

[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

166

IRQ_REG_ENTRY(OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

175

#define vupdate_no_lock_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

176

[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

177

IRQ_REG_ENTRY(OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

182

#define vblank_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

183

[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

184

IRQ_REG_ENTRY(OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

190

#define vline0_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

191

[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

192

IRQ_REG_ENTRY(OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

203

#define i2c_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

204

[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

206

#define dp_sink_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

207

[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

209

#define gpio_pad_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

210

[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

212

#define dc_underflow_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

213

[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

186

#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

187

.enable_reg = SRI(reg1, block, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

189

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

191

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

192

~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

194

.ack_reg = SRI(reg2, block, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

196

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

198

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

214

#define hpd_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

215

[DC_IRQ_SOURCE_HPD1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

216

IRQ_REG_ENTRY(HPD, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

219

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

223

#define hpd_rx_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

224

[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

225

IRQ_REG_ENTRY(HPD, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

228

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

231

#define pflip_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

232

[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

233

IRQ_REG_ENTRY(HUBPREQ, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

242

#define vupdate_no_lock_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

243

[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

244

IRQ_REG_ENTRY(OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

250

#define vblank_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

251

[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

252

IRQ_REG_ENTRY(OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

258

#define vline0_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

259

[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

260

IRQ_REG_ENTRY(OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

278

#define i2c_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

279

[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

281

#define dp_sink_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

282

[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

284

#define gpio_pad_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

285

[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

287

#define dc_underflow_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

288

[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

193

#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

194

.enable_reg = SRI(reg1, block, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

196

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

198

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

199

~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

201

.ack_reg = SRI(reg2, block, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

203

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

205

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

221

#define hpd_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

222

[DC_IRQ_SOURCE_HPD1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

223

IRQ_REG_ENTRY(HPD, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

226

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

230

#define hpd_rx_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

231

[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

232

IRQ_REG_ENTRY(HPD, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

235

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

238

#define pflip_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

239

[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

240

IRQ_REG_ENTRY(HUBPREQ, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

249

#define vupdate_no_lock_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

250

[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

251

IRQ_REG_ENTRY(OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

257

#define vblank_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

258

[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

259

IRQ_REG_ENTRY(OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

272

#define vline0_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

273

[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

274

IRQ_REG_ENTRY(OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

285

#define i2c_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

286

[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

288

#define dp_sink_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

289

[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

291

#define gpio_pad_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

292

[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

294

#define dc_underflow_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

295

[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

178

#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

179

.enable_reg = SRI(reg1, block, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

180

.enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

182

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

183

~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

185

.ack_reg = SRI(reg2, block, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

186

.ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

187

.ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

210

#define hpd_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

211

[DC_IRQ_SOURCE_HPD1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

212

IRQ_REG_ENTRY(HPD, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

215

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

219

#define hpd_rx_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

220

[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

221

IRQ_REG_ENTRY(HPD, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

224

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

227

#define pflip_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

228

[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

229

IRQ_REG_ENTRY(HUBPREQ, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

238

#define vupdate_no_lock_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

239

[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

240

IRQ_REG_ENTRY(OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

246

#define vblank_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

247

[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

248

IRQ_REG_ENTRY(OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

254

#define vline0_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

255

[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

256

IRQ_REG_ENTRY(OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

264

#define i2c_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

265

[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

267

#define dp_sink_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

268

[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

270

#define gpio_pad_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

271

[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

273

#define dc_underflow_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

274

[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

121

#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

122

.enable_reg = SRI(reg1, block, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

123

.enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

125

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

126

~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

128

.ack_reg = SRI(reg2, block, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

129

.ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

130

.ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

134

#define hpd_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

135

[DC_IRQ_SOURCE_HPD1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

136

IRQ_REG_ENTRY(HPD, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

139

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

143

#define hpd_rx_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

144

[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

145

IRQ_REG_ENTRY(HPD, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

148

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

151

#define pflip_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

152

[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

153

IRQ_REG_ENTRY(HUBPREQ, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

162

#define vupdate_no_lock_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

163

[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

164

IRQ_REG_ENTRY(OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

170

#define vblank_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

171

[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

172

IRQ_REG_ENTRY(OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

178

#define vline0_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

179

[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

180

IRQ_REG_ENTRY(OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

188

#define i2c_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

189

[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

191

#define dp_sink_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

192

[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

194

#define gpio_pad_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

195

[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

197

#define dc_underflow_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

198

[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

181

#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

182

.enable_reg = SRI(reg1, block, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

184

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

186

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

187

~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

189

.ack_reg = SRI(reg2, block, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

191

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

193

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

209

#define hpd_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

210

[DC_IRQ_SOURCE_HPD1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

211

IRQ_REG_ENTRY(HPD, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

214

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

218

#define hpd_rx_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

219

[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

220

IRQ_REG_ENTRY(HPD, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

223

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

226

#define pflip_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

227

[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

228

IRQ_REG_ENTRY(HUBPREQ, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

237

#define vupdate_no_lock_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

238

[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

239

IRQ_REG_ENTRY(OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

245

#define vblank_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

246

[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

247

IRQ_REG_ENTRY(OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

253

#define vline0_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

254

[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

255

IRQ_REG_ENTRY(OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

273

#define i2c_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

274

[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

276

#define dp_sink_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

277

[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

279

#define gpio_pad_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

280

[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

282

#define dc_underflow_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

283

[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

183

#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

184

.enable_reg = SRI(reg1, block, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

186

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

188

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

189

~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

191

.ack_reg = SRI(reg2, block, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

193

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

195

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

211

#define hpd_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

212

[DC_IRQ_SOURCE_HPD1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

213

IRQ_REG_ENTRY(HPD, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

216

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

220

#define hpd_rx_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

221

[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

222

IRQ_REG_ENTRY(HPD, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

225

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

228

#define pflip_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

229

[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

230

IRQ_REG_ENTRY(HUBPREQ, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

239

#define vupdate_no_lock_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

240

[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

241

IRQ_REG_ENTRY(OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

247

#define vblank_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

248

[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

249

IRQ_REG_ENTRY(OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

255

#define vline0_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

256

[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

257

IRQ_REG_ENTRY(OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

275

#define i2c_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

276

[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

278

#define dp_sink_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

279

[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

281

#define gpio_pad_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

282

[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

284

#define dc_underflow_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

285

[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

188

#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

189

.enable_reg = SRI(reg1, block, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

191

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

193

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

194

~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

196

.ack_reg = SRI(reg2, block, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

198

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

200

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

216

#define hpd_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

217

[DC_IRQ_SOURCE_HPD1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

218

IRQ_REG_ENTRY(HPD, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

221

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

225

#define hpd_rx_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

226

[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

227

IRQ_REG_ENTRY(HPD, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

230

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

233

#define pflip_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

234

[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

235

IRQ_REG_ENTRY(HUBPREQ, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

244

#define vupdate_no_lock_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

245

[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

246

IRQ_REG_ENTRY(OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

252

#define vblank_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

253

[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

254

IRQ_REG_ENTRY(OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

260

#define vline0_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

261

[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

262

IRQ_REG_ENTRY(OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

280

#define i2c_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

281

[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

283

#define dp_sink_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

284

[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

286

#define gpio_pad_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

287

[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

289

#define dc_underflow_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

290

[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

192

#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

193

.enable_reg = SRI(reg1, block, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

195

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

197

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

198

~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

200

.ack_reg = SRI(reg2, block, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

202

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

204

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

220

#define hpd_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

221

[DC_IRQ_SOURCE_HPD1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

222

IRQ_REG_ENTRY(HPD, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

225

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

229

#define hpd_rx_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

230

[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

231

IRQ_REG_ENTRY(HPD, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

234

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

237

#define pflip_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

238

[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

239

IRQ_REG_ENTRY(HUBPREQ, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

245

#define vblank_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

246

[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

247

IRQ_REG_ENTRY(OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

255

#define vupdate_no_lock_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

256

[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

257

IRQ_REG_ENTRY(OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

263

#define vline0_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

264

[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

265

IRQ_REG_ENTRY(OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

270

#define vline1_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

271

[DC_IRQ_SOURCE_DC1_VLINE1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

272

IRQ_REG_ENTRY(OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

277

#define vline2_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

278

[DC_IRQ_SOURCE_DC1_VLINE2 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

279

IRQ_REG_ENTRY(OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

297

#define i2c_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

298

[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

300

#define dp_sink_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

301

[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

303

#define gpio_pad_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

304

[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

306

#define dc_underflow_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

307

[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

180

#define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

181

REG_STRUCT[base + reg_num].enable_reg = SRI(reg1, block, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

182

REG_STRUCT[base + reg_num].enable_mask = \

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

183

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

184

REG_STRUCT[base + reg_num].enable_value[0] = \

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

185

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

186

REG_STRUCT[base + reg_num].enable_value[1] = \

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

187

~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

188

REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

189

REG_STRUCT[base + reg_num].ack_mask = \

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

190

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

191

REG_STRUCT[base + reg_num].ack_value = \

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

192

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

208

#define hpd_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

209

IRQ_REG_ENTRY(DC_IRQ_SOURCE_HPD1, HPD, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

212

REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].funcs = &hpd_irq_info_funcs;\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

213

REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

215

#define hpd_rx_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

216

IRQ_REG_ENTRY(DC_IRQ_SOURCE_HPD1RX, HPD, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

219

REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

220

REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].funcs = &hpd_rx_irq_info_funcs;\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

222

#define pflip_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

223

IRQ_REG_ENTRY(DC_IRQ_SOURCE_PFLIP1, HUBPREQ, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

226

REG_STRUCT[DC_IRQ_SOURCE_PFLIP1 + reg_num].funcs = &pflip_irq_info_funcs\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

231

#define vupdate_no_lock_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

232

IRQ_REG_ENTRY(DC_IRQ_SOURCE_VUPDATE1, OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

235

REG_STRUCT[DC_IRQ_SOURCE_VUPDATE1 + reg_num].funcs = &vupdate_no_lock_irq_info_funcs\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

237

#define vblank_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

238

IRQ_REG_ENTRY(DC_IRQ_SOURCE_VBLANK1, OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

241

REG_STRUCT[DC_IRQ_SOURCE_VBLANK1 + reg_num].funcs = &vblank_irq_info_funcs\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

243

#define vline0_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

244

IRQ_REG_ENTRY(DC_IRQ_SOURCE_DC1_VLINE0, OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

247

REG_STRUCT[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num].funcs = &vline0_irq_info_funcs\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

258

#define i2c_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

259

dummy_irq_entry(DC_IRQ_SOURCE_I2C_DDC ## reg_num)

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

261

#define dp_sink_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

262

dummy_irq_entry(DC_IRQ_SOURCE_DPSINK ## reg_num)

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

264

#define gpio_pad_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

265

dummy_irq_entry(DC_IRQ_SOURCE_GPIOPAD ## reg_num)

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

267

#define dc_underflow_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

268

dummy_irq_entry(DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW)

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

159

#define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

160

REG_STRUCT[base + reg_num].enable_reg = SRI(reg1, block, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

161

REG_STRUCT[base + reg_num].enable_mask = \

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

162

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

163

REG_STRUCT[base + reg_num].enable_value[0] = \

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

164

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

165

REG_STRUCT[base + reg_num].enable_value[1] = \

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

166

~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

167

REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

168

REG_STRUCT[base + reg_num].ack_mask = \

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

169

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

170

REG_STRUCT[base + reg_num].ack_value = \

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

171

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

187

#define hpd_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

188

IRQ_REG_ENTRY(DC_IRQ_SOURCE_HPD1, HPD, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

191

REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].funcs = &hpd_irq_info_funcs;\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

192

REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

194

#define hpd_rx_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

195

IRQ_REG_ENTRY(DC_IRQ_SOURCE_HPD1RX, HPD, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

198

REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

199

REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].funcs = &hpd_rx_irq_info_funcs;\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

201

#define pflip_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

202

IRQ_REG_ENTRY(DC_IRQ_SOURCE_PFLIP1, HUBPREQ, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

205

REG_STRUCT[DC_IRQ_SOURCE_PFLIP1 + reg_num].funcs = &pflip_irq_info_funcs\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

210

#define vupdate_no_lock_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

211

IRQ_REG_ENTRY(DC_IRQ_SOURCE_VUPDATE1, OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

214

REG_STRUCT[DC_IRQ_SOURCE_VUPDATE1 + reg_num].funcs = &vupdate_no_lock_irq_info_funcs\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

216

#define vblank_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

217

IRQ_REG_ENTRY(DC_IRQ_SOURCE_VBLANK1, OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

220

REG_STRUCT[DC_IRQ_SOURCE_VBLANK1 + reg_num].funcs = &vblank_irq_info_funcs\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

222

#define vline0_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

223

IRQ_REG_ENTRY(DC_IRQ_SOURCE_DC1_VLINE0, OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

226

REG_STRUCT[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num].funcs = &vline0_irq_info_funcs\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

237

#define i2c_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

238

dummy_irq_entry(DC_IRQ_SOURCE_I2C_DDC ## reg_num)

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

240

#define dp_sink_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

241

dummy_irq_entry(DC_IRQ_SOURCE_DPSINK ## reg_num)

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

243

#define gpio_pad_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

244

dummy_irq_entry(DC_IRQ_SOURCE_GPIOPAD ## reg_num)

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

246

#define dc_underflow_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

247

dummy_irq_entry(DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW)

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

158

#define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

159

REG_STRUCT[base + reg_num].enable_reg = SRI(reg1, block, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

160

REG_STRUCT[base + reg_num].enable_mask = \

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

161

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

162

REG_STRUCT[base + reg_num].enable_value[0] = \

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

163

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

164

REG_STRUCT[base + reg_num].enable_value[1] = \

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

165

~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

166

REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

167

REG_STRUCT[base + reg_num].ack_mask = \

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

168

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

169

REG_STRUCT[base + reg_num].ack_value = \

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

170

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

186

#define hpd_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

187

IRQ_REG_ENTRY(DC_IRQ_SOURCE_HPD1, HPD, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

190

REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].funcs = &hpd_irq_info_funcs;\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

191

REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

193

#define hpd_rx_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

194

IRQ_REG_ENTRY(DC_IRQ_SOURCE_HPD1RX, HPD, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

197

REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

198

REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].funcs = &hpd_rx_irq_info_funcs;\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

200

#define pflip_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

201

IRQ_REG_ENTRY(DC_IRQ_SOURCE_PFLIP1, HUBPREQ, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

204

REG_STRUCT[DC_IRQ_SOURCE_PFLIP1 + reg_num].funcs = &pflip_irq_info_funcs\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

209

#define vupdate_no_lock_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

210

IRQ_REG_ENTRY(DC_IRQ_SOURCE_VUPDATE1, OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

213

REG_STRUCT[DC_IRQ_SOURCE_VUPDATE1 + reg_num].funcs = &vupdate_no_lock_irq_info_funcs\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

215

#define vblank_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

216

IRQ_REG_ENTRY(DC_IRQ_SOURCE_VBLANK1, OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

219

REG_STRUCT[DC_IRQ_SOURCE_VBLANK1 + reg_num].funcs = &vblank_irq_info_funcs\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

221

#define vline0_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

222

IRQ_REG_ENTRY(DC_IRQ_SOURCE_DC1_VLINE0, OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

225

REG_STRUCT[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num].funcs = &vline0_irq_info_funcs\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

236

#define i2c_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

237

dummy_irq_entry(DC_IRQ_SOURCE_I2C_DDC ## reg_num)

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

239

#define dp_sink_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

240

dummy_irq_entry(DC_IRQ_SOURCE_DPSINK ## reg_num)

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

242

#define gpio_pad_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

243

dummy_irq_entry(DC_IRQ_SOURCE_GPIOPAD ## reg_num)

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

245

#define dc_underflow_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

246

dummy_irq_entry(DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW)

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

172

#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

173

.enable_reg = SRI(reg1, block, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

175

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

177

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

178

~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

180

.ack_reg = SRI(reg2, block, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

182

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

184

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

200

#define hpd_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

201

[DC_IRQ_SOURCE_HPD1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

202

IRQ_REG_ENTRY(HPD, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

205

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

209

#define hpd_rx_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

210

[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

211

IRQ_REG_ENTRY(HPD, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

214

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

217

#define pflip_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

218

[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

219

IRQ_REG_ENTRY(HUBPREQ, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

225

#define vblank_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

226

[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

227

IRQ_REG_ENTRY(OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

235

#define vupdate_no_lock_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

236

[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

237

IRQ_REG_ENTRY(OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

243

#define vline0_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

244

[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

245

IRQ_REG_ENTRY(OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

250

#define vline1_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

251

[DC_IRQ_SOURCE_DC1_VLINE1 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

252

IRQ_REG_ENTRY(OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

257

#define vline2_int_entry(reg_num)\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

258

[DC_IRQ_SOURCE_DC1_VLINE2 + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

259

IRQ_REG_ENTRY(OTG, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

277

#define i2c_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

278

[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

280

#define dp_sink_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

281

[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

283

#define gpio_pad_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

284

[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

286

#define dc_underflow_int_entry(reg_num) \

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

287

[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

249

settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

261

settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

273

settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

285

settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

303

if (settings->reg_num > 9)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

308

for (i = 0; i < settings->reg_num; i++) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

368

for (i = 0; i < settings->reg_num; i++) {

drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h

282

unsigned char reg_num;

drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.c

30

u32 reg_num;

drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.c

35

reg_num = DIV_ROUND_UP(size, HIBMC_BYTES_IN_U32);

drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.c

36

for (i = 0; i < reg_num; i++) {

drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.c

48

u32 reg_num;

drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.c

53

reg_num = DIV_ROUND_UP(size, HIBMC_BYTES_IN_U32);

drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.c

54

for (i = 0; i < reg_num; i++) {

drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c

101

reg_num = bit_num / 32;

drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c

103

ade_update_bits(base + ADE_RELOAD_DIS(reg_num), bit_ofst,

drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c

109

u32 tmp, bit_ofst, reg_num;

drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c

112

reg_num = bit_num / 32;

drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c

114

tmp = readl(base + ADE_RELOAD_DIS(reg_num));

drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c

98

u32 bit_ofst, reg_num;

drivers/gpu/drm/imagination/pvr_rogue_fwif.h

575

u16 reg_num;

drivers/gpu/drm/imagination/pvr_rogue_meta.h

73

#define META_CR_CORE_REG(thr, reg_num, unit) \

drivers/gpu/drm/imagination/pvr_rogue_meta.h

75

((u32)(reg_num) << META_CR_TXUXXRXRQ_RX_S) | \

drivers/gpu/drm/radeon/evergreen.c

4162

u32 dws, data, i, j, k, reg_num;

drivers/gpu/drm/radeon/evergreen.c

4304

reg_num = cs_data[i].section[j].reg_count;

drivers/gpu/drm/radeon/evergreen.c

4313

data = 0x08000000 | (reg_num * 4);

drivers/gpu/drm/radeon/evergreen.c

4317

for (k = 0; k < reg_num; k++) {

drivers/gpu/drm/radeon/evergreen.c

4321

reg_list_mc_addr += reg_num * 4;

drivers/gpu/drm/radeon/evergreen.c

4322

reg_list_blk_index += reg_num;

drivers/input/keyboard/bcm-keypad.c

102

writel(0xFFFFFFFF, kp->base + KPICRN_OFFSET(reg_num));

drivers/input/keyboard/bcm-keypad.c

104

state = readl(kp->base + KPSSRN_OFFSET(reg_num));

drivers/input/keyboard/bcm-keypad.c

105

change = kp->last_state[reg_num] ^ state;

drivers/input/keyboard/bcm-keypad.c

106

kp->last_state[reg_num] = state;

drivers/input/keyboard/bcm-keypad.c

112

row = BIT_TO_ROW_SSRN(bit_nr, reg_num);

drivers/input/keyboard/bcm-keypad.c

123

int reg_num;

drivers/input/keyboard/bcm-keypad.c

125

for (reg_num = 0; reg_num <= 1; reg_num++)

drivers/input/keyboard/bcm-keypad.c

126

bcm_kp_report_keys(kp, reg_num, pull_mode);

drivers/input/keyboard/bcm-keypad.c

93

static void bcm_kp_report_keys(struct bcm_kp *kp, int reg_num, int pull_mode)

drivers/input/rmi4/rmi_f30.c

104

unsigned int reg_num = button >> 3;

drivers/input/rmi4/rmi_f30.c

107

bool key_down = !(f30->data_regs[reg_num] & BIT(bit_num));

drivers/irqchip/irq-imx-irqsteer.c

146

if (hwirq >= data->reg_num * 32)

drivers/irqchip/irq-imx-irqsteer.c

150

CHANSTATUS(idx, data->reg_num));

drivers/irqchip/irq-imx-irqsteer.c

196

data->reg_num = irqs_num / 32;

drivers/irqchip/irq-imx-irqsteer.c

200

sizeof(u32) * data->reg_num,

drivers/irqchip/irq-imx-irqsteer.c

215

data->domain = irq_domain_create_linear(dev_fwnode(&pdev->dev), data->reg_num * 32,

drivers/irqchip/irq-imx-irqsteer.c

273

for (i = 0; i < data->reg_num; i++)

drivers/irqchip/irq-imx-irqsteer.c

275

CHANMASK(i, data->reg_num));

drivers/irqchip/irq-imx-irqsteer.c

283

for (i = 0; i < data->reg_num; i++)

drivers/irqchip/irq-imx-irqsteer.c

285

data->regs + CHANMASK(i, data->reg_num));

drivers/irqchip/irq-imx-irqsteer.c

35

int reg_num;

drivers/irqchip/irq-imx-irqsteer.c

45

return (data->reg_num - irqnum / 32 - 1);

drivers/irqchip/irq-imx-irqsteer.c

56

val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num));

drivers/irqchip/irq-imx-irqsteer.c

58

writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num));

drivers/irqchip/irq-imx-irqsteer.c

70

val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num));

drivers/irqchip/irq-imx-irqsteer.c

72

writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num));

drivers/media/i2c/ov2640.c

282

u8 reg_num;

drivers/media/i2c/ov2640.c

655

while ((vals->reg_num != 0xff) || (vals->value != 0xff)) {

drivers/media/i2c/ov2640.c

657

vals->reg_num, vals->value);

drivers/media/i2c/ov2640.c

659

vals->reg_num, vals->value);

drivers/media/i2c/ov7670.c

272

unsigned char reg_num;

drivers/media/i2c/ov7670.c

593

while (vals->reg_num != 0xff || vals->value != 0xff) {

drivers/media/i2c/ov7670.c

594

int ret = ov7670_write(sd, vals->reg_num, vals->value);

drivers/media/i2c/ov7740.c

130

u32 reg_num;

drivers/media/i2c/ov7740.c

137

u32 reg_num;

drivers/media/i2c/ov7740.c

262

.reg_num = ARRAY_SIZE(ov7740_vga),

drivers/media/i2c/ov7740.c

595

ov7740->fmt->reg_num);

drivers/media/i2c/ov7740.c

603

ov7740->frmsize->reg_num);

drivers/media/i2c/ov7740.c

663

.reg_num = ARRAY_SIZE(ov7740_format_yuyv),

drivers/media/i2c/ov7740.c

669

.reg_num = ARRAY_SIZE(ov7740_format_bggr8),

drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c

125

reg_num = of_property_count_elems_of_size(pdev->dev.of_node, "reg",

drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c

127

if (reg_num <= 0 || reg_num > num_max_vdec_regs) {

drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c

128

dev_err(&pdev->dev, "Invalid register property size: %d\n", reg_num);

drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c

133

for (i = 0; i < reg_num; i++) {

drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c

141

for (i = 0; i < reg_num; i++) {

drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c

91

int reg_num, i;

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

131

int reg_num;

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

158

reg_num = 0;

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

166

vdpu_write_relaxed(vpu, reg, G1_REG_BD_REF_PIC(reg_num++));

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

186

reg_num = 0;

drivers/media/platform/verisilicon/hantro_g1_h264_dec.c

194

vdpu_write_relaxed(vpu, reg, G1_REG_FWD_PIC(reg_num++));

drivers/mfd/ezx-pcap.c

104

int ezx_pcap_set_bits(struct pcap_chip *pcap, u8 reg_num, u32 mask, u32 val)

drivers/mfd/ezx-pcap.c

109

(reg_num << PCAP_REGISTER_ADDRESS_SHIFT);

drivers/mfd/ezx-pcap.c

118

(reg_num << PCAP_REGISTER_ADDRESS_SHIFT);

drivers/mfd/ezx-pcap.c

72

int ezx_pcap_write(struct pcap_chip *pcap, u8 reg_num, u32 value)

drivers/mfd/ezx-pcap.c

80

| (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);

drivers/mfd/ezx-pcap.c

88

int ezx_pcap_read(struct pcap_chip *pcap, u8 reg_num, u32 *value)

drivers/mfd/ezx-pcap.c

95

| (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);

drivers/net/bonding/bond_main.c

4557

if (mii->reg_num == 1) {

drivers/net/ethernet/3com/3c574_cs.c

1043

data->phy_id, data->reg_num, data->val_in, data->val_out);

drivers/net/ethernet/3com/3c574_cs.c

1058

data->reg_num & 0x1f);

drivers/net/ethernet/3com/3c574_cs.c

1072

data->reg_num & 0x1f, data->val_in);

drivers/net/ethernet/8390/axnet_cs.c

618

data->val_out = mdio_read(mii_addr, data->phy_id, data->reg_num & 0x1f);

drivers/net/ethernet/8390/axnet_cs.c

621

mdio_write(mii_addr, data->phy_id, data->reg_num & 0x1f, data->val_in);

drivers/net/ethernet/8390/pcnet_cs.c

1122

data->val_out = mdio_read(mii_addr, data->phy_id, data->reg_num & 0x1f);

drivers/net/ethernet/8390/pcnet_cs.c

1125

mdio_write(mii_addr, data->phy_id, data->reg_num & 0x1f, data->val_in);

drivers/net/ethernet/amd/amd8111e.c

1475

data->reg_num & PHY_REG_ADDR_MASK, &mii_regval);

drivers/net/ethernet/amd/amd8111e.c

1485

data->reg_num & PHY_REG_ADDR_MASK, data->val_in);

drivers/net/ethernet/amd/amd8111e.c

157

static int amd8111e_mdio_read(struct net_device *dev, int phy_id, int reg_num)

drivers/net/ethernet/amd/amd8111e.c

162

amd8111e_read_phy(lp, phy_id, reg_num, &reg_val);

drivers/net/ethernet/amd/amd8111e.c

169

int phy_id, int reg_num, int val)

drivers/net/ethernet/amd/amd8111e.c

173

amd8111e_write_phy(lp, phy_id, reg_num, val);

drivers/net/ethernet/amd/pcnet32.c

2752

static int mdio_read(struct net_device *dev, int phy_id, int reg_num)

drivers/net/ethernet/amd/pcnet32.c

2761

lp->a->write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));

drivers/net/ethernet/amd/pcnet32.c

2768

static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)

drivers/net/ethernet/amd/pcnet32.c

2776

lp->a->write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));

drivers/net/ethernet/amd/pcnet32.c

321

static int mdio_read(struct net_device *dev, int phy_id, int reg_num);

drivers/net/ethernet/amd/pcnet32.c

322

static void mdio_write(struct net_device *dev, int phy_id, int reg_num,

drivers/net/ethernet/arc/emac_mdio.c

56

static int arc_mdio_read(struct mii_bus *bus, int phy_addr, int reg_num)

drivers/net/ethernet/arc/emac_mdio.c

63

0x60020000 | (phy_addr << 23) | (reg_num << 18));

drivers/net/ethernet/arc/emac_mdio.c

72

phy_addr, reg_num, value);

drivers/net/ethernet/arc/emac_mdio.c

89

int reg_num, u16 value)

drivers/net/ethernet/arc/emac_mdio.c

95

phy_addr, reg_num, value);

drivers/net/ethernet/arc/emac_mdio.c

98

0x50020000 | (phy_addr << 23) | (reg_num << 18) | value);

drivers/net/ethernet/atheros/atl1c/atl1c_main.c

578

static int atl1c_mdio_read(struct net_device *netdev, int phy_id, int reg_num)

drivers/net/ethernet/atheros/atl1c/atl1c_main.c

583

atl1c_read_phy_reg(&adapter->hw, reg_num, &result);

drivers/net/ethernet/atheros/atl1c/atl1c_main.c

588

int reg_num, int val)

drivers/net/ethernet/atheros/atl1c/atl1c_main.c

592

atl1c_write_phy_reg(&adapter->hw, reg_num, val);

drivers/net/ethernet/atheros/atl1c/atl1c_main.c

614

if (atl1c_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,

drivers/net/ethernet/atheros/atl1c/atl1c_main.c

622

if (data->reg_num & ~(0x1F)) {

drivers/net/ethernet/atheros/atl1c/atl1c_main.c

628

data->reg_num, data->val_in);

drivers/net/ethernet/atheros/atl1c/atl1c_main.c

630

data->reg_num, data->val_in)) {

drivers/net/ethernet/atheros/atl1e/atl1e_main.c

444

static int atl1e_mdio_read(struct net_device *netdev, int phy_id, int reg_num)

drivers/net/ethernet/atheros/atl1e/atl1e_main.c

449

atl1e_read_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, &result);

drivers/net/ethernet/atheros/atl1e/atl1e_main.c

454

int reg_num, int val)

drivers/net/ethernet/atheros/atl1e/atl1e_main.c

459

reg_num & MDIO_REG_ADDR_MASK, val))

drivers/net/ethernet/atheros/atl1e/atl1e_main.c

481

if (atl1e_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,

drivers/net/ethernet/atheros/atl1e/atl1e_main.c

489

if (data->reg_num & ~(0x1F)) {

drivers/net/ethernet/atheros/atl1e/atl1e_main.c

495

data->reg_num, data->val_in);

drivers/net/ethernet/atheros/atl1e/atl1e_main.c

497

data->reg_num, data->val_in)) {

drivers/net/ethernet/atheros/atlx/atl1.c

979

static int mdio_read(struct net_device *netdev, int phy_id, int reg_num)

drivers/net/ethernet/atheros/atlx/atl1.c

984

atl1_read_phy_reg(&adapter->hw, reg_num & 0x1f, &result);

drivers/net/ethernet/atheros/atlx/atl1.c

989

static void mdio_write(struct net_device *netdev, int phy_id, int reg_num,

drivers/net/ethernet/atheros/atlx/atl1.c

994

atl1_write_phy_reg(&adapter->hw, reg_num, val);

drivers/net/ethernet/atheros/atlx/atl2.c

955

data->reg_num & 0x1F, &data->val_out)) {

drivers/net/ethernet/atheros/atlx/atl2.c

962

if (data->reg_num & ~(0x1F))

drivers/net/ethernet/atheros/atlx/atl2.c

965

if (atl2_write_phy_reg(&adapter->hw, data->reg_num,

drivers/net/ethernet/broadcom/bnx2.c

7863

err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);

drivers/net/ethernet/broadcom/bnx2.c

7879

err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);

drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

12819

mdio->phy_id, mdio->reg_num, mdio->val_in);

drivers/net/ethernet/broadcom/bnxt/bnxt.c

13386

rc = bnxt_hwrm_port_phy_read(bp, mdio->phy_id, mdio->reg_num,

drivers/net/ethernet/broadcom/bnxt/bnxt.c

13396

return bnxt_hwrm_port_phy_write(bp, mdio->phy_id, mdio->reg_num,

drivers/net/ethernet/broadcom/tg3.c

14087

data->reg_num & 0x1f, &mii_regval);

drivers/net/ethernet/broadcom/tg3.c

14104

data->reg_num & 0x1f, data->val_in);

drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c

3142

data->reg_num &= 0x1f;

drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c

3149

data->reg_num, &data->val_out);

drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c

3152

data->reg_num, data->val_in);

drivers/net/ethernet/dec/tulip/tulip_core.c

904

unsigned int regnum = data->reg_num;

drivers/net/ethernet/dec/tulip/winbond-840.c

1450

data->val_out = mdio_read(dev, data->phy_id & 0x1f, data->reg_num & 0x1f);

drivers/net/ethernet/dec/tulip/winbond-840.c

1456

mdio_write(dev, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);

drivers/net/ethernet/dlink/dl2k.c

1376

miidata->val_out = mii_read (dev, phy_addr, miidata->reg_num);

drivers/net/ethernet/dlink/dl2k.c

1381

mii_write (dev, phy_addr, miidata->reg_num, miidata->val_in);

drivers/net/ethernet/dlink/dl2k.c

1451

mii_read (struct net_device *dev, int phy_addr, int reg_num)

drivers/net/ethernet/dlink/dl2k.c

1461

cmd = (0x06 << 10 | phy_addr << 5 | reg_num);

drivers/net/ethernet/dlink/dl2k.c

1479

mii_write (struct net_device *dev, int phy_addr, int reg_num, u16 data)

drivers/net/ethernet/dlink/dl2k.c

1487

cmd = (0x5002 << 16) | (phy_addr << 23) | (reg_num << 18) | data;

drivers/net/ethernet/dlink/dl2k.c

84

static int mii_read (struct net_device *dev, int phy_addr, int reg_num);

drivers/net/ethernet/dlink/dl2k.c

85

static int mii_write (struct net_device *dev, int phy_addr, int reg_num,

drivers/net/ethernet/hisilicon/hns/hns_enet.c

1990

u32 *data, reg_num, i;

drivers/net/ethernet/hisilicon/hns/hns_enet.c

1993

reg_num = ops->get_regs_len(priv->ae_handle);

drivers/net/ethernet/hisilicon/hns/hns_enet.c

1994

reg_num = (reg_num + 3ul) & ~3ul;

drivers/net/ethernet/hisilicon/hns/hns_enet.c

1995

data = kcalloc(reg_num, sizeof(u32), GFP_KERNEL);

drivers/net/ethernet/hisilicon/hns/hns_enet.c

1998

for (i = 0; i < reg_num; i += 4)

drivers/net/ethernet/hisilicon/hns/hns_ethtool.c

1116

u32 reg_num;

drivers/net/ethernet/hisilicon/hns/hns_ethtool.c

1126

reg_num = ops->get_regs_len(priv->ae_handle);

drivers/net/ethernet/hisilicon/hns/hns_ethtool.c

1127

if (reg_num > 0)

drivers/net/ethernet/hisilicon/hns/hns_ethtool.c

1128

return reg_num * sizeof(u32);

drivers/net/ethernet/hisilicon/hns/hns_ethtool.c

1130

return reg_num; /* error code */

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

3232

for (i = 0; i < type_reg_info->reg_num; i++)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

3282

offset += type_reg_info->reg_num;

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h

230

u8 reg_num;

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

1428

u32 reg_num = 0;

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

1431

ret = hclge_mac_query_reg_num(hdev, &reg_num);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

1435

hdev->ae_dev->dev_specs.mac_stats_num = reg_num;

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

480

u32 reg_num = hdev->ae_dev->dev_specs.mac_stats_num;

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

490

desc_num = reg_num / HCLGE_REG_NUM_PER_DESC + 1;

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

506

data_size = min_t(u32, sizeof(hdev->mac_stats) / sizeof(u64), reg_num);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

523

static int hclge_mac_query_reg_num(struct hclge_dev *hdev, u32 *reg_num)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

534

*reg_num = HCLGE_MAC_STATS_MAX_NUM_V1;

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

547

*reg_num = le32_to_cpu(desc.data[0]);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

548

if (*reg_num == 0) {

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

9437

return hclge_read_phy_reg(hdev, data->reg_num, &data->val_out);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

9440

return hclge_write_phy_reg(hdev, data->reg_num, data->val_in);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_regs.c

373

int entries_per_desc, reg_num, desc_index, index, i;

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_regs.c

378

reg_num = entries_per_desc * bd_num;

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_regs.c

379

for (i = 0; i < reg_num; i++) {

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_regs.c

385

return reg_num;

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_regs.c

516

int i, j, reg_num;

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_regs.c

521

reg_num = ARRAY_SIZE(cmdq_reg_addr_list);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_regs.c

522

reg += hclge_reg_get_tlv(HCLGE_REG_TAG_CMDQ, reg_num, reg);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_regs.c

523

for (i = 0; i < reg_num; i++)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_regs.c

525

data_num_sum = reg_num + HCLGE_REG_TLV_SPACE;

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_regs.c

527

reg_num = ARRAY_SIZE(common_reg_addr_list);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_regs.c

528

reg += hclge_reg_get_tlv(HCLGE_REG_TAG_COMMON, reg_num, reg);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_regs.c

529

for (i = 0; i < reg_num; i++)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_regs.c

531

data_num_sum += reg_num + HCLGE_REG_TLV_SPACE;

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_regs.c

533

reg_num = ARRAY_SIZE(ring_reg_addr_list);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_regs.c

535

reg += hclge_reg_get_tlv(HCLGE_REG_TAG_RING, reg_num, reg);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_regs.c

537

for (i = 0; i < reg_num; i++)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_regs.c

542

data_num_sum += (reg_num + HCLGE_REG_TLV_SPACE) * kinfo->num_tqps;

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_regs.c

544

reg_num = ARRAY_SIZE(tqp_intr_reg_addr_list);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_regs.c

546

reg += hclge_reg_get_tlv(HCLGE_REG_TAG_TQP_INTR, reg_num, reg);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_regs.c

547

for (i = 0; i < reg_num; i++)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_regs.c

552

data_num_sum += (reg_num + HCLGE_REG_TLV_SPACE) *

drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_regs.c

130

int i, j, reg_num;

drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_regs.c

137

reg_num = ARRAY_SIZE(cmdq_reg_addr_list);

drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_regs.c

138

reg += hclgevf_reg_get_tlv(HCLGEVF_REG_TAG_CMDQ, reg_num, reg);

drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_regs.c

139

for (i = 0; i < reg_num; i++)

drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_regs.c

142

reg_num = ARRAY_SIZE(common_reg_addr_list);

drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_regs.c

143

reg += hclgevf_reg_get_tlv(HCLGEVF_REG_TAG_COMMON, reg_num, reg);

drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_regs.c

144

for (i = 0; i < reg_num; i++)

drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_regs.c

147

reg_num = ARRAY_SIZE(ring_reg_addr_list);

drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_regs.c

149

reg += hclgevf_reg_get_tlv(HCLGEVF_REG_TAG_RING, reg_num, reg);

drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_regs.c

151

for (i = 0; i < reg_num; i++)

drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_regs.c

157

reg_num = ARRAY_SIZE(tqp_intr_reg_addr_list);

drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_regs.c

160

reg_num, reg);

drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_regs.c

161

for (i = 0; i < reg_num; i++)

drivers/net/ethernet/ibm/emac/core.c

2309

data->reg_num);

drivers/net/ethernet/ibm/emac/core.c

2313

emac_mdio_write(ndev, dev->phy.address, data->reg_num,

drivers/net/ethernet/intel/e1000/e1000_main.c

4780

if (e1000_read_phy_reg(hw, data->reg_num & 0x1F,

drivers/net/ethernet/intel/e1000/e1000_main.c

4788

if (data->reg_num & ~(0x1F))

drivers/net/ethernet/intel/e1000/e1000_main.c

4792

if (e1000_write_phy_reg(hw, data->reg_num,

drivers/net/ethernet/intel/e1000/e1000_main.c

4799

switch (data->reg_num) {

drivers/net/ethernet/intel/e1000/e1000_main.c

4834

switch (data->reg_num) {

drivers/net/ethernet/intel/e1000e/netdev.c

6117

switch (data->reg_num & 0x1F) {

drivers/net/ethernet/intel/igb/igb_main.c

9289

if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,

drivers/net/ethernet/intel/igb/igb_main.c

9294

if (igb_write_phy_reg(&adapter->hw, data->reg_num & 0x1F,

drivers/net/ethernet/marvell/skge.c

2462

err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);

drivers/net/ethernet/marvell/skge.c

2464

err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);

drivers/net/ethernet/marvell/skge.c

2473

err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,

drivers/net/ethernet/marvell/skge.c

2476

err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,

drivers/net/ethernet/marvell/sky2.c

1385

err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);

drivers/net/ethernet/marvell/sky2.c

1394

err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,

drivers/net/ethernet/micrel/ksz884x.c

5465

if (data->phy_id != priv->id || data->reg_num >= 6)

drivers/net/ethernet/micrel/ksz884x.c

5468

hw_r_phy(hw, port->linked->port_id, data->reg_num,

drivers/net/ethernet/micrel/ksz884x.c

5476

else if (data->phy_id != priv->id || data->reg_num >= 6)

drivers/net/ethernet/micrel/ksz884x.c

5479

hw_w_phy(hw, port->linked->port_id, data->reg_num,

drivers/net/ethernet/micrel/ksz884x.c

5506

static int mdio_read(struct net_device *dev, int phy_id, int reg_num)

drivers/net/ethernet/micrel/ksz884x.c

5513

hw_r_phy(hw, port->linked->port_id, reg_num << 1, &val_out);

drivers/net/ethernet/micrel/ksz884x.c

5526

static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)

drivers/net/ethernet/micrel/ksz884x.c

5535

hw_w_phy(hw, pi, reg_num << 1, val);

drivers/net/ethernet/natsemi/natsemi.c

3090

data->reg_num & 0x1f);

drivers/net/ethernet/natsemi/natsemi.c

3096

data->reg_num & 0x1f);

drivers/net/ethernet/natsemi/natsemi.c

3103

if ((data->reg_num & 0x1f) == MII_ADVERTISE)

drivers/net/ethernet/natsemi/natsemi.c

3105

mdio_write(dev, data->reg_num & 0x1f,

drivers/net/ethernet/natsemi/natsemi.c

3110

if ((data->reg_num & 0x1f) == MII_ADVERTISE)

drivers/net/ethernet/natsemi/natsemi.c

3115

data->reg_num & 0x1f,

drivers/net/ethernet/packetengines/yellowfin.c

1364

data->val_out = mdio_read(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f);

drivers/net/ethernet/packetengines/yellowfin.c

1370

switch (data->reg_num) {

drivers/net/ethernet/packetengines/yellowfin.c

1381

mdio_write(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);

drivers/net/ethernet/sis/sis900.c

2228

data->val_out = mdio_read(net_dev, data->phy_id & 0x1f, data->reg_num & 0x1f);

drivers/net/ethernet/sis/sis900.c

2232

mdio_write(net_dev, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);

drivers/net/ethernet/sun/cassini.c

4733

data->val_out = cas_phy_read(cp, data->reg_num & 0x1f);

drivers/net/ethernet/sun/cassini.c

4742

rc = cas_phy_write(cp, data->reg_num & 0x1f, data->val_in);

drivers/net/ethernet/sun/sungem.c

2708

data->reg_num & 0x1f);

drivers/net/ethernet/sun/sungem.c

2713

__sungem_phy_write(gp, data->phy_id & 0x1f, data->reg_num & 0x1f,

drivers/net/ethernet/ti/tlan.c

953

data->reg_num & 0x1f, &data->val_out);

drivers/net/ethernet/ti/tlan.c

959

data->reg_num & 0x1f, data->val_in);

drivers/net/ethernet/via/via-velocity.c

2402

if (velocity_mii_read(vptr->mac_regs, miidata->reg_num & 0x1f, &(miidata->val_out)) < 0)

drivers/net/ethernet/via/via-velocity.c

2407

err = velocity_mii_write(vptr->mac_regs, miidata->reg_num & 0x1f, miidata->val_in);

drivers/net/ethernet/xircom/xirc2ps_cs.c

1426

data->phy_id, data->reg_num, data->val_in, data->val_out);

drivers/net/ethernet/xircom/xirc2ps_cs.c

1437

data->reg_num & 0x1f);

drivers/net/ethernet/xircom/xirc2ps_cs.c

1440

mii_wr(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in,

drivers/net/mdio.c

359

u16 addr = mii_data->reg_num;

drivers/net/mii.c

596

mii_data->reg_num &= mii_if->reg_num_mask;

drivers/net/mii.c

606

mii_data->reg_num);

drivers/net/mii.c

613

switch(mii_data->reg_num) {

drivers/net/mii.c

639

mii_data->reg_num, val);

drivers/net/phy/fixed_phy.c

61

static int fixed_mdio_read(struct mii_bus *bus, int phy_addr, int reg_num)

drivers/net/phy/fixed_phy.c

72

return swphy_read_reg(reg_num, &fp->status);

drivers/net/phy/fixed_phy.c

75

static int fixed_mdio_write(struct mii_bus *bus, int phy_addr, int reg_num,

drivers/net/phy/phy.c

331

mii_data->reg_num);

drivers/net/phy/phy.c

335

mii_data->reg_num);

drivers/net/phy/phy.c

351

devad = mii_data->reg_num;

drivers/net/phy/phy.c

393

mii_data->reg_num, val);

drivers/net/phy/phylink.c

3538

ret = phylink_phy_read(pl, mii->phy_id, mii->reg_num);

drivers/net/phy/phylink.c

3546

ret = phylink_phy_write(pl, mii->phy_id, mii->reg_num,

drivers/net/phy/phylink.c

3561

ret = phylink_mii_read(pl, mii->phy_id, mii->reg_num);

drivers/net/phy/phylink.c

3569

ret = phylink_mii_write(pl, mii->phy_id, mii->reg_num,

drivers/net/usb/r8152.c

9333

data->val_out = r8152_mdio_read(tp, data->reg_num);

drivers/net/usb/r8152.c

9343

r8152_mdio_write(tp, data->reg_num, data->val_in);

drivers/net/wireless/realtek/rtw88/rtw8822c.c

1192

u32 reg_backup[], u32 reg_num)

drivers/net/wireless/realtek/rtw88/rtw8822c.c

1196

for (i = 0; i < reg_num; i++) {

drivers/net/wireless/realtek/rtw88/rtw8822c.c

1206

u32 reg_num)

drivers/net/wireless/realtek/rtw88/rtw8822c.c

1210

for (i = 0; i < reg_num; i++) {

drivers/net/wireless/realtek/rtw88/rtw8822c.c

3188

rtw8822c_dpk_restore_registers(struct rtw_dev *rtwdev, u32 reg_num,

drivers/net/wireless/realtek/rtw88/rtw8822c.c

3191

rtw_restore_reg(rtwdev, bckp, reg_num);

drivers/net/wireless/realtek/rtw88/rtw8822c.c

3198

u32 reg_num, struct rtw_backup_info *bckp)

drivers/net/wireless/realtek/rtw88/rtw8822c.c

3202

for (i = 0; i < reg_num; i++) {

drivers/net/wireless/realtek/rtw89/coex.c

1042

idx = _search_reg_index(rtwdev, pmreg->v1.reg_num,

drivers/net/wireless/realtek/rtw89/coex.c

1051

idx = _search_reg_index(rtwdev, pmreg->v2.reg_num,

drivers/net/wireless/realtek/rtw89/coex.c

1072

idx = _search_reg_index(rtwdev, pmreg->v1.reg_num,

drivers/net/wireless/realtek/rtw89/coex.c

1082

idx = _search_reg_index(rtwdev, pmreg->v2.reg_num,

drivers/net/wireless/realtek/rtw89/coex.c

10907

__func__, pmreg->reg_num);

drivers/net/wireless/realtek/rtw89/coex.c

10909

for (i = 0; i < pmreg->reg_num; i++) {

drivers/net/wireless/realtek/rtw89/coex.c

10926

if (i >= pmreg->reg_num)

drivers/net/wireless/realtek/rtw89/coex.c

10993

__func__, pmreg->reg_num);

drivers/net/wireless/realtek/rtw89/coex.c

10995

for (i = 0; i < pmreg->reg_num; i++) {

drivers/net/wireless/realtek/rtw89/coex.c

11012

if (i >= pmreg->reg_num)

drivers/net/wireless/realtek/rtw89/coex.c

11078

for (i = 0; i < pmreg->reg_num; i++) {

drivers/net/wireless/realtek/rtw89/coex.c

2691

v1->reg_num = n;

drivers/net/wireless/realtek/rtw89/coex.c

395

u8 reg_num;

drivers/net/wireless/realtek/rtw89/coex.c

396

struct rtw89_btc_fbtc_mreg regs[] __counted_by(reg_num);

drivers/net/wireless/realtek/rtw89/core.h

2543

u8 reg_num;

drivers/net/wireless/realtek/rtw89/core.h

2550

u8 reg_num;

drivers/net/wireless/realtek/rtw89/core.h

2557

u8 reg_num;

drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.c

3437

u32 reg_backup[], u32 reg_num)

drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.c

3441

for (i = 0; i < reg_num; i++) {

drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.c

3452

u32 reg_backup[], u32 reg_num)

drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.c

3457

for (i = 0; i < reg_num; i++) {

drivers/net/wireless/realtek/rtw89/rtw8852bt_rfk.c

3507

u32 reg_backup[], u32 reg_num)

drivers/net/wireless/realtek/rtw89/rtw8852bt_rfk.c

3511

for (i = 0; i < reg_num; i++) {

drivers/net/wireless/realtek/rtw89/rtw8852bt_rfk.c

3522

u32 reg_backup[], u32 reg_num)

drivers/net/wireless/realtek/rtw89/rtw8852bt_rfk.c

3527

for (i = 0; i < reg_num; i++) {

drivers/pci/of_property.c

55

u32 reg_num, u32 flags, bool reloc)

drivers/pci/of_property.c

64

prop[0] |= flags | reg_num;

drivers/pinctrl/intel/pinctrl-intel-platform.c

136

gpp->reg_num = group;

drivers/pinctrl/intel/pinctrl-intel.c

1134

gpp = padgrp->reg_num;

drivers/pinctrl/intel/pinctrl-intel.c

1158

gpp = padgrp->reg_num;

drivers/pinctrl/intel/pinctrl-intel.c

1294

gpp = padgrp->reg_num;

drivers/pinctrl/intel/pinctrl-intel.c

1490

gpps[i].reg_num = i;

drivers/pinctrl/intel/pinctrl-intel.c

241

offset = community->hostown_offset + padgrp->reg_num * 4;

drivers/pinctrl/intel/pinctrl-intel.c

290

offset = community->padcfglock_offset + 0 + padgrp->reg_num * 8;

drivers/pinctrl/intel/pinctrl-intel.c

295

offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8;

drivers/pinctrl/intel/pinctrl-intel.h

59

unsigned int reg_num;

drivers/pinctrl/intel/pinctrl-intel.h

82

.reg_num = (r), \

drivers/power/supply/max1721x_battery.c

342

"max1721x-%012X", (unsigned int)sl->reg_num.id);

drivers/s390/net/qeth_core_main.c

6566

mii_data->phy_id, mii_data->reg_num);

drivers/scsi/wd33c93.c

166

read_wd33c93(const wd33c93_regs regs, uchar reg_num)

drivers/scsi/wd33c93.c

168

*regs.SASR = reg_num;

drivers/scsi/wd33c93.c

194

write_wd33c93(const wd33c93_regs regs, uchar reg_num, uchar value)

drivers/scsi/wd33c93.c

196

*regs.SASR = reg_num;

drivers/soc/fsl/qe/ucc.c

101

unsigned int reg_num;

drivers/soc/fsl/qe/ucc.c

108

get_cmxucr_reg(ucc_num, &cmxucr, &reg_num, &shift);

drivers/soc/fsl/qe/ucc.c

123

unsigned int reg_num;

drivers/soc/fsl/qe/ucc.c

135

get_cmxucr_reg(ucc_num, &cmxucr, &reg_num, &shift);

drivers/soc/fsl/qe/ucc.c

137

switch (reg_num) {

drivers/soc/fsl/qe/ucc.c

89

unsigned int *reg_num, unsigned int *shift)

drivers/soc/fsl/qe/ucc.c

93

*reg_num = cmx + 1;

drivers/staging/media/atomisp/i2c/gc2235.h

106

u16 reg_num;

drivers/staging/media/atomisp/i2c/ov2722.h

154

u16 reg_num;

drivers/staging/media/meson/vdec/vdec_helpers.c

180

u32 reg_base[], u32 reg_num[])

drivers/staging/media/meson/vdec/vdec_helpers.c

218

if (reg_num_cur >= reg_num[reg_base_cur]) {

drivers/staging/media/meson/vdec/vdec_helpers.h

20

u32 reg_base[], u32 reg_num[]);

drivers/video/fbdev/via/hw.c

1022

iga1_fetch_count_reg.reg_num;

drivers/video/fbdev/via/hw.c

1029

iga2_fetch_count_reg.reg_num;

drivers/video/fbdev/via/hw.c

1161

display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg_num;

drivers/video/fbdev/via/hw.c

1169

iga1_fifo_threshold_select_reg.reg_num;

drivers/video/fbdev/via/hw.c

1180

iga1_fifo_high_threshold_select_reg.reg_num;

drivers/video/fbdev/via/hw.c

1192

iga1_display_queue_expire_num_reg.reg_num;

drivers/video/fbdev/via/hw.c

1315

iga2_fifo_depth_select_reg.reg_num;

drivers/video/fbdev/via/hw.c

1328

iga2_fifo_depth_select_reg.reg_num;

drivers/video/fbdev/via/hw.c

1340

iga2_fifo_threshold_select_reg.reg_num;

drivers/video/fbdev/via/hw.c

1351

iga2_fifo_high_threshold_select_reg.reg_num;

drivers/video/fbdev/via/hw.c

1363

iga2_display_queue_expire_num_reg.reg_num;

drivers/video/fbdev/via/hw.h

355

int reg_num;

drivers/video/fbdev/via/hw.h

361

int reg_num;

drivers/video/fbdev/via/hw.h

367

int reg_num;

drivers/video/fbdev/via/hw.h

373

int reg_num;

drivers/video/fbdev/via/hw.h

379

int reg_num;

drivers/video/fbdev/via/hw.h

385

int reg_num;

drivers/video/fbdev/via/hw.h

391

int reg_num;

drivers/video/fbdev/via/hw.h

397

int reg_num;

drivers/video/fbdev/via/hw.h

403

int reg_num;

drivers/video/fbdev/via/hw.h

409

int reg_num;

drivers/video/fbdev/via/hw.h

420

int reg_num;

drivers/video/fbdev/via/hw.h

425

int reg_num;

drivers/video/fbdev/via/hw.h

436

int reg_num;

drivers/video/fbdev/via/hw.h

441

int reg_num;

drivers/video/fbdev/via/hw.h

446

int reg_num;

drivers/video/fbdev/via/hw.h

451

int reg_num;

drivers/video/fbdev/via/hw.h

464

int reg_num;

drivers/video/fbdev/via/hw.h

469

int reg_num;

drivers/video/fbdev/via/hw.h

500

int reg_num;

drivers/video/fbdev/via/hw.h

505

int reg_num;

drivers/video/fbdev/via/hw.h

510

int reg_num;

drivers/video/fbdev/via/hw.h

515

int reg_num;

drivers/video/fbdev/via/hw.h

520

int reg_num;

drivers/video/fbdev/via/hw.h

525

int reg_num;

drivers/video/fbdev/via/hw.h

530

int reg_num;

drivers/video/fbdev/via/hw.h

535

int reg_num;

drivers/video/fbdev/via/lcd.c

357

reg_num;

drivers/video/fbdev/via/lcd.c

378

lcd_scaling_factor.lcd_hor_scaling_factor.reg_num;

drivers/video/fbdev/via/lcd.c

401

reg_num;

drivers/video/fbdev/via/lcd.c

422

lcd_scaling_factor.lcd_ver_scaling_factor.reg_num;

drivers/video/fbdev/via/vt1636.c

69

int reg_num, i;

drivers/video/fbdev/via/vt1636.c

72

reg_num = ARRAY_SIZE(common_init_data);

drivers/video/fbdev/via/vt1636.c

73

for (i = 0; i < reg_num; i++)

drivers/w1/slaves/w1_ds2405.c

182

u64 dev_addr = le64_to_cpu(*(u64 *)&sl->reg_num);

drivers/w1/slaves/w1_ds2405.c

30

u64 dev_addr = le64_to_cpu(*(u64 *)&sl->reg_num);

drivers/w1/slaves/w1_ds2408.c

295

u64 rn = le64_to_cpu(*((u64 *)&sl->reg_num));

drivers/w1/slaves/w1_ds250x.c

204

sl->master->bus_master->dev_id, sl->reg_num.family,

drivers/w1/slaves/w1_ds250x.c

205

(unsigned long long)sl->reg_num.id);

drivers/w1/slaves/w1_ds250x.c

209

sl->reg_num.family,

drivers/w1/slaves/w1_ds250x.c

210

(unsigned long long)sl->reg_num.id);

drivers/w1/slaves/w1_therm.c

1063

u64 rn = le64_to_cpu(*((u64 *)&sl->reg_num));

drivers/w1/slaves/w1_therm.c

2091

struct w1_reg_num *reg_num;

drivers/w1/slaves/w1_therm.c

2116

reg_num = (struct w1_reg_num *) &rn;

drivers/w1/slaves/w1_therm.c

2117

if (reg_num->family == W1_42_FINISHED_BYTE)

drivers/w1/slaves/w1_therm.c

2119

if (sl->reg_num.id == reg_num->id)

drivers/w1/w1.c

438

if (sl->reg_num.family == rn->family &&

drivers/w1/w1.c

439

sl->reg_num.id == rn->id &&

drivers/w1/w1.c

440

sl->reg_num.crc == rn->crc) {

drivers/w1/w1.c

596

err = add_uevent_var(env, "W1_FID=%02X", sl->reg_num.family);

drivers/w1/w1.c

601

(unsigned long long)sl->reg_num.id);

drivers/w1/w1.c

677

(unsigned int) sl->reg_num.family,

drivers/w1/w1.c

678

(unsigned long long) sl->reg_num.id);

drivers/w1/w1.c

681

(unsigned int) sl->reg_num.family,

drivers/w1/w1.c

682

(unsigned long long) sl->reg_num.id);

drivers/w1/w1.c

732

memcpy(&sl->reg_num, rn, sizeof(sl->reg_num));

drivers/w1/w1.c

790

memcpy(msg.id.id, &sl->reg_num, sizeof(msg.id));

drivers/w1/w1.c

846

if (iter->reg_num.family == id->family &&

drivers/w1/w1.c

847

iter->reg_num.id == id->id &&

drivers/w1/w1.c

848

iter->reg_num.crc == id->crc) {

drivers/w1/w1.c

883

&& sl->reg_num.family == f->fid) ||

drivers/w1/w1.c

888

memcpy(&rn, &sl->reg_num, sizeof(rn));

drivers/w1/w1.c

97

ssize_t count = sizeof(sl->reg_num);

drivers/w1/w1.c

99

memcpy(buf, (u8 *)&sl->reg_num, count);

drivers/w1/w1_io.c

396

u64 rn = le64_to_cpu(*((u64*)&sl->reg_num));

drivers/w1/w1_netlink.c

276

memcpy(&rn, &sl->reg_num, sizeof(rn));

drivers/w1/w1_netlink.c

391

__func__, sl->reg_num.family, (unsigned long long)sl->reg_num.id,

drivers/w1/w1_netlink.c

392

sl->reg_num.crc, cmd->cmd, cmd->len);

include/linux/mlx5/driver.h

1067

u16 reg_num, int arg, int write);

include/linux/w1.h

69

struct w1_reg_num reg_num;

include/uapi/linux/mii.h

180

__u16 reg_num;

sound/soc/codecs/aw88395/aw88395_lib.c

114

bin->header_info[bin_num].reg_num = parse_dsp_reg_num;

sound/soc/codecs/aw88395/aw88395_lib.c

141

bin->header_info[bin_num].reg_num = parse_soc_app_num;

sound/soc/codecs/aw88395/aw88395_lib.c

84

bin->header_info[bin_num].reg_num = parse_register_num;

sound/soc/codecs/aw88395/aw88395_lib.h

71

unsigned int reg_num;

tools/lib/bpf/usdt.c

1420

int reg_num;

tools/lib/bpf/usdt.c

1422

if (sscanf(reg_name, "x%d", &reg_num) == 1) {

tools/lib/bpf/usdt.c

1423

if (reg_num >= 0 && reg_num < 31)

tools/lib/bpf/usdt.c

1424

return offsetof(struct user_pt_regs, regs[reg_num]);