reg_mode
kw_write_reg(reg_mode, mode_reg | (bus->channel << 4));
bool reg_mode = false;
reg_mode = true;
if (reg_mode)
if (reg_mode)
u8 reg_mode;
reg_mode = NPCM7XX_FAN_TCKC_CLK1_APB
iowrite8(reg_mode, NPCM7XX_FAN_REG_TCKC(data->fan_base,
reg_mode =
iowrite8(reg_mode,
u8 reg_mode;
reg_mode = ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));
iowrite8((reg_mode & ~flag_mode),
u8 reg_mode;
reg_mode = ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));
iowrite8((reg_mode & ~flag_mode),
.reg_mode.mode = __cpu_to_le32(mode),
.reg_mode.inband = inband,
.reg_mode.speed = __cpu_to_le32(speed),
.reg_mode.duplex = duplex,
.reg_mode.fec = fec
} reg_mode;
static void ma35_gpio_set_mode(void __iomem *reg_mode, unsigned int gpio, u32 mode)
u32 regval = readl(reg_mode);
writel(regval, reg_mode);
static u32 ma35_gpio_get_mode(void __iomem *reg_mode, unsigned int gpio)
u32 regval = readl(reg_mode);
void __iomem *reg_mode = bank->reg_base + MA35_GP_REG_MODE;
ma35_gpio_set_mode(reg_mode, gpio, MA35_GP_MODE_INPUT);
void __iomem *reg_mode = bank->reg_base + MA35_GP_REG_MODE;
ma35_gpio_set_mode(reg_mode, gpio, MA35_GP_MODE_OUTPUT);
int pm_mode, reg_mode;
reg_mode = REGULATOR_MODE_FAST;
reg_mode = REGULATOR_MODE_NORMAL;
reg_mode = REGULATOR_MODE_IDLE;
return reg_mode;
ep->reg_mode = &dev->regs->ep_mode[i];
dev->ep[0].reg_mode = NULL;
writel(mode, ep->reg_mode);
u32 __iomem *reg_mode;