reg_isr
isr = kw_read_reg(reg_isr) & KW_I2C_IRQ_MASK;
kw_write_reg(reg_isr, isr);
kw_write_reg(reg_isr, KW_I2C_IRQ_ADDR);
kw_write_reg(reg_isr, KW_I2C_IRQ_DATA);
kw_write_reg(reg_isr, KW_I2C_IRQ_DATA);
kw_write_reg(reg_isr, KW_I2C_IRQ_STOP);
kw_write_reg(reg_isr, KW_I2C_IRQ_START);
kw_i2c_handle_interrupt(host, kw_read_reg(reg_isr));
kw_i2c_handle_interrupt(host, kw_read_reg(reg_isr));
kw_write_reg(reg_isr, kw_read_reg(reg_isr));
kw_write_reg(reg_isr, kw_read_reg(reg_isr));
i2c->reg_isr = i2c->reg_base + pxa_reg_layout[i2c_type].isr;
void __iomem *reg_isr;
#define _ISR(i2c) ((i2c)->reg_isr)
u32 reg40, reg_isr;
reg_isr = readw(ndev->bmmio0 + REG_ISR);
if (reg_isr & NETUP_UNIDVB_IRQ_SPI)
if (reg_isr & NETUP_UNIDVB_IRQ_I2C0) {
} else if (reg_isr & NETUP_UNIDVB_IRQ_I2C1) {
} else if (reg_isr & NETUP_UNIDVB_IRQ_DMA1) {
} else if (reg_isr & NETUP_UNIDVB_IRQ_DMA2) {
} else if (reg_isr & NETUP_UNIDVB_IRQ_CI) {
__func__, reg_isr);