reg_encode
val = reg_encode(reg, GENERIC_OPCODE, opcode);
val |= reg_encode(reg, GENERIC_CHID, channel_id);
val |= reg_encode(reg, GENERIC_EE, GSI_EE_MODEM);
val |= reg_encode(reg, GENERIC_PARAMS, params);
val = reg_encode(reg, CHTYPE_PROTOCOL, type);
return val | reg_encode(reg, CHTYPE_PROTOCOL_MSB, type);
val = reg_encode(reg, EV_CHID, evt_ring_id);
val |= reg_encode(reg, EV_OPCODE, opcode);
val = reg_encode(reg, CH_CHID, channel_id);
val |= reg_encode(reg, CH_OPCODE, opcode);
val = reg_encode(reg, EV_CHTYPE, GSI_CHANNEL_TYPE_GPI);
val |= reg_encode(reg, EV_ELEMENT_SIZE, GSI_RING_ELEMENT_SIZE);
val = reg_encode(reg, R_LENGTH, ring->count * GSI_RING_ELEMENT_SIZE);
val = reg_encode(reg, EV_MODT, GSI_EVT_RING_INT_MODT);
val |= reg_encode(reg, EV_MODC, 1); /* comes from channel */
val |= reg_encode(reg, ERINDEX, channel->evt_ring_id);
val |= reg_encode(reg, ELEMENT_SIZE, GSI_RING_ELEMENT_SIZE);
val = reg_encode(reg, CH_R_LENGTH, size);
val |= reg_encode(reg, CH_ERINDEX, channel->evt_ring_id);
val = reg_encode(reg, WRR_WEIGHT, wrr_weight);
val |= reg_encode(reg, PREFETCH_MODE, ESCAPE_BUF_ONLY);
val |= reg_encode(reg, AGGR_EN, IPA_ENABLE_AGGR);
val |= reg_encode(reg, AGGR_TYPE, IPA_GENERIC);
val |= reg_encode(reg, BYTE_LIMIT, limit);
val |= reg_encode(reg, AGGR_EN, IPA_ENABLE_DEAGGR);
val |= reg_encode(reg, AGGR_TYPE, IPA_QCMAP);
val |= reg_encode(reg, AGGR_EN, IPA_BYPASS_AGGR);
return reg_encode(reg, TIMER_GRAN_SEL, 1) |
reg_encode(reg, TIMER_LIMIT, ticks);
return reg_encode(reg, TIMER_BASE_VALUE, (u32)ticks);
val = reg_encode(reg, TIMER_SCALE, scale);
val |= reg_encode(reg, TIMER_BASE_VALUE, (u32)ticks >> scale);
val = reg_encode(reg, ENDP_RSRC_GRP, resource_group);
val = reg_encode(reg, SEQ_TYPE, endpoint->config.tx.seq_type);
val |= reg_encode(reg, SEQ_REP_TYPE,
val |= reg_encode(reg, STATUS_ENDP, status_endpoint_id);
val = reg_encode(reg, ROUTE_DEF_PIPE, endpoint_id);
val |= reg_encode(reg, ROUTE_FRAG_DEF_PIPE, endpoint_id);
val |= reg_encode(reg, CS_METADATA_HDR_OFFSET, off);
val |= reg_encode(reg, CS_OFFLOAD_EN, enabled);
val = reg_encode(reg, NAT_EN, IPA_NAT_TYPE_BYPASS);
val = reg_encode(reg, HDR_LEN, header_size & field_max);
val |= reg_encode(reg, HDR_LEN_MSB, header_size);
val = reg_encode(reg, HDR_OFST_METADATA, offset);
val |= reg_encode(reg, HDR_OFST_METADATA_MSB, offset);
val |= reg_encode(reg, HDR_OFST_PKT_SIZE, off);
val |= reg_encode(reg, HDR_PAD_TO_ALIGNMENT, pad_align);
val |= reg_encode(reg, HDR_OFST_PKT_SIZE_MSB, off);
val = reg_encode(reg, ENDP_MODE, IPA_DMA);
val |= reg_encode(reg, DEST_PIPE_INDEX, dma_endpoint_id);
val = reg_encode(reg, ENDP_MODE, IPA_BASIC);
return reg_encode(reg, AGGR_GRAN_SEL, select) |
reg_encode(reg, TIME_LIMIT, ticks);
return reg_encode(reg, TIME_LIMIT, ticks);
val = reg_encode(reg, GEN_QMB_0_MAX_WRITES, data0->max_writes);
val |= reg_encode(reg, GEN_QMB_1_MAX_WRITES, data1->max_writes);
val = reg_encode(reg, GEN_QMB_0_MAX_READS, data0->max_reads);
val |= reg_encode(reg, GEN_QMB_0_MAX_READS_BEATS,
val = reg_encode(reg, GEN_QMB_1_MAX_READS, data1->max_reads);
val |= reg_encode(reg, GEN_QMB_1_MAX_READS_BEATS,
val = reg_encode(reg, DPL_TIMESTAMP_LSB, DPL_TIMESTAMP_SHIFT);
val = reg_encode(reg, TAG_TIMESTAMP_LSB, TAG_TIMESTAMP_SHIFT);
val = reg_encode(reg, NAT_TIMESTAMP_LSB, NAT_TIMESTAMP_SHIFT);
val = reg_encode(reg, PULSE_GRAN_0, IPA_GRAN_100_US);
val |= reg_encode(reg, PULSE_GRAN_1, IPA_GRAN_1_MS);
val |= reg_encode(reg, PULSE_GRAN_2, IPA_GRAN_10_MS);
val |= reg_encode(reg, PULSE_GRAN_3, IPA_GRAN_10_MS);
val |= reg_encode(reg, PULSE_GRAN_2, IPA_GRAN_1_MS);
val = reg_encode(reg, DIV_VALUE, IPA_XO_CLOCK_DIVIDER - 1);
val = reg_encode(reg, AGGR_GRANULARITY, granularity);
val = reg_encode(reg, ENTER_IDLE_DEBOUNCE_THRESH,
val = reg_encode(reg, IPA_BASE_ADDR, offset);
val = reg_encode(reg, X_MIN_LIM, xlimits->min);
val |= reg_encode(reg, X_MAX_LIM, xlimits->max);
val |= reg_encode(reg, Y_MIN_LIM, ylimits->min);
val |= reg_encode(reg, Y_MAX_LIM, ylimits->max);