readb_poll_timeout
if (readb_poll_timeout(priv->base + NPCM_RNGCS_REG,
ret = readb_poll_timeout(priv->io_base + TS73XX_FPGA_CONFIG_REG,
ret = readb_poll_timeout(ki2c->base + KI2C_STATUS_REG,
return readb_poll_timeout(addr, val, (val & mask), KI2C_POLL_DELAY_US,
return readb_poll_timeout(priv->base + I2C_LS2X_SR, value,
return readb_poll_timeout(addr, val, val & mask, 0, 100);
ret = readb_poll_timeout(riic->base + riic->info->regs[RIIC_ICCR2], val,
ret = readb_poll_timeout(adc->base + JZ_ADC_REG_ENABLE, val,
ret = readb_poll_timeout(host->ioaddr + SDHCI_SOFTWARE_RESET, sw_rst,
return readb_poll_timeout(cs553x->mmio + MM_NAND_STS, status,
ret = readb_poll_timeout(data->busy, status, status & BIT(5), 0, timeout_us);
ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat,
ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat,
ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat,
ret = readb_poll_timeout(phy->regs + PHY_REG(34), val,
ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, !(tmp & mask),
ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, (tmp & mask),
ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, !(tmp & mask),
ret = readb_poll_timeout(priv->base + RTCA3_RADJ, tmp, !tmp, 10,
ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, ((tmp & mask) == mask),
return readb_poll_timeout(priv->base + RTCA3_RCR1, tmp, ((tmp & RTCA3_RCR1_PES) == val),
ret = readb_poll_timeout(reg_base + OFFSET_SPIMCTRL, value,
ret = readb_poll_timeout(reg_base + OFFSET_SPIMCTRL, value,
ret = readb_poll_timeout(reg_base + OFFSET_SPIMCTRL, value,
ret = readb_poll_timeout(kspi->base + KSPI2_STATUS_REG,
ret = readb_poll_timeout(kspi->base + KSPI2_STATUS_REG,
ret = readb_poll_timeout(loongson_spi->base + LOONGSON_SPI_SPSR_REG,
readb_poll_timeout((adev)->dsp_ba + (reg), val, cond, \