arch/arc/include/asm/irqflags-arcv2.h

80

unsigned int irqact = read_aux_reg(AUX_IRQ_ACT);

arch/arc/kernel/fpu.c

75

save->ctrl = read_aux_reg(ARC_REG_FPU_CTRL);

arch/arc/kernel/fpu.c

76

save->status = read_aux_reg(ARC_REG_FPU_STATUS);

arch/arc/kernel/intc-arcv2.c

93

tmp = read_aux_reg(ARC_REG_STATUS32);

arch/arc/kernel/intc-compact.c

47

ienb = read_aux_reg(AUX_IENABLE);

arch/arc/kernel/intc-compact.c

68

ienb = read_aux_reg(AUX_IENABLE);

arch/arc/kernel/intc-compact.c

77

ienb = read_aux_reg(AUX_IENABLE);

arch/arc/kernel/mcip.c

117

ipi_was_pending = read_aux_reg(ARC_REG_MCIP_READBACK);

arch/arc/kernel/mcip.c

139

cpu = read_aux_reg(ARC_REG_MCIP_READBACK); /* 1,2,4,8... */

arch/arc/kernel/mcip.c

44

gfrc_halt_mask = read_aux_reg(ARC_REG_MCIP_READBACK);

arch/arc/kernel/mcip.c

64

mcip_mask = read_aux_reg(ARC_REG_MCIP_READBACK);

arch/arc/kernel/perf_event.c

272

tmp = read_aux_reg(ARC_REG_PCT_CONTROL);

arch/arc/kernel/perf_event.c

274

result = (u64) (read_aux_reg(ARC_REG_PCT_SNAPH)) << 32;

arch/arc/kernel/perf_event.c

275

result |= read_aux_reg(ARC_REG_PCT_SNAPL);

arch/arc/kernel/perf_event.c

393

tmp = read_aux_reg(ARC_REG_PCT_CONTROL);

arch/arc/kernel/perf_event.c

401

tmp = read_aux_reg(ARC_REG_PCT_CONTROL);

arch/arc/kernel/perf_event.c

469

read_aux_reg(ARC_REG_PCT_INT_CTRL) | BIT(idx));

arch/arc/kernel/perf_event.c

489

read_aux_reg(ARC_REG_PCT_INT_CTRL) & ~BIT(idx));

arch/arc/kernel/perf_event.c

572

active_ints = read_aux_reg(ARC_REG_PCT_INT_ACT);

arch/arc/kernel/perf_event.c

593

read_aux_reg(ARC_REG_PCT_INT_CTRL) | BIT(idx));

arch/arc/kernel/perf_event.c

777

cc_name.indiv.word0 = le32_to_cpu(read_aux_reg(ARC_REG_CC_NAME0));

arch/arc/kernel/perf_event.c

778

cc_name.indiv.word1 = le32_to_cpu(read_aux_reg(ARC_REG_CC_NAME1));

arch/arc/kernel/setup.c

140

base = read_aux_reg(ARC_REG_DCCM_BASE_BUILD);

arch/arc/kernel/setup.c

235

ctl = read_aux_reg(ARC_REG_LPB_CTRL);

arch/arc/kernel/setup.c

254

base = read_aux_reg(ARC_REG_AUX_ICCM);

arch/arc/kernel/setup.c

264

base = read_aux_reg(ARC_REG_AUX_DCCM);

arch/arc/kernel/setup.c

322

vec_base = read_aux_reg(AUX_INTR_VEC_BASE);

arch/arc/mm/cache.c

371

write_aux_reg(ctl, read_aux_reg(ctl) | DC_CTRL_INV_MODE_FLUSH);

arch/arc/mm/cache.c

380

unsigned int val = read_aux_reg(ctl);

arch/arc/mm/cache.c

408

while ((reg = read_aux_reg(ctl)) & DC_CTRL_FLUSH_STATUS)

arch/arc/mm/cache.c

444

write_aux_reg(r, read_aux_reg(r) | DC_CTRL_DIS);

arch/arc/mm/cache.c

451

write_aux_reg(r, read_aux_reg(r) & ~DC_CTRL_DIS);

arch/arc/mm/cache.c

492

read_aux_reg(ARC_REG_IC_CTRL); /* blocks */

arch/arc/mm/cache.c

569

ctrl = read_aux_reg(ARC_REG_SLC_CTRL);

arch/arc/mm/cache.c

601

read_aux_reg(ARC_REG_SLC_CTRL);

arch/arc/mm/cache.c

603

while (read_aux_reg(ARC_REG_SLC_CTRL) & SLC_CTRL_BUSY);

arch/arc/mm/cache.c

628

ctrl = read_aux_reg(ARC_REG_SLC_CTRL);

arch/arc/mm/cache.c

651

read_aux_reg(ARC_REG_SLC_CTRL);

arch/arc/mm/cache.c

653

while (read_aux_reg(ARC_REG_SLC_CTRL) & SLC_CTRL_BUSY);

arch/arc/mm/cache.c

665

ctrl = read_aux_reg(r);

arch/arc/mm/cache.c

680

read_aux_reg(r);

arch/arc/mm/cache.c

683

while (read_aux_reg(r) & SLC_CTRL_BUSY);

arch/arc/mm/cache.c

691

write_aux_reg(r, read_aux_reg(r) | SLC_CTRL_DIS);

arch/arc/mm/cache.c

698

write_aux_reg(r, read_aux_reg(r) & ~SLC_CTRL_DIS);

arch/arc/mm/cache.c

945

if (read_aux_reg(ARC_REG_IO_COH_ENABLE) & ARC_IO_COH_ENABLE_BIT)

arch/arc/mm/cache.c

955

if (read_aux_reg(ARC_REG_SLC_BCR))

arch/arc/mm/tlb.c

438

asid_or_sasid = read_aux_reg(ARC_REG_PID) & 0xff;

arch/arc/mm/tlb.c

54

idx = read_aux_reg(ARC_REG_TLBINDEX);

arch/arc/mm/tlb.c

572

bcr = read_aux_reg(ARC_REG_MMU_BCR);

arch/arc/mm/tlb.c

717

pd0[way] = read_aux_reg(ARC_REG_TLBPD0);

arch/arc/plat-axs10x/axs10x.c

312

unsigned int num_cores = (read_aux_reg(ARC_REG_MCIP_BCR) >> 16) & 0x3F;

drivers/clocksource/arc_timer.c

140

l = read_aux_reg(AUX_RTC_LOW);

drivers/clocksource/arc_timer.c

141

h = read_aux_reg(AUX_RTC_HIGH);

drivers/clocksource/arc_timer.c

142

status = read_aux_reg(AUX_RTC_CTRL);

drivers/clocksource/arc_timer.c

198

return (u64) read_aux_reg(ARC_REG_TIMER1_CNT);

drivers/clocksource/arc_timer.c

80

l = read_aux_reg(ARC_REG_MCIP_READBACK);

drivers/clocksource/arc_timer.c

83

h = read_aux_reg(ARC_REG_MCIP_READBACK);

include/soc/arc/arc_aux.h

37

tmp = read_aux_reg(reg); \

include/soc/arc/mcip.h

130

return read_aux_reg(ARC_REG_MCIP_READBACK);