r23
unsigned long r23;
dest[23] = pt->r23;
PT_REG( r20), PT_REG( r21), PT_REG( r22), PT_REG( r23),
err |= __get_user(regs->r23, sc->sc_regs+23);
err |= __put_user(regs->r23, sc->sc_regs+23);
regs->r22, regs->r23, regs->r24);
R(r19), R(r20), R(r21), R(r22), R(r23), R(r24), R(r25), R(r26),
push r23
pop r23
push r23
pop r23
unsigned long r25, r24, r23, r22, r21, r20, r19, r18, r17, r16, r15, r14, r13;
unsigned long r25, r24, r23, r22, r21, r20, r19, r18, r17, r16, r15, r14, r13;
unsigned long r23;
PTREGS_INFO(r23), \
unsigned long r25, r24, r23, r22, r21, r20;
membuf_store(&to, cregs->r23);
REG_IN_ONE(callee.r23, &cregs->r23);
regs->r21, regs->r22, regs->r23,
DEST.r23 = REGS->r23; \
unsigned long r23;
unsigned long r23;
unsigned long r23;
{ "r23", GDB_SIZEOF_REG, offsetof(struct pt_regs, r23)},
regs->r23);
#define s0 $r23 /* callee saved */
REG_OFFSET_NAME(r23, regs[23]),
__u32 r23;
_r->r20 = _r->r21 = _r->r22 = _r->r23 = \
microblaze_reg_t r23;
DEFINE(CC_R23, offsetof(struct cpu_context, r23));
DEFINE(PT_R23, offsetof(struct pt_regs, r23));
regs->r21, regs->r22, regs->r23, regs->r24);
COPY(r22); COPY(r23); COPY(r24); COPY(r25);
COPY(r22); COPY(r23); COPY(r24); COPY(r25);
REG_OFFSET_NAME(r23, regs[23]),
pr_reg[30] = sw->r23; \
ldw r23, SW_R23(sp)
stw r23, SW_R23(sp)
unsigned long r23;
OFFSET(SW_R23, switch_stack, r23);
childstack->r23 = tls;
err |= __put_user(sw->r23, &gregs[22]);
err |= __get_user(sw->r23, &gregs[22]);
arg3: .reg %r23
r23: .reg %r23
STREG %r23, PT_GR23(\regs)
LDREG PT_GR23(\regs), %r23
#define K_LOAD_ARGS_4(r26,r25,r24,r23) \
register unsigned long __r23 __asm__("r23") = (unsigned long)(r23); \
#define K_LOAD_ARGS_5(r26,r25,r24,r23,r22) \
K_LOAD_ARGS_4(r26,r25,r24,r23)
#define K_LOAD_ARGS_6(r26,r25,r24,r23,r22,r21) \
K_LOAD_ARGS_5(r26,r25,r24,r23,r22)
asmlinkage long sys32_unimplemented(int r26, int r25, int r24, int r23,
#define r23 %r23
x.r23 = read_reg( x.fan, 0x23, 1 );
write_reg( x.fan, 0x23, x.r23, 1 );
int r0, r1, r20, r23, r25; /* saved register */
u32 val, r9, r23;
err = ice_read_cgu_reg(hw, ICE_CGU_R23, &r23);
ice_tspll_log_cfg(hw, !!FIELD_GET(ICE_CGU_R23_R24_TSPLL_ENABLE, r23),
FIELD_GET(ICE_CGU_R23_R24_TIME_REF_SEL, r23),
if (FIELD_GET(ICE_CGU_R23_R24_TSPLL_ENABLE, r23)) {
r23 &= ~ICE_CGU_R23_R24_TSPLL_ENABLE;
err = ice_write_cgu_reg(hw, ICE_CGU_R23, r23);
err = ice_read_cgu_reg(hw, ICE_CGU_R23, &r23);
r23 &= ~(ICE_CGU_R23_R24_REF1588_CK_DIV | ICE_CGU_R23_R24_TIME_REF_SEL);
r23 |= FIELD_PREP(ICE_CGU_R23_R24_TIME_REF_SEL, clk_src);
err = ice_write_cgu_reg(hw, ICE_CGU_R23, r23);
r23 |= ICE_CGU_R23_R24_TSPLL_ENABLE;
err = ice_write_cgu_reg(hw, ICE_CGU_R23, r23);
err = ice_read_cgu_reg(hw, ICE_CGU_R23, &r23);
ice_tspll_log_cfg(hw, !!FIELD_GET(ICE_CGU_R23_R24_TSPLL_ENABLE, r23),
FIELD_GET(ICE_CGU_R23_R24_TIME_REF_SEL, r23),
r20, r21, r22, r23, r24, r25, r26, r27, r28, r29, \
.radio_tx0_pgaa_boost_tune = r23, \
r20, r21, r22, r23, r24, r25, r26, r27) \
.radio_pga_boost_tune_core1 = r23, \
#define rW7 r23
#define s0 $r23
std r23,(top_pos - 64)(%r1); \
ld r23,(top_pos - 64)(%r1); \
ld r23,72(r3)
#define r23 %r23