pte_flags
unsigned long pte_flags;
pte_flags = pte_val(pte) & ~PTE_RPN_MASK;
return __pgprot(pte_flags);
unsigned long pte_flags = pte_val(pte) & _PAGE_CHG_MASK;
pte_flags |= pgprot_val(PAGE_KERNEL);
pte_flags |= pgprot_val(PAGE_KERNEL_RO);
pte_flags |= pte_val(pte) & mio_wb_bit_mask;
return __pgprot(pte_flags);
set_pte(pte, __pte(ppd->paddr | ppd->pte_flags));
pmdval_t pmd_flags, pteval_t pte_flags)
ppd->pte_flags = pte_flags;
pteval_t pte_flags;
return (pte_flags(pte) & (_PAGE_PROTNONE | _PAGE_PRESENT))
return pte_flags(pte) & _PAGE_SWP_EXCLUSIVE;
return pte_flags(pte) & _PAGE_SWP_SOFT_DIRTY;
return pte_flags(pte) & _PAGE_SWP_UFFD_WP;
return pte_flags(pte) & _PAGE_DIRTY_BITS;
static inline u16 pte_flags_pkey(unsigned long pte_flags)
return (pte_flags & _PAGE_PKEY_MASK) >> _PAGE_BIT_PKEY_BIT0;
(pte_flags(pte) & (_PAGE_RW | _PAGE_DIRTY)) == _PAGE_DIRTY;
return pte_flags(pte) & _PAGE_ACCESSED;
return (pte_flags(pte) & _PAGE_RW) || pte_shstk(pte);
return pte_flags(pte) & _PAGE_PSE;
return pte_flags(pte) & _PAGE_GLOBAL;
return !(pte_flags(pte) & _PAGE_NX);
return pte_flags(pte) & _PAGE_SPECIAL;
return pte_flags(pte) & _PAGE_UFFD_WP;
return pte_flags(pte) & _PAGE_SOFT_DIRTY;
#define pte_pgprot(x) __pgprot(pte_flags(x))
return pte_flags(a) & (_PAGE_PRESENT | _PAGE_PROTNONE);
if (pte_flags(a) & _PAGE_PRESENT)
if ((pte_flags(a) & _PAGE_PROTNONE) &&
if (!(pte_flags(oldpte) & _PAGE_PRESENT))
return pte_flags_need_flush(pte_flags(oldpte), pte_flags(newpte),
pkeys = pte_flags_pkey(pte_flags(pte));
return pte_flags(pte) & _PAGE_SOFTW1;
if (pte_flags(first) & _PAGE_KERNEL_4K)
if (pte_flags(entry) != pte_flags(first))
if (pte_flags(*pte) & _PAGE_USER) {
if (WARN_ON(!(pte_flags(*pte) & _PAGE_PRESENT)))
u32 pte_flags;
pte_flags = I810_PTE_VALID;
pte_flags |= I830_PTE_SYSTEM_CACHED;
writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
u32 pte_flags = I810_PTE_VALID;
pte_flags |= I810_PTE_LOCAL;
pte_flags |= I830_PTE_SYSTEM_CACHED;
writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
u32 pte_flags = I810_PTE_VALID;
pte_flags |= I830_PTE_SYSTEM_CACHED;
writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
uint64_t pte_flags;
entry->pte_flags);
attachment[i]->pte_flags = get_pte_flags(adev, vm, mem);
uint64_t *pte_flags);
#define amdgpu_gmc_get_vm_pte(adev, vm, bo, vm_flags, pte_flags) \
(pte_flags)))
#define amdgpu_gmc_override_vm_pte_flags(adev, vm, addr, pte_flags) \
((adev), (vm), (addr), (pte_flags))
u64 pte_flags;
pte_flags = AMDGPU_PTE_VALID | AMDGPU_PTE_READABLE;
pte_flags |= AMDGPU_PTE_SYSTEM | AMDGPU_PTE_SNOOPED;
pte_flags |= AMDGPU_PTE_WRITEABLE;
pte_flags |= adev->gart.gart_pte_flags;
amdgpu_gart_map(adev, 0, npages, addr, pte_flags, cpu_addr);
uint64_t pte_flags;
pte_flags = AMDGPU_PTE_VALID;
pte_flags |= (domain == SVM_RANGE_VRAM_DOMAIN) ? 0 : AMDGPU_PTE_SYSTEM;
pte_flags |= snoop ? AMDGPU_PTE_SNOOPED : 0;
pte_flags |= AMDGPU_PTE_IS_PTE;
amdgpu_gmc_get_vm_pte(node->adev, vm, NULL, mapping_flags, &pte_flags);
pte_flags |= AMDGPU_PTE_READABLE;
pte_flags |= AMDGPU_PTE_WRITEABLE;
pte_flags |= AMDGPU_PTE_BUS_ATOMICS;
return pte_flags;
uint64_t pte_flags;
pte_flags = svm_range_get_pte_flags(pdd->dev, vm, prange, last_domain);
pte_flags &= ~AMDGPU_PTE_WRITEABLE;
pte_flags);
pte_flags,
vm->insert_entries(vm, vma_res, pat_index, pte_flags);
u32 pte_flags;
pte_flags = 0;
pte_flags |= PTE_READ_ONLY;
pte_flags |= PTE_LM;
u32 pte_flags;
pte_flags = vm->has_read_only;
pte_flags |= PTE_LM;
pte_flags);
u32 pte_flags;
pte_flags = 0;
pte_flags |= PTE_LM;
pte_flags);
u32 pte_flags;
pte_flags = 0;
pte_flags |= PTE_READ_ONLY;
pte_flags |= PTE_LM;
vm->insert_entries(vm, vma_res, pat_index, pte_flags);
u32 pte_flags;
pte_flags = 0;
pte_flags |= PTE_READ_ONLY;
vm->insert_entries(vm, vma_res, pat_index, pte_flags);
u32 pte_flags;
pte_flags = 0;
pte_flags |= PTE_READ_ONLY;
pte_flags |= PTE_LM;
vm->insert_entries(vm, vma_res, pat_index, pte_flags);
unsigned int pte_flags = 0;
pte_flags |= PTE_LM;
ce->vm->insert_entries(ce->vm, &vb_res, pat_index, pte_flags);
pte_flags |= PTE_LM;
pte_flags);
pte_flags);
u32 pte_flags = 0;
u32 pte_flags;
pte_flags = get_mips_pte_flags(true, true, cache_policy);
pte |= pte_flags;
u64 pte_flags,
write_pte(ggtt, *ggtt_ofs, pte_flags | addr);
u64 pte_flags, xe_ggtt_set_pte_fn write_pte, void *data)
write_ggtt_rotated(ggtt, &ggtt_ofs, pte_flags, write_pte,
u32 pte_flags;
pte_flags = src_is_vram ? (PTE_UPDATE_FLAG_IS_VRAM |
batch_size += pte_update_size(m, pte_flags, src, &src_it, &src_L0,
pte_flags = dst_is_vram ? (PTE_UPDATE_FLAG_IS_VRAM |
batch_size += pte_update_size(m, pte_flags, dst, &dst_it, &src_L0,
struct xe_bo *bo, u64 pte_flags,
transform(ggtt, node, pte_flags, ggtt->pt_ops->ggtt_set_pte, arg);
xe_ggtt_map_bo(ggtt, node, bo, pte_flags);
u64 pte_flags,
u32 pte_flags = PTE_UPDATE_FLAG_IS_VRAM;
pte_flags |= use_comp_pat ? PTE_UPDATE_FLAG_IS_COMP_PTE : 0;
batch_size += pte_update_size(m, pte_flags, vram, &vram_it, &vram_L0,
u32 pte_flags;
pte_flags = clear_vram ? PTE_UPDATE_FLAG_IS_VRAM : 0;
pte_update_size(m, pte_flags, src, &src_it,
u32 pte_flags;
pte_flags = src_is_vram ? PTE_UPDATE_FLAG_IS_VRAM : 0;
pte_flags |= use_comp_pat ? PTE_UPDATE_FLAG_IS_COMP_PTE : 0;
batch_size += pte_update_size(m, pte_flags, src, &src_it, &src_L0,
pte_flags = dst_is_vram ? PTE_UPDATE_FLAG_IS_VRAM : 0;
batch_size += pte_update_size(m, pte_flags, dst,