arch/mips/include/asm/octeon/cvmx-led-defs.h
63
uint64_t phase:7;
arch/mips/include/asm/octeon/cvmx-led-defs.h
65
uint64_t phase:7;
drivers/acpi/acpi_fpdt.c
79
#define FPDT_ATTR(phase, name) \
drivers/acpi/acpi_fpdt.c
83
return sprintf(buf, "%llu\n", record_##phase->name); \
drivers/block/swim.c
254
swim_write(base, phase, 0xf5);
drivers/block/swim.c
255
if (swim_read(base, phase) != 0xf5)
drivers/block/swim.c
257
swim_write(base, phase, 0xf6);
drivers/block/swim.c
258
if (swim_read(base, phase) != 0xf6)
drivers/block/swim.c
260
swim_write(base, phase, 0xf7);
drivers/block/swim.c
261
if (swim_read(base, phase) != 0xf7)
drivers/block/swim.c
272
swim_write(base, phase, RELAX);
drivers/block/swim.c
276
swim_write(base, phase, sel & CA_MASK);
drivers/block/swim.c
287
swim_write(base, phase, (LSTRB<<4) | LSTRB);
drivers/block/swim.c
289
swim_write(base, phase, (LSTRB<<4) | ((~LSTRB) & 0x0F));
drivers/char/ipmi/kcs_bmc_cdev_ipmi.c
133
priv->phase = KCS_PHASE_ERROR;
drivers/char/ipmi/kcs_bmc_cdev_ipmi.c
145
switch (priv->phase) {
drivers/char/ipmi/kcs_bmc_cdev_ipmi.c
147
priv->phase = KCS_PHASE_WRITE_DATA;
drivers/char/ipmi/kcs_bmc_cdev_ipmi.c
165
priv->phase = KCS_PHASE_WRITE_DONE;
drivers/char/ipmi/kcs_bmc_cdev_ipmi.c
187
priv->phase = KCS_PHASE_IDLE;
drivers/char/ipmi/kcs_bmc_cdev_ipmi.c
198
priv->phase = KCS_PHASE_ABORT_ERROR2;
drivers/char/ipmi/kcs_bmc_cdev_ipmi.c
205
priv->phase = KCS_PHASE_IDLE;
drivers/char/ipmi/kcs_bmc_cdev_ipmi.c
224
priv->phase = KCS_PHASE_WRITE_START;
drivers/char/ipmi/kcs_bmc_cdev_ipmi.c
231
if (priv->phase != KCS_PHASE_WRITE_DATA) {
drivers/char/ipmi/kcs_bmc_cdev_ipmi.c
236
priv->phase = KCS_PHASE_WRITE_END_CMD;
drivers/char/ipmi/kcs_bmc_cdev_ipmi.c
243
priv->phase = KCS_PHASE_ABORT_ERROR1;
drivers/char/ipmi/kcs_bmc_cdev_ipmi.c
367
if (priv->phase == KCS_PHASE_WRITE_DONE) {
drivers/char/ipmi/kcs_bmc_cdev_ipmi.c
368
priv->phase = KCS_PHASE_WAIT_READ;
drivers/char/ipmi/kcs_bmc_cdev_ipmi.c
400
if (priv->phase == KCS_PHASE_WAIT_READ) {
drivers/char/ipmi/kcs_bmc_cdev_ipmi.c
401
priv->phase = KCS_PHASE_READ;
drivers/char/ipmi/kcs_bmc_cdev_ipmi.c
76
enum kcs_ipmi_phases phase;
drivers/char/ppdev.c
404
pp->saved_state.phase = info->phase;
drivers/char/ppdev.c
406
info->phase = pp->state.phase;
drivers/char/ppdev.c
435
pp->state.phase = init_phase(mode);
drivers/char/ppdev.c
439
pp->pdev->port->ieee1284.phase = pp->state.phase;
drivers/char/ppdev.c
459
int phase;
drivers/char/ppdev.c
461
if (copy_from_user(&phase, argp, sizeof(phase)))
drivers/char/ppdev.c
465
pp->state.phase = phase;
drivers/char/ppdev.c
468
pp->pdev->port->ieee1284.phase = phase;
drivers/char/ppdev.c
474
int phase;
drivers/char/ppdev.c
477
phase = pp->pdev->port->ieee1284.phase;
drivers/char/ppdev.c
479
phase = pp->state.phase;
drivers/char/ppdev.c
480
if (copy_to_user(argp, &phase, sizeof(phase)))
drivers/char/ppdev.c
551
pp->state.phase = info->phase;
drivers/char/ppdev.c
553
info->phase = pp->saved_state.phase;
drivers/char/ppdev.c
697
pp->state.phase = init_phase(pp->state.mode);
drivers/char/ppdev.c
729
pp->saved_state.phase = info->phase;
drivers/char/ppdev.c
731
info->phase = pp->state.phase;
drivers/char/ppdev.c
748
pp->state.phase = info->phase;
drivers/char/ppdev.c
750
info->phase = pp->saved_state.phase;
drivers/clk/clk-rp1.c
1521
.phase = RP1_PLL_PHASE_0,
drivers/clk/clk-rp1.c
1538
.phase = RP1_PLL_PHASE_0,
drivers/clk/clk-rp1.c
1555
.phase = RP1_PLL_PHASE_0,
drivers/clk/clk-rp1.c
336
unsigned int phase;
drivers/clk/clk-rp1.c
656
ph_reg |= data->phase << PLL_PH_PHASE_SHIFT;
drivers/clk/clk.c
2974
core->phase = degrees;
drivers/clk/clk.c
3041
core->phase = ret;
drivers/clk/clk.c
3277
int phase;
drivers/clk/clk.c
3288
phase = clk_core_get_phase(c);
drivers/clk/clk.c
3289
if (phase >= 0)
drivers/clk/clk.c
3290
seq_printf(s, "%-5d", phase);
drivers/clk/clk.c
3355
int phase;
drivers/clk/clk.c
3369
phase = clk_core_get_phase(c);
drivers/clk/clk.c
3370
if (phase >= 0)
drivers/clk/clk.c
3371
seq_printf(s, "\"phase\": %d,", phase);
drivers/clk/clk.c
3507
*val = core->phase;
drivers/clk/clk.c
3882
int phase;
drivers/clk/clk.c
4009
phase = clk_core_get_phase(core);
drivers/clk/clk.c
4010
if (phase < 0) {
drivers/clk/clk.c
4011
ret = phase;
drivers/clk/clk.c
92
int phase;
drivers/clk/hisilicon/clk-hisi-phase.c
100
phase = devm_kzalloc(dev, sizeof(struct clk_hisi_phase), GFP_KERNEL);
drivers/clk/hisilicon/clk-hisi-phase.c
101
if (!phase)
drivers/clk/hisilicon/clk-hisi-phase.c
110
phase->reg = base + clks->offset;
drivers/clk/hisilicon/clk-hisi-phase.c
111
phase->shift = clks->shift;
drivers/clk/hisilicon/clk-hisi-phase.c
112
phase->mask = (BIT(clks->width) - 1) << clks->shift;
drivers/clk/hisilicon/clk-hisi-phase.c
113
phase->lock = lock;
drivers/clk/hisilicon/clk-hisi-phase.c
114
phase->phase_degrees = clks->phase_degrees;
drivers/clk/hisilicon/clk-hisi-phase.c
115
phase->phase_regvals = clks->phase_regvals;
drivers/clk/hisilicon/clk-hisi-phase.c
116
phase->phase_num = clks->phase_num;
drivers/clk/hisilicon/clk-hisi-phase.c
117
phase->hw.init = &init;
drivers/clk/hisilicon/clk-hisi-phase.c
119
return devm_clk_register(dev, &phase->hw);
drivers/clk/hisilicon/clk-hisi-phase.c
30
static int hisi_phase_regval_to_degrees(struct clk_hisi_phase *phase,
drivers/clk/hisilicon/clk-hisi-phase.c
35
for (i = 0; i < phase->phase_num; i++)
drivers/clk/hisilicon/clk-hisi-phase.c
36
if (phase->phase_regvals[i] == regval)
drivers/clk/hisilicon/clk-hisi-phase.c
37
return phase->phase_degrees[i];
drivers/clk/hisilicon/clk-hisi-phase.c
44
struct clk_hisi_phase *phase = to_clk_hisi_phase(hw);
drivers/clk/hisilicon/clk-hisi-phase.c
47
regval = readl(phase->reg);
drivers/clk/hisilicon/clk-hisi-phase.c
48
regval = (regval & phase->mask) >> phase->shift;
drivers/clk/hisilicon/clk-hisi-phase.c
50
return hisi_phase_regval_to_degrees(phase, regval);
drivers/clk/hisilicon/clk-hisi-phase.c
53
static int hisi_phase_degrees_to_regval(struct clk_hisi_phase *phase,
drivers/clk/hisilicon/clk-hisi-phase.c
58
for (i = 0; i < phase->phase_num; i++)
drivers/clk/hisilicon/clk-hisi-phase.c
59
if (phase->phase_degrees[i] == degrees)
drivers/clk/hisilicon/clk-hisi-phase.c
60
return phase->phase_regvals[i];
drivers/clk/hisilicon/clk-hisi-phase.c
67
struct clk_hisi_phase *phase = to_clk_hisi_phase(hw);
drivers/clk/hisilicon/clk-hisi-phase.c
72
regval = hisi_phase_degrees_to_regval(phase, degrees);
drivers/clk/hisilicon/clk-hisi-phase.c
76
spin_lock_irqsave(phase->lock, flags);
drivers/clk/hisilicon/clk-hisi-phase.c
78
val = readl(phase->reg);
drivers/clk/hisilicon/clk-hisi-phase.c
79
val &= ~phase->mask;
drivers/clk/hisilicon/clk-hisi-phase.c
80
val |= regval << phase->shift;
drivers/clk/hisilicon/clk-hisi-phase.c
81
writel(val, phase->reg);
drivers/clk/hisilicon/clk-hisi-phase.c
83
spin_unlock_irqrestore(phase->lock, flags);
drivers/clk/hisilicon/clk-hisi-phase.c
97
struct clk_hisi_phase *phase;
drivers/clk/meson/clk-phase.c
40
struct meson_clk_phase_data *phase = meson_clk_phase_data(clk);
drivers/clk/meson/clk-phase.c
43
val = meson_parm_read(clk->map, &phase->ph);
drivers/clk/meson/clk-phase.c
45
return meson_clk_degrees_from_val(val, phase->ph.width);
drivers/clk/meson/clk-phase.c
51
struct meson_clk_phase_data *phase = meson_clk_phase_data(clk);
drivers/clk/meson/clk-phase.c
54
val = meson_clk_degrees_to_val(degrees, phase->ph.width);
drivers/clk/meson/clk-phase.c
55
meson_parm_write(clk->map, &phase->ph, val);
drivers/clk/sunxi-ng/ccu_phase.c
110
spin_lock_irqsave(phase->common.lock, flags);
drivers/clk/sunxi-ng/ccu_phase.c
111
reg = readl(phase->common.base + phase->common.reg);
drivers/clk/sunxi-ng/ccu_phase.c
112
reg &= ~GENMASK(phase->width + phase->shift - 1, phase->shift);
drivers/clk/sunxi-ng/ccu_phase.c
113
writel(reg | (delay << phase->shift),
drivers/clk/sunxi-ng/ccu_phase.c
114
phase->common.base + phase->common.reg);
drivers/clk/sunxi-ng/ccu_phase.c
115
spin_unlock_irqrestore(phase->common.lock, flags);
drivers/clk/sunxi-ng/ccu_phase.c
15
struct ccu_phase *phase = hw_to_ccu_phase(hw);
drivers/clk/sunxi-ng/ccu_phase.c
22
reg = readl(phase->common.base + phase->common.reg);
drivers/clk/sunxi-ng/ccu_phase.c
23
delay = (reg >> phase->shift);
drivers/clk/sunxi-ng/ccu_phase.c
24
delay &= (1 << phase->width) - 1;
drivers/clk/sunxi-ng/ccu_phase.c
58
struct ccu_phase *phase = hw_to_ccu_phase(hw);
drivers/clk/sunxi/clk-mod0.c
173
struct mmc_phase *phase = to_mmc_phase(hw);
drivers/clk/sunxi/clk-mod0.c
179
value = readl(phase->reg);
drivers/clk/sunxi/clk-mod0.c
180
delay = (value >> phase->offset) & 0x3;
drivers/clk/sunxi/clk-mod0.c
215
struct mmc_phase *phase = to_mmc_phase(hw);
drivers/clk/sunxi/clk-mod0.c
266
spin_lock_irqsave(phase->lock, flags);
drivers/clk/sunxi/clk-mod0.c
267
value = readl(phase->reg);
drivers/clk/sunxi/clk-mod0.c
268
value &= ~GENMASK(phase->offset + 3, phase->offset);
drivers/clk/sunxi/clk-mod0.c
269
value |= delay << phase->offset;
drivers/clk/sunxi/clk-mod0.c
270
writel(value, phase->reg);
drivers/clk/sunxi/clk-mod0.c
271
spin_unlock_irqrestore(phase->lock, flags);
drivers/clk/sunxi/clk-mod0.c
324
struct mmc_phase *phase;
drivers/clk/sunxi/clk-mod0.c
326
phase = kmalloc_obj(*phase);
drivers/clk/sunxi/clk-mod0.c
327
if (!phase)
drivers/clk/sunxi/clk-mod0.c
330
phase->hw.init = &init;
drivers/clk/sunxi/clk-mod0.c
331
phase->reg = reg;
drivers/clk/sunxi/clk-mod0.c
332
phase->lock = lock;
drivers/clk/sunxi/clk-mod0.c
335
phase->offset = 8;
drivers/clk/sunxi/clk-mod0.c
337
phase->offset = 20;
drivers/clk/sunxi/clk-mod0.c
343
clk_data->clks[i] = clk_register(NULL, &phase->hw);
drivers/clk/sunxi/clk-mod0.c
345
kfree(phase);
drivers/cxl/core/pci.c
818
static int update_gpf_port_dvsec(struct pci_dev *pdev, int dvsec, int phase)
drivers/cxl/core/pci.c
824
switch (phase) {
drivers/cxl/core/pci.c
853
phase, GPF_TIMEOUT_BASE_MAX);
drivers/gpib/gpio/gpib_bitbang.c
301
int phase;
drivers/gpib/gpio/gpib_bitbang.c
382
priv->phase = 100;
drivers/gpib/gpio/gpib_bitbang.c
438
priv->count, priv->phase);
drivers/gpib/gpio/gpib_bitbang.c
440
priv->phase = 200;
drivers/gpib/gpio/gpib_bitbang.c
448
priv->phase, priv->cmd, LINVAL);
drivers/gpib/gpio/gpib_bitbang.c
463
priv->phase = 210;
drivers/gpib/gpio/gpib_bitbang.c
469
priv->phase = 220;
drivers/gpib/gpio/gpib_bitbang.c
472
priv->phase = 230;
drivers/gpib/gpio/gpib_bitbang.c
506
priv->phase = 300;
drivers/gpib/gpio/gpib_bitbang.c
544
priv->w_cnt, length, priv->phase, LINVAL, send_eoi);
drivers/gpib/gpio/gpib_bitbang.c
565
priv->phase = 310;
drivers/gpib/gpio/gpib_bitbang.c
598
priv->w_cnt, priv->length, priv->phase);
drivers/gpib/gpio/gpib_bitbang.c
604
priv->w_cnt, priv->length, priv->phase, priv->cmd, LINVAL);
drivers/gpib/gpio/gpib_bitbang.c
605
priv->phase = 400;
drivers/gpib/gpio/gpib_bitbang.c
635
priv->phase = 410;
drivers/gpib/gpio/gpib_bitbang.c
675
dbg_printk(1, "out of order interrupt at %zu:%d.\n", priv->w_cnt, priv->phase);
drivers/gpib/gpio/gpib_bitbang.c
676
priv->phase = 500;
drivers/gpib/gpio/gpib_bitbang.c
691
priv->phase = 510;
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c
53
int modulo, phase;
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c
57
phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk;
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c
59
if (phase > 0xff) {
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c
61
phase = 0xff;
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c
65
DPPCLK0_DTO_PHASE, phase,
drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c
53
int phase;
drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c
67
phase = (req_dppclk + 9999) / 10000;
drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c
69
if (phase > modulo) {
drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c
74
phase = modulo;
drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c
85
phase = 10;
drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c
89
DPPCLK0_DTO_PHASE, phase,
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
575
uint32_t modulo, phase;
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
579
phase = (uint32_t)div_u64((((unsigned long long)modulo * req_dtbclk_khz) + params->ref_dtbclk_khz - 1),
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
586
REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], phase);
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
61
int modulo, phase;
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
619
uint32_t modulo, phase;
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
623
phase = (uint32_t)div_u64((((unsigned long long)modulo * params->req_audio_dtbclk_khz) + params->ref_dtbclk_khz - 1),
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
628
REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_PHASE, phase);
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
65
phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk;
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
67
if (phase > 0xff) {
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
69
phase = 0xff;
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
73
DPPCLK0_DTO_PHASE, phase,
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
215
uint32_t modulo, phase;
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
219
phase = req_dtbclk_khz * 1000;
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
222
REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], phase);
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c
214
uint32_t modulo, phase;
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c
218
phase = req_dtbclk_khz * 1000;
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c
221
REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], phase);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1285
int modulo, phase;
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1289
phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk;
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1291
if (phase > 0xff) {
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1293
phase = 0xff;
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1298
DPPCLK0_DTO_PHASE, phase,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1499
uint32_t modulo, phase;
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1518
phase = req_dtbclk_khz * 1000;
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1521
REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], phase);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1541
params->ref_dtbclk_khz, req_dtbclk_khz, phase, modulo);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2477
int modulo, phase;
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2481
phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk;
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2483
if (phase > 0xff) {
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2485
phase = 0xff;
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2493
DPPCLK0_DTO_PHASE, phase,
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2626
uint32_t modulo, phase;
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2632
phase = req_dtbclk_khz * 1000;
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2635
REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], phase);
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
84
int modulo, phase;
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
88
phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk;
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
90
if (phase > 0xff) {
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
92
phase = 0xff;
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
96
DPPCLK0_DTO_PHASE, phase,
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
224
int phase, pair;
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
241
for (phase = 0; phase < phases_to_program; phase++) {
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
250
SCL_C_RAM_PHASE, phase,
drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c
289
int i, phase, pair;
drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c
319
for (phase = 0; phase < phases_to_program; phase++) {
drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c
322
set_reg_field_value(select, phase, SCLV_COEF_RAM_SELECT, SCL_C_RAM_PHASE);
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c
689
int phase;
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c
696
for (phase = 0; phase < (NUM_PHASES / 2 + 1); phase++) {
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c
698
even_coef = filter[phase * taps + 2 * pair];
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c
700
odd_coef = filter[phase * taps + 2 * pair + 1];
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c
706
WBSCL_COEF_RAM_PHASE, phase,
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
247
int phase;
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
256
for (phase = 0; phase < (NUM_PHASES / 2 + 1); phase++) {
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
258
even_coef = filter[phase * taps + 2 * pair];
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
260
odd_coef = filter[phase * taps + 2 * pair + 1];
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
245
int phase;
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
254
for (phase = 0; phase < (NUM_PHASES / 2 + 1); phase++) {
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
256
even_coef = filter[phase * taps + 2 * pair];
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
258
odd_coef = filter[phase * taps + 2 * pair + 1];
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2434
uint64_t phase[MAX_PIPES];
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2472
phase[i] = embedded_pix_clk_100hz*(uint64_t)100;
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2476
phase[i] = (uint64_t)embedded_pix_clk_100hz*
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2479
phase[i] = div_u64(phase[i], get_clock_divider(grouped_pipes[i], true));
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2484
if (reduceSizeAndFraction(&phase[i],
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2501
(unsigned int)phase[i], (unsigned int)modulo[i]);
drivers/gpu/drm/arm/malidp_crtc.c
272
u32 phase;
drivers/gpu/drm/arm/malidp_crtc.c
303
phase = s->input_w;
drivers/gpu/drm/arm/malidp_crtc.c
305
((phase << SE_N_PHASE) / s->output_w + 1) / 2;
drivers/gpu/drm/arm/malidp_crtc.c
307
phase = s->input_w;
drivers/gpu/drm/arm/malidp_crtc.c
308
phase <<= (SE_SHIFT_N_PHASE + SE_N_PHASE);
drivers/gpu/drm/arm/malidp_crtc.c
309
s->h_delta_phase = phase / s->output_w;
drivers/gpu/drm/arm/malidp_crtc.c
312
phase = s->input_h;
drivers/gpu/drm/arm/malidp_crtc.c
314
((phase << SE_N_PHASE) / s->output_h + 1) / 2;
drivers/gpu/drm/arm/malidp_crtc.c
316
phase = s->input_h;
drivers/gpu/drm/arm/malidp_crtc.c
317
phase <<= (SE_SHIFT_N_PHASE + SE_N_PHASE);
drivers/gpu/drm/arm/malidp_crtc.c
318
s->v_delta_phase = phase / s->output_h;
drivers/gpu/drm/i915/display/skl_scaler.c
62
int phase = -0x8000;
drivers/gpu/drm/i915/display/skl_scaler.c
66
phase += (sub - 1) * 0x8000 / sub;
drivers/gpu/drm/i915/display/skl_scaler.c
68
phase += scale / (2 * sub);
drivers/gpu/drm/i915/display/skl_scaler.c
75
WARN_ON(phase < -0x8000 || phase > 0x18000);
drivers/gpu/drm/i915/display/skl_scaler.c
77
if (phase < 0)
drivers/gpu/drm/i915/display/skl_scaler.c
78
phase = 0x10000 + phase;
drivers/gpu/drm/i915/display/skl_scaler.c
82
return ((phase >> 2) & PS_PHASE_MASK) | trip;
drivers/gpu/drm/i915/gem/i915_gem_pm.c
143
}, **phase;
drivers/gpu/drm/i915/gem/i915_gem_pm.c
176
for (phase = phases; *phase; phase++) {
drivers/gpu/drm/i915/gem/i915_gem_pm.c
177
list_for_each_entry(obj, *phase, mm.link) {
drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
120
}, *phase;
drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
178
for (phase = phases; phase->list; phase++) {
drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
183
if ((shrink & phase->bit) == 0)
drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
197
(obj = list_first_entry_or_null(phase->list,
drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
244
list_splice_tail(&still_in_list, phase->list);
drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
1349
} *phase, phases[] = {
drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
1360
for (i = 0, phase = phases; ret == 0 && i < ARRAY_SIZE(phases);
drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
1361
i++, phase++)
drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
1362
ret = __igt_ctx_sseu(arg, phase->name, phase->flags);
drivers/gpu/drm/i915/gt/selftest_execlists.c
3645
const unsigned int phase[] = { 0, BATCH };
drivers/gpu/drm/i915/gt/selftest_execlists.c
3684
for (n = 0; n < ARRAY_SIZE(phase); n++) {
drivers/gpu/drm/i915/gt/selftest_execlists.c
3685
err = smoke_crescendo(&smoke, phase[n]);
drivers/gpu/drm/i915/gt/selftest_execlists.c
3689
err = smoke_random(&smoke, phase[n]);
drivers/gpu/drm/i915/gvt/edid.c
139
vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;
drivers/gpu/drm/i915/gvt/edid.c
168
vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;
drivers/gpu/drm/i915/gvt/edid.c
254
i2c_edid->gmbus.phase = GMBUS_IDLE_PHASE;
drivers/gpu/drm/i915/gvt/edid.c
266
i2c_edid->gmbus.phase = GMBUS_DATA_PHASE;
drivers/gpu/drm/i915/gvt/edid.c
325
i2c_edid->gmbus.phase = GMBUS_IDLE_PHASE;
drivers/gpu/drm/i915/gvt/edid.c
330
i2c_edid->gmbus.phase = GMBUS_WAIT_PHASE;
drivers/gpu/drm/i915/gvt/edid.h
104
enum gvt_gmbus_phase phase;
drivers/gpu/drm/i915/selftests/i915_syncmap.c
547
unsigned long count, phase, i;
drivers/gpu/drm/i915/selftests/i915_syncmap.c
560
phase = jiffies + HZ/100 + 1;
drivers/gpu/drm/i915/selftests/i915_syncmap.c
569
} while (!time_after(jiffies, phase));
drivers/gpu/drm/i915/selftests/i915_syncmap.c
572
phase = 0;
drivers/gpu/drm/i915/selftests/i915_syncmap.c
596
phase++;
drivers/gpu/drm/i915/selftests/i915_syncmap.c
598
pr_debug("Completed %lu passes, each of %lu contexts\n", phase, count);
drivers/gpu/drm/imx/dcss/dcss-scaler.c
179
int phase;
drivers/gpu/drm/imx/dcss/dcss-scaler.c
184
for (phase = 0; phase < PSC_STORED_PHASES; phase++) {
drivers/gpu/drm/imx/dcss/dcss-scaler.c
185
coef[phase][0] = 0;
drivers/gpu/drm/imx/dcss/dcss-scaler.c
186
coef[phase][PSC_NUM_TAPS - 1] = 0;
drivers/gpu/drm/imx/dcss/dcss-scaler.c
233
for (phase = 0; phase < PSC_STORED_PHASES; phase++) {
drivers/gpu/drm/imx/dcss/dcss-scaler.c
238
sum += coef[phase][i];
drivers/gpu/drm/imx/dcss/dcss-scaler.c
240
ll_temp = coef[phase][i];
drivers/gpu/drm/imx/dcss/dcss-scaler.c
244
coef[phase][i] = (int)ll_temp;
drivers/gpu/drm/imx/dcss/dcss-scaler.c
577
int i, phase;
drivers/gpu/drm/imx/dcss/dcss-scaler.c
593
for (phase = (PSC_NUM_PHASES >> 1) - 1;
drivers/gpu/drm/imx/dcss/dcss-scaler.c
594
i < PSC_NUM_PHASES; i++, phase--) {
drivers/gpu/drm/imx/dcss/dcss-scaler.c
595
dcss_scaler_write(ch, ((coef[phase][5] & 0xfff) << 16 |
drivers/gpu/drm/imx/dcss/dcss-scaler.c
596
(coef[phase][4] & 0xfff) << 4 |
drivers/gpu/drm/imx/dcss/dcss-scaler.c
597
(coef[phase][3] & 0xf00) >> 8),
drivers/gpu/drm/imx/dcss/dcss-scaler.c
599
dcss_scaler_write(ch, ((coef[phase][3] & 0x0ff) << 20 |
drivers/gpu/drm/imx/dcss/dcss-scaler.c
600
(coef[phase][2] & 0xfff) << 8 |
drivers/gpu/drm/imx/dcss/dcss-scaler.c
601
(coef[phase][1] & 0xff0) >> 4),
drivers/gpu/drm/imx/dcss/dcss-scaler.c
603
dcss_scaler_write(ch, ((coef[phase][1] & 0x00f) << 24),
drivers/gpu/drm/imx/dcss/dcss-scaler.c
612
int i, phase;
drivers/gpu/drm/imx/dcss/dcss-scaler.c
630
for (phase = (PSC_NUM_PHASES >> 1) - 1;
drivers/gpu/drm/imx/dcss/dcss-scaler.c
631
i < PSC_NUM_PHASES; i++, phase--) {
drivers/gpu/drm/imx/dcss/dcss-scaler.c
632
dcss_scaler_write(ch, ((coef[phase][6] & 0xfff) << 16 |
drivers/gpu/drm/imx/dcss/dcss-scaler.c
633
(coef[phase][5] & 0xfff) << 4 |
drivers/gpu/drm/imx/dcss/dcss-scaler.c
634
(coef[phase][4] & 0xf00) >> 8),
drivers/gpu/drm/imx/dcss/dcss-scaler.c
636
dcss_scaler_write(ch, ((coef[phase][4] & 0x0ff) << 20 |
drivers/gpu/drm/imx/dcss/dcss-scaler.c
637
(coef[phase][3] & 0xfff) << 8 |
drivers/gpu/drm/imx/dcss/dcss-scaler.c
638
(coef[phase][2] & 0xff0) >> 4),
drivers/gpu/drm/imx/dcss/dcss-scaler.c
640
dcss_scaler_write(ch, ((coef[phase][2] & 0x00f) << 24 |
drivers/gpu/drm/imx/dcss/dcss-scaler.c
641
(coef[phase][1] & 0xfff) << 12 |
drivers/gpu/drm/imx/dcss/dcss-scaler.c
642
(coef[phase][0] & 0xfff)),
drivers/gpu/drm/meson/meson_overlay.c
201
static void meson_overlay_get_vertical_phase(unsigned int ratio_y, int *phase,
drivers/gpu/drm/meson/meson_overlay.c
216
*phase = (offset_out - offset_in) >> 2;
drivers/gpu/drm/meson/meson_overlay.c
218
if (*phase > 0x100)
drivers/gpu/drm/meson/meson_overlay.c
221
*phase = *phase & 0xff;
drivers/gpu/drm/sun4i/sun4i_tcon.h
115
#define SUN4I_TCON0_IO_POL_DCLK_PHASE(phase) ((phase & 3) << 28)
drivers/gpu/drm/tegra/nvdec.c
101
dev_err(nvdec->dev, "failed to boot %s, debuginfo=0x%x\n", phase, val);
drivers/gpu/drm/tegra/nvdec.c
94
static int nvdec_wait_debuginfo(struct nvdec *nvdec, const char *phase)
drivers/gpu/drm/tidss/tidss_dispc.c
1769
int phase;
drivers/gpu/drm/tidss/tidss_dispc.c
1776
for (phase = 0; phase <= 8; ++phase) {
drivers/gpu/drm/tidss/tidss_dispc.c
1777
u16 reg = c0_base + phase * 4;
drivers/gpu/drm/tidss/tidss_dispc.c
1778
u16 c0 = coefs->c0[phase];
drivers/gpu/drm/tidss/tidss_dispc.c
1783
for (phase = 0; phase <= 15; ++phase) {
drivers/gpu/drm/tidss/tidss_dispc.c
1784
u16 reg = c12_base + phase * 4;
drivers/gpu/drm/tidss/tidss_dispc.c
1788
c1 = coefs->c1[phase];
drivers/gpu/drm/tidss/tidss_dispc.c
1789
c2 = coefs->c2[phase];
drivers/gpu/drm/tidss/tidss_dispc_regs.h
148
#define DISPC_VID_FIR_COEF_H0(phase) (0x6c + (phase) * 4)
drivers/gpu/drm/tidss/tidss_dispc_regs.h
150
#define DISPC_VID_FIR_COEF_H0_C(phase) (0x90 + (phase) * 4)
drivers/gpu/drm/tidss/tidss_dispc_regs.h
153
#define DISPC_VID_FIR_COEF_H12(phase) (0xb4 + (phase) * 4)
drivers/gpu/drm/tidss/tidss_dispc_regs.h
155
#define DISPC_VID_FIR_COEF_H12_C(phase) (0xf4 + (phase) * 4)
drivers/gpu/drm/tidss/tidss_dispc_regs.h
158
#define DISPC_VID_FIR_COEF_V0(phase) (0x134 + (phase) * 4)
drivers/gpu/drm/tidss/tidss_dispc_regs.h
160
#define DISPC_VID_FIR_COEF_V0_C(phase) (0x158 + (phase) * 4)
drivers/gpu/drm/tidss/tidss_dispc_regs.h
163
#define DISPC_VID_FIR_COEF_V12(phase) (0x17c + (phase) * 4)
drivers/gpu/drm/tidss/tidss_dispc_regs.h
165
#define DISPC_VID_FIR_COEF_V12_C(phase) (0x1bc + (phase) * 4)
drivers/gpu/drm/vc4/vc4_plane.c
603
s32 phase;
drivers/gpu/drm/vc4/vc4_plane.c
640
phase = offset + (offset2 >> 1);
drivers/gpu/drm/vc4/vc4_plane.c
643
if (phase >= 1 << PHASE_BITS)
drivers/gpu/drm/vc4/vc4_plane.c
644
phase = (1 << PHASE_BITS) - 1;
drivers/gpu/drm/vc4/vc4_plane.c
646
phase &= SCALER_PPF_IPHASE_MASK;
drivers/gpu/drm/vc4/vc4_plane.c
656
VC4_SET_FIELD(phase, SCALER_PPF_IPHASE));
drivers/greybus/arpc.h
60
__u8 phase;
drivers/greybus/connection.c
531
u8 phase)
drivers/greybus/connection.c
545
req->phase = phase;
drivers/greybus/connection.c
555
u8 phase)
drivers/greybus/connection.c
568
ret = drv->cport_shutdown(hd, connection->hd_cport_id, phase,
drivers/greybus/connection.c
571
ret = gb_connection_shutdown_operation(connection, phase);
drivers/greybus/connection.c
576
connection->name, phase, ret);
drivers/greybus/es2.c
621
u8 phase, unsigned int timeout)
drivers/greybus/es2.c
634
req.phase = phase;
drivers/hid/hid-logitech-hidpp.c
2628
params[12] = effect->u.periodic.phase >> 8;
drivers/hid/hid-logitech-hidpp.c
2629
params[13] = effect->u.periodic.phase & 255;
drivers/hid/hid-logitech-hidpp.c
2641
effect->u.periodic.phase);
drivers/hid/usbhid/hid-pidff.c
582
pidff_set(&pidff->set_periodic[PID_PHASE], effect->u.periodic.phase);
drivers/hid/usbhid/hid-pidff.c
598
effect->u.periodic.phase != old->u.periodic.phase ||
drivers/hwmon/pmbus/adm1275.c
259
int phase, int reg)
drivers/hwmon/pmbus/aps-379.c
47
static int aps_379_read_word_data(struct i2c_client *client, int page, int phase, int reg)
drivers/hwmon/pmbus/bpa-rs600.c
88
static int bpa_rs600_read_word_data(struct i2c_client *client, int page, int phase, int reg)
drivers/hwmon/pmbus/delta-ahe50dc-fan.c
32
static int ahe50dc_fan_read_word_data(struct i2c_client *client, int page, int phase, int reg)
drivers/hwmon/pmbus/dps920ab.c
20
static int dps920ab_read_word_data(struct i2c_client *client, int page, int phase, int reg)
drivers/hwmon/pmbus/dps920ab.c
46
return pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/fsp-3y.c
125
static int fsp3y_read_word_data(struct i2c_client *client, int page, int phase, int reg)
drivers/hwmon/pmbus/hac300s.c
48
int phase, int reg)
drivers/hwmon/pmbus/hac300s.c
60
rv = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/ibm-cffps.c
309
int phase, int reg)
drivers/hwmon/pmbus/ibm-cffps.c
315
rc = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/ibm-cffps.c
332
rc = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/ina233.c
63
int phase, int reg)
drivers/hwmon/pmbus/ir35221.c
25
int phase, int reg)
drivers/hwmon/pmbus/ir35221.c
31
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/ir35221.c
35
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/ir35221.c
39
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/ir35221.c
43
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/ir35221.c
47
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/ir35221.c
51
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/ir35221.c
55
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/ir35221.c
59
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/isl68137.c
152
int phase, int reg)
drivers/hwmon/pmbus/isl68137.c
161
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/isl68137.c
172
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/lm25066.c
239
int phase, int reg)
drivers/hwmon/pmbus/lm25066.c
324
int phase, int reg)
drivers/hwmon/pmbus/lm25066.c
346
ret = lm25066_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/lt3074.c
25
int phase, int reg)
drivers/hwmon/pmbus/lt3074.c
29
return pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/lt3074.c
32
return pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/lt3074.c
35
return pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/lt7182s.c
35
static int lt7182s_read_word_data(struct i2c_client *client, int page, int phase, int reg)
drivers/hwmon/pmbus/lt7182s.c
42
ret = pmbus_read_word_data(client, page, phase, MFR_READ_ITH);
drivers/hwmon/pmbus/lt7182s.c
44
ret = pmbus_read_word_data(client, 0, phase, MFR_READ_EXTVCC);
drivers/hwmon/pmbus/lt7182s.c
47
ret = pmbus_read_word_data(client, page, phase, MFR_IOUT_PEAK);
drivers/hwmon/pmbus/lt7182s.c
50
ret = pmbus_read_word_data(client, page, phase, MFR_VOUT_PEAK);
drivers/hwmon/pmbus/lt7182s.c
53
ret = pmbus_read_word_data(client, page, phase, MFR_VIN_PEAK);
drivers/hwmon/pmbus/lt7182s.c
56
ret = pmbus_read_word_data(client, page, phase, MFR_TEMPERATURE_1_PEAK);
drivers/hwmon/pmbus/ltc2978.c
181
static int ltc_read_word_data(struct i2c_client *client, int page, int phase,
drivers/hwmon/pmbus/ltc2978.c
313
int phase, int reg)
drivers/hwmon/pmbus/ltc2978.c
325
ret = ltc_read_word_data(client, page, phase,
drivers/hwmon/pmbus/ltc2978.c
360
int phase, int reg)
drivers/hwmon/pmbus/ltc2978.c
379
ret = ltc2978_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/ltc2978.c
386
int phase, int reg)
drivers/hwmon/pmbus/ltc2978.c
414
ret = ltc2978_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/ltc2978.c
421
int phase, int reg)
drivers/hwmon/pmbus/ltc2978.c
454
int phase, int reg)
drivers/hwmon/pmbus/ltc2978.c
469
ret = ltc3880_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/ltc3815.c
73
int phase, int reg)
drivers/hwmon/pmbus/ltc3815.c
79
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/ltc3815.c
83
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/ltc3815.c
87
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/ltc3815.c
91
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/ltc3815.c
95
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/lx1308.c
26
int phase, int reg)
drivers/hwmon/pmbus/max16064.c
19
int phase, int reg)
drivers/hwmon/pmbus/max16064.c
25
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/max16064.c
29
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/max16601.c
71
static int max16601_read_word(struct i2c_client *client, int page, int phase,
drivers/hwmon/pmbus/max16601.c
81
if (phase == 0xff)
drivers/hwmon/pmbus/max16601.c
88
phase);
drivers/hwmon/pmbus/max20730.c
447
int phase, int reg)
drivers/hwmon/pmbus/max20730.c
473
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/max31785.c
193
int phase, int reg)
drivers/hwmon/pmbus/max34440.c
119
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/max34440.c
123
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/max34440.c
131
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/max34440.c
135
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/max34440.c
141
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/max34440.c
147
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/max34440.c
154
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/max34440.c
158
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/max34440.c
76
int phase, int reg)
drivers/hwmon/pmbus/max34440.c
84
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/max34440.c
88
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/max8688.c
32
int phase, int reg)
drivers/hwmon/pmbus/mp2856.c
112
mp2856_read_word_helper(struct i2c_client *client, int page, int phase, u8 reg,
drivers/hwmon/pmbus/mp2856.c
115
int ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp2856.c
122
int phase, u8 reg)
drivers/hwmon/pmbus/mp2856.c
126
ret = mp2856_read_word_helper(client, page, phase, reg,
drivers/hwmon/pmbus/mp2856.c
140
int page, int phase, u8 reg)
drivers/hwmon/pmbus/mp2856.c
145
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp2856.c
149
if (!((phase + 1) % MP2856_PAGE_NUM))
drivers/hwmon/pmbus/mp2856.c
163
int page, int phase)
drivers/hwmon/pmbus/mp2856.c
168
switch (phase) {
drivers/hwmon/pmbus/mp2856.c
170
ret = mp2856_read_phase(client, data, page, phase,
drivers/hwmon/pmbus/mp2856.c
174
ret = mp2856_read_phase(client, data, page, phase,
drivers/hwmon/pmbus/mp2856.c
178
ret = mp2856_read_phase(client, data, page, phase,
drivers/hwmon/pmbus/mp2856.c
182
ret = mp2856_read_phase(client, data, page, phase,
drivers/hwmon/pmbus/mp2856.c
189
switch (phase) {
drivers/hwmon/pmbus/mp2856.c
191
ret = mp2856_read_phase(client, data, page, phase,
drivers/hwmon/pmbus/mp2856.c
195
ret = mp2856_read_phase(client, data, page, phase,
drivers/hwmon/pmbus/mp2856.c
207
int phase, int reg)
drivers/hwmon/pmbus/mp2856.c
215
ret = mp2856_read_vout(client, data, page, phase, reg);
drivers/hwmon/pmbus/mp2856.c
218
if (phase != 0xff)
drivers/hwmon/pmbus/mp2856.c
219
ret = mp2856_read_phases(client, data, page, phase);
drivers/hwmon/pmbus/mp2856.c
221
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp2869.c
232
static int mp2869_read_word_data(struct i2c_client *client, int page, int phase,
drivers/hwmon/pmbus/mp2869.c
249
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp2869.c
269
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp2869.c
280
ret = pmbus_read_word_data(client, page, phase, MFR_READ_IIN_EST);
drivers/hwmon/pmbus/mp2869.c
293
ret = pmbus_read_word_data(client, page, phase, MFR_READ_PIN_EST);
drivers/hwmon/pmbus/mp2869.c
300
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp2869.c
308
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp2869.c
322
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp2869.c
329
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp2869.c
336
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp2869.c
347
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp2869.c
363
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp2869.c
370
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp2869.c
378
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp2869.c
386
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp2869.c
394
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp2888.c
102
if (!((phase + 1) % 2))
drivers/hwmon/pmbus/mp2888.c
128
mp2888_read_phases(struct i2c_client *client, struct mp2888_data *data, int page, int phase)
drivers/hwmon/pmbus/mp2888.c
132
switch (phase) {
drivers/hwmon/pmbus/mp2888.c
134
ret = mp2888_read_phase(client, data, page, phase, MP2888_MFR_READ_CS1_2);
drivers/hwmon/pmbus/mp2888.c
137
ret = mp2888_read_phase(client, data, page, phase, MP2888_MFR_READ_CS3_4);
drivers/hwmon/pmbus/mp2888.c
140
ret = mp2888_read_phase(client, data, page, phase, MP2888_MFR_READ_CS5_6);
drivers/hwmon/pmbus/mp2888.c
143
ret = mp2888_read_phase(client, data, page, phase, MP2888_MFR_READ_CS7_8);
drivers/hwmon/pmbus/mp2888.c
146
ret = mp2888_read_phase(client, data, page, phase, MP2888_MFR_READ_CS9_10);
drivers/hwmon/pmbus/mp2888.c
154
static int mp2888_read_word_data(struct i2c_client *client, int page, int phase, int reg)
drivers/hwmon/pmbus/mp2888.c
162
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp2888.c
174
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp2888.c
184
if (phase != 0xff)
drivers/hwmon/pmbus/mp2888.c
185
return mp2888_read_phases(client, data, page, phase);
drivers/hwmon/pmbus/mp2888.c
187
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp2888.c
198
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp2888.c
211
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp2888.c
217
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp2888.c
94
mp2888_read_phase(struct i2c_client *client, struct mp2888_data *data, int page, int phase, u8 reg)
drivers/hwmon/pmbus/mp2888.c
98
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp2891.c
222
int phase, int reg)
drivers/hwmon/pmbus/mp2891.c
230
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp2891.c
245
ret = pmbus_read_word_data(client, page, phase, READ_IIN_EST);
drivers/hwmon/pmbus/mp2891.c
261
ret = pmbus_read_word_data(client, page, phase, READ_PIN_EST);
drivers/hwmon/pmbus/mp2891.c
274
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp2891.c
282
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp2891.c
289
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp2891.c
302
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp2891.c
314
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp2891.c
321
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp2891.c
334
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp2891.c
346
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp2891.c
359
ret = pmbus_read_word_data(client, 0, phase, reg);
drivers/hwmon/pmbus/mp2891.c
371
ret = pmbus_read_word_data(client, 0, phase, reg);
drivers/hwmon/pmbus/mp2925.c
110
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp2925.c
85
static int mp2925_read_word_data(struct i2c_client *client, int page, int phase,
drivers/hwmon/pmbus/mp2925.c
94
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp29502.c
289
int phase, int reg)
drivers/hwmon/pmbus/mp29502.c
306
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp29502.c
317
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp29502.c
335
ret = pmbus_read_word_data(client, page, phase, MFR_READ_IIN_EST);
drivers/hwmon/pmbus/mp29502.c
349
ret = pmbus_read_word_data(client, page, phase, MFR_READ_PIN_EST);
drivers/hwmon/pmbus/mp29502.c
363
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp29502.c
373
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp29502.c
381
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp29502.c
393
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp29502.c
407
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp29502.c
424
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp29502.c
437
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp29502.c
452
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp2975.c
142
mp2975_read_word_helper(struct i2c_client *client, int page, int phase, u8 reg,
drivers/hwmon/pmbus/mp2975.c
145
int ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp2975.c
209
int page, int phase, u8 reg)
drivers/hwmon/pmbus/mp2975.c
213
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp2975.c
217
if (!((phase + 1) % MP2975_PAGE_NUM))
drivers/hwmon/pmbus/mp2975.c
240
ret = pmbus_read_word_data(client, page, phase, PMBUS_READ_IOUT);
drivers/hwmon/pmbus/mp2975.c
250
int page, int phase)
drivers/hwmon/pmbus/mp2975.c
255
switch (phase) {
drivers/hwmon/pmbus/mp2975.c
257
ret = mp2975_read_phase(client, data, page, phase,
drivers/hwmon/pmbus/mp2975.c
261
ret = mp2975_read_phase(client, data, page, phase,
drivers/hwmon/pmbus/mp2975.c
265
ret = mp2975_read_phase(client, data, page, phase,
drivers/hwmon/pmbus/mp2975.c
272
switch (phase) {
drivers/hwmon/pmbus/mp2975.c
274
ret = mp2975_read_phase(client, data, page, phase,
drivers/hwmon/pmbus/mp2975.c
278
ret = mp2975_read_phase(client, data, page, phase,
drivers/hwmon/pmbus/mp2975.c
282
ret = mp2975_read_phase(client, data, page, phase,
drivers/hwmon/pmbus/mp2975.c
286
ret = mp2975_read_phase(client, data, page, phase,
drivers/hwmon/pmbus/mp2975.c
290
ret = mp2975_read_phase(client, data, page, phase,
drivers/hwmon/pmbus/mp2975.c
294
ret = mp2975_read_phase(client, data, page, phase,
drivers/hwmon/pmbus/mp2975.c
305
int phase, int reg)
drivers/hwmon/pmbus/mp2975.c
314
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp2975.c
320
ret = mp2975_read_word_helper(client, page, phase, reg,
drivers/hwmon/pmbus/mp2975.c
324
ret = mp2975_read_word_helper(client, page, phase, reg,
drivers/hwmon/pmbus/mp2975.c
335
ret = mp2975_read_word_helper(client, page, phase,
drivers/hwmon/pmbus/mp2975.c
344
ret = mp2975_read_word_helper(client, page, phase, reg,
drivers/hwmon/pmbus/mp2975.c
351
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/mp2975.c
355
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/mp2975.c
359
ret = mp2975_read_word_helper(client, page, phase,
drivers/hwmon/pmbus/mp2975.c
469
int phase, int reg)
drivers/hwmon/pmbus/mp2975.c
477
ret = mp2975_read_word_helper(client, page, phase, reg,
drivers/hwmon/pmbus/mp2975.c
481
ret = mp2975_read_word_helper(client, page, phase, reg,
drivers/hwmon/pmbus/mp2975.c
495
ret = mp2975_read_word_helper(client, page, phase,
drivers/hwmon/pmbus/mp2975.c
505
ret = mp2975_read_word_helper(client, page, phase,
drivers/hwmon/pmbus/mp2975.c
515
ret = mp2975_read_word_helper(client, page, phase,
drivers/hwmon/pmbus/mp2975.c
524
ret = mp2975_read_word_helper(client, page, phase,
drivers/hwmon/pmbus/mp2975.c
533
ret = mp2975_read_phases(client, data, page, phase);
drivers/hwmon/pmbus/mp2985.c
106
static int mp2985_read_word_data(struct i2c_client *client, int page, int phase,
drivers/hwmon/pmbus/mp2985.c
115
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp2985.c
138
ret = pmbus_read_word_data(client, page, phase, READ_IIN_EST);
drivers/hwmon/pmbus/mp2985.c
147
ret = pmbus_read_word_data(client, page, phase, READ_PIN_EST);
drivers/hwmon/pmbus/mp2985.c
151
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp2993.c
100
ret = pmbus_read_word_data(client, 0, phase, reg);
drivers/hwmon/pmbus/mp2993.c
104
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp2993.c
116
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp2993.c
78
static int mp2993_read_word_data(struct i2c_client *client, int page, int phase,
drivers/hwmon/pmbus/mp2993.c
86
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp5926.c
60
static int mp5926_read_word_data(struct i2c_client *client, int page, int phase,
drivers/hwmon/pmbus/mp5926.c
69
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp5990.c
56
int phase, int reg)
drivers/hwmon/pmbus/mp5990.c
65
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp9941.c
144
static int mp9941_read_word_data(struct i2c_client *client, int page, int phase,
drivers/hwmon/pmbus/mp9941.c
154
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp9941.c
162
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp9941.c
170
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp9941.c
178
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp9941.c
193
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/mp9945.c
94
static int mp9945_read_word_data(struct i2c_client *client, int page, int phase,
drivers/hwmon/pmbus/mpq7932.c
76
int phase, int reg)
drivers/hwmon/pmbus/mpq8785.c
78
int phase, int reg)
drivers/hwmon/pmbus/mpq8785.c
82
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/pim4328.c
55
int phase, int reg)
drivers/hwmon/pmbus/pim4328.c
62
if (phase == 0xff)
drivers/hwmon/pmbus/pim4328.c
67
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/pim4328.c
68
phase == 0 ? PIM4328_MFR_READ_VINA
drivers/hwmon/pmbus/pim4328.c
72
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/pim4328.c
73
phase == 0 ? PIM4328_MFR_READ_IINA
drivers/hwmon/pmbus/pli1209bc.c
26
int phase, int reg)
drivers/hwmon/pmbus/pli1209bc.c
33
data = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/pli1209bc.c
45
data = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/pli1209bc.c
51
return pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/pm6764tr.c
16
static int pm6764tr_read_word_data(struct i2c_client *client, int page, int phase, int reg)
drivers/hwmon/pmbus/pm6764tr.c
22
ret = pmbus_read_word_data(client, page, phase, PM6764TR_PMBUS_READ_VOUT);
drivers/hwmon/pmbus/pmbus.h
459
int (*read_word_data)(struct i2c_client *client, int page, int phase,
drivers/hwmon/pmbus/pmbus.h
551
int pmbus_set_page(struct i2c_client *client, int page, int phase);
drivers/hwmon/pmbus/pmbus.h
552
int pmbus_read_word_data(struct i2c_client *client, int page, int phase,
drivers/hwmon/pmbus/pmbus_core.c
1433
int seq, int page, int phase,
drivers/hwmon/pmbus/pmbus_core.c
1458
sensor->phase = phase;
drivers/hwmon/pmbus/pmbus_core.c
1484
const char *lstring, int index, int phase)
drivers/hwmon/pmbus/pmbus_core.c
1497
if (phase == 0xff)
drivers/hwmon/pmbus/pmbus_core.c
1501
lstring, phase);
drivers/hwmon/pmbus/pmbus_core.c
1503
if (phase == 0xff)
drivers/hwmon/pmbus/pmbus_core.c
1508
lstring, index, phase);
drivers/hwmon/pmbus/pmbus_core.c
1602
int index, int page, int phase,
drivers/hwmon/pmbus/pmbus_core.c
1612
paged ? page + 1 : 0, phase);
drivers/hwmon/pmbus/pmbus_core.c
1616
base = pmbus_add_sensor(data, name, "input", index, page, phase,
drivers/hwmon/pmbus/pmbus_core.c
1621
if (attr->sfunc && phase == 0xff) {
drivers/hwmon/pmbus/pmbus_core.c
1696
int phase;
drivers/hwmon/pmbus/pmbus_core.c
1698
for (phase = 0; phase < info->phases[page];
drivers/hwmon/pmbus/pmbus_core.c
1699
phase++) {
drivers/hwmon/pmbus/pmbus_core.c
1700
if (!(info->pfunc[phase] & attrs->func))
drivers/hwmon/pmbus/pmbus_core.c
1704
phase, attrs, paged);
drivers/hwmon/pmbus/pmbus_core.c
208
int pmbus_set_page(struct i2c_client *client, int page, int phase)
drivers/hwmon/pmbus/pmbus_core.c
235
if (data->info->phases[page] && data->currphase != phase &&
drivers/hwmon/pmbus/pmbus_core.c
239
phase);
drivers/hwmon/pmbus/pmbus_core.c
244
data->currphase = phase;
drivers/hwmon/pmbus/pmbus_core.c
406
int pmbus_read_word_data(struct i2c_client *client, int page, int phase, u8 reg)
drivers/hwmon/pmbus/pmbus_core.c
410
rv = pmbus_set_page(client, page, phase);
drivers/hwmon/pmbus/pmbus_core.c
445
int phase, int reg)
drivers/hwmon/pmbus/pmbus_core.c
452
status = info->read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/pmbus_core.c
460
return pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/pmbus_core.c
50
u8 phase; /* phase number, 0xff for all phases */
drivers/hwmon/pmbus/pmbus_core.c
720
sensor->phase, sensor->reg);
drivers/hwmon/pmbus/stpddc60.c
110
int phase, int reg)
drivers/hwmon/pmbus/stpddc60.c
119
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/stpddc60.c
127
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/tps25990.c
103
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/tps25990.c
108
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/tps25990.c
113
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/tps25990.c
118
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/tps25990.c
123
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/tps25990.c
128
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/tps25990.c
133
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/tps25990.c
138
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/tps25990.c
143
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/tps25990.c
148
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/tps25990.c
153
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/tps25990.c
158
ret = pmbus_read_word_data(client, page, phase,
drivers/hwmon/pmbus/tps25990.c
177
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/tps25990.c
184
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/tps25990.c
97
int page, int phase, int reg)
drivers/hwmon/pmbus/tps53679.c
208
int phase, int reg)
drivers/hwmon/pmbus/tps53679.c
220
if (reg == PMBUS_READ_IOUT && page == 0 && phase == 0xff)
drivers/hwmon/pmbus/xdpe12284.c
24
int phase, int reg)
drivers/hwmon/pmbus/xdpe12284.c
35
ret = pmbus_read_word_data(client, page, phase, reg);
drivers/hwmon/pmbus/zl6100.c
124
int phase, int reg)
drivers/hwmon/pmbus/zl6100.c
165
ret = pmbus_read_word_data(client, page, phase, vreg);
drivers/iio/adc/ad9467.c
712
unsigned int phase = AN877_ADC_OUTPUT_EVEN_ODD_MODE_EN;
drivers/iio/adc/ad9467.c
715
phase |= AN877_ADC_INVERT_DCO_CLK;
drivers/iio/adc/ad9467.c
718
phase);
drivers/iio/dac/adi-axi-dac.c
269
u32 reg, raw, phase;
drivers/iio/dac/adi-axi-dac.c
285
phase = DIV_ROUND_CLOSEST_ULL((u64)raw * AXI_DAC_2_PI_MEGA, U16_MAX);
drivers/iio/dac/adi-axi-dac.c
287
vals[0] = phase / MEGA;
drivers/iio/dac/adi-axi-dac.c
288
vals[1] = phase % MEGA;
drivers/iio/dac/adi-axi-dac.c
398
int integer, frac, phase;
drivers/iio/dac/adi-axi-dac.c
409
phase = integer * MEGA + frac;
drivers/iio/dac/adi-axi-dac.c
410
if (phase < 0 || phase > AXI_DAC_2_PI_MEGA)
drivers/iio/dac/adi-axi-dac.c
413
raw = DIV_ROUND_CLOSEST_ULL((u64)phase * U16_MAX, AXI_DAC_2_PI_MEGA);
drivers/iio/dac/ltc2688.c
546
unsigned int phase)
drivers/iio/dac/ltc2688.c
553
FIELD_PREP(LTC2688_CH_DIT_PH_MSK, phase));
drivers/infiniband/hw/bnxt_re/ib_verbs.c
3569
resp.phase = cq->qplib_cq.period;
drivers/infiniband/hw/efa/efa_com.c
1212
u8 phase;
drivers/infiniband/hw/efa/efa_com.c
1216
phase = eeq->phase;
drivers/infiniband/hw/efa/efa_com.c
1220
while ((READ_ONCE(eqe->common) & EFA_ADMIN_EQE_PHASE_MASK) == phase) {
drivers/infiniband/hw/efa/efa_com.c
1235
phase = !phase;
drivers/infiniband/hw/efa/efa_com.c
1242
eeq->phase = phase;
drivers/infiniband/hw/efa/efa_com.c
1283
eeq->phase = 1;
drivers/infiniband/hw/efa/efa_com.c
155
sq->phase = 1;
drivers/infiniband/hw/efa/efa_com.c
195
cq->phase = 1;
drivers/infiniband/hw/efa/efa_com.c
236
aenq->phase = 1;
drivers/infiniband/hw/efa/efa_com.c
350
EFA_ADMIN_AQ_COMMON_DESC_PHASE, aq->sq.phase);
drivers/infiniband/hw/efa/efa_com.c
368
aq->sq.phase = !aq->sq.phase;
drivers/infiniband/hw/efa/efa_com.c
480
u8 phase;
drivers/infiniband/hw/efa/efa_com.c
487
phase = aq->cq.phase;
drivers/infiniband/hw/efa/efa_com.c
493
EFA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK) == phase) {
drivers/infiniband/hw/efa/efa_com.c
507
phase = !phase;
drivers/infiniband/hw/efa/efa_com.c
513
aq->cq.phase = phase;
drivers/infiniband/hw/efa/efa_com.c
886
u8 phase;
drivers/infiniband/hw/efa/efa_com.c
890
phase = aenq->phase;
drivers/infiniband/hw/efa/efa_com.c
896
EFA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) == phase) {
drivers/infiniband/hw/efa/efa_com.c
914
phase = !phase;
drivers/infiniband/hw/efa/efa_com.c
921
aenq->phase = phase;
drivers/infiniband/hw/efa/efa_com.h
127
u8 phase;
drivers/infiniband/hw/efa/efa_com.h
31
u8 phase;
drivers/infiniband/hw/efa/efa_com.h
43
u8 phase;
drivers/infiniband/hw/efa/efa_com.h
95
u8 phase;
drivers/infiniband/hw/ocrdma/ocrdma.h
316
u32 phase;
drivers/infiniband/hw/ocrdma/ocrdma.h
498
return (cqe_valid == cq->phase);
drivers/infiniband/hw/ocrdma/ocrdma_hw.c
3128
cmd->cmd.set_eqd[i].phase = 0;
drivers/infiniband/hw/ocrdma/ocrdma_sli.h
343
u32 phase;
drivers/infiniband/hw/ocrdma/ocrdma_verbs.c
1005
cq->phase = OCRDMA_CQE_VALID;
drivers/infiniband/hw/ocrdma/ocrdma_verbs.c
2740
cq->phase = (~cq->phase & OCRDMA_CQE_VALID);
drivers/input/ff-core.c
71
effect->u.periodic.phase = 0;
drivers/input/input-compat.h
30
__u16 phase;
drivers/input/joystick/iforce/iforce-ff.c
265
|| old->u.periodic.phase != new->u.periodic.phase);
drivers/input/joystick/iforce/iforce-ff.c
349
effect->u.periodic.period, effect->u.periodic.phase);
drivers/input/joystick/iforce/iforce-ff.c
49
__s16 magnitude, __s16 offset, u16 period, u16 phase)
drivers/input/joystick/iforce/iforce-ff.c
70
data[4] = HI(phase);
drivers/leds/trigger/ledtrig-heartbeat.c
140
heartbeat_data->phase = 0;
drivers/leds/trigger/ledtrig-heartbeat.c
27
unsigned int phase;
drivers/leds/trigger/ledtrig-heartbeat.c
52
switch (heartbeat_data->phase) {
drivers/leds/trigger/ledtrig-heartbeat.c
65
heartbeat_data->phase++;
drivers/leds/trigger/ledtrig-heartbeat.c
71
heartbeat_data->phase++;
drivers/leds/trigger/ledtrig-heartbeat.c
77
heartbeat_data->phase++;
drivers/leds/trigger/ledtrig-heartbeat.c
84
heartbeat_data->phase = 0;
drivers/md/dm-vdo/dm-vdo-target.c
1247
switch (vdo->admin.phase) {
drivers/md/dm-vdo/dm-vdo-target.c
1294
u32 phase = vdo->admin.phase++;
drivers/md/dm-vdo/dm-vdo-target.c
1298
return phase;
drivers/md/dm-vdo/dm-vdo-target.c
1318
admin->phase = starting_phase;
drivers/md/dm-vdo/dm-vdo-target.c
1344
ADMIN_PHASE_NAMES[vdo->admin.phase]);
drivers/md/dm-vdo/dm-vdo-target.c
1501
vdo->admin.phase = PRE_LOAD_PHASE_FORMAT_START;
drivers/md/dm-vdo/dm-vdo-target.c
1503
vdo->admin.phase = PRE_LOAD_PHASE_LOAD_SUPER;
drivers/md/dm-vdo/dm-vdo-target.c
2391
vdo->admin.phase = LOAD_PHASE_FINISHED;
drivers/md/dm-vdo/dm-vdo-target.c
2418
(vdo->admin.phase == LOAD_PHASE_MAKE_DIRTY)) {
drivers/md/dm-vdo/dm-vdo-target.c
2420
vdo->admin.phase = LOAD_PHASE_DRAIN_JOURNAL;
drivers/md/dm-vdo/dm-vdo-target.c
2426
(vdo->admin.phase == LOAD_PHASE_MAKE_DIRTY)) {
drivers/md/dm-vdo/dm-vdo-target.c
2428
vdo->admin.phase = LOAD_PHASE_FINISHED;
drivers/md/dm-vdo/dm-vdo-target.c
2435
vdo->admin.phase = LOAD_PHASE_WAIT_FOR_READ_ONLY;
drivers/md/dm-vdo/dm-vdo-target.c
2608
if (vdo->admin.phase == GROW_LOGICAL_PHASE_GROW_BLOCK_MAP) {
drivers/md/dm-vdo/dm-vdo-target.c
2617
vdo->admin.phase = GROW_LOGICAL_PHASE_ERROR;
drivers/md/dm-vdo/dm-vdo-target.c
2776
completion->vdo->admin.phase = GROW_PHYSICAL_PHASE_ERROR;
drivers/md/dm-vdo/vdo.h
169
u32 phase;
drivers/media/pci/hws/hws_pci.c
144
const char *phase)
drivers/media/pci/hws/hws_pci.c
156
action, phase, READ_ONCE(hws->suspended), hws->start_run,
drivers/media/pci/hws/hws_pci.c
169
action, phase, READ_ONCE(hws->suspended), hws->start_run,
drivers/media/pci/hws/hws_video.c
1246
const char *phase)
drivers/media/pci/hws/hws_video.c
1273
action, phase, v->channel_index, streaming, cap_active,
drivers/media/pci/pt1/pt1.c
406
int phase;
drivers/media/pci/pt1/pt1.c
408
phase = pt1->pdev->device == 0x211a ? 128 : 166;
drivers/media/pci/pt1/pt1.c
409
for (i = 0; i < phase; i++) {
drivers/mmc/core/host.c
215
struct mmc_clk_phase *phase)
drivers/mmc/core/host.c
221
phase->valid = !rc;
drivers/mmc/core/host.c
222
if (phase->valid) {
drivers/mmc/core/host.c
223
phase->in_deg = degrees[0];
drivers/mmc/core/host.c
224
phase->out_deg = degrees[1];
drivers/mmc/core/host.c
232
&map->phase[MMC_TIMING_LEGACY]);
drivers/mmc/core/host.c
234
&map->phase[MMC_TIMING_MMC_HS]);
drivers/mmc/core/host.c
236
&map->phase[MMC_TIMING_SD_HS]);
drivers/mmc/core/host.c
238
&map->phase[MMC_TIMING_UHS_SDR12]);
drivers/mmc/core/host.c
240
&map->phase[MMC_TIMING_UHS_SDR25]);
drivers/mmc/core/host.c
242
&map->phase[MMC_TIMING_UHS_SDR50]);
drivers/mmc/core/host.c
244
&map->phase[MMC_TIMING_UHS_SDR104]);
drivers/mmc/core/host.c
246
&map->phase[MMC_TIMING_UHS_DDR50]);
drivers/mmc/core/host.c
248
&map->phase[MMC_TIMING_MMC_DDR52]);
drivers/mmc/core/host.c
250
&map->phase[MMC_TIMING_MMC_HS200]);
drivers/mmc/core/host.c
252
&map->phase[MMC_TIMING_MMC_HS400]);
drivers/mmc/host/dw_mmc-hi3798mv200.c
160
host->phase_map.phase[MMC_TIMING_MMC_HS200].in_deg = degrees[mid];
drivers/mmc/host/dw_mmc-hi3798mv200.c
161
host->phase_map.phase[MMC_TIMING_MMC_HS400].in_deg = degrees[mid];
drivers/mmc/host/dw_mmc-hi3798mv200.c
162
host->phase_map.phase[MMC_TIMING_UHS_SDR104].in_deg = degrees[mid];
drivers/mmc/host/dw_mmc-hi3798mv200.c
38
struct mmc_clk_phase phase = host->phase_map.phase[ios->timing];
drivers/mmc/host/dw_mmc-hi3798mv200.c
66
if (phase.valid) {
drivers/mmc/host/dw_mmc-hi3798mv200.c
67
clk_set_phase(priv->drive_clk, phase.out_deg);
drivers/mmc/host/dw_mmc-hi3798mv200.c
68
clk_set_phase(priv->sample_clk, phase.in_deg);
drivers/mmc/host/dw_mmc-pltfm.c
62
struct mmc_clk_phase phase;
drivers/mmc/host/dw_mmc-pltfm.c
67
phase = host->phase_map.phase[MMC_TIMING_SD_HS];
drivers/mmc/host/dw_mmc-pltfm.c
68
if (!phase.valid)
drivers/mmc/host/dw_mmc-pltfm.c
80
phase.in_deg /= SOCFPGA_DW_MMC_CLK_PHASE_STEP;
drivers/mmc/host/dw_mmc-pltfm.c
81
phase.out_deg /= SOCFPGA_DW_MMC_CLK_PHASE_STEP;
drivers/mmc/host/dw_mmc-pltfm.c
83
hs_timing = SYSMGR_SDMMC_CTRL_SET(phase.in_deg, phase.out_deg, reg_shift);
drivers/mmc/host/dw_mmc-rockchip.c
182
struct mmc_clk_phase phase = host->phase_map.phase[ios->timing];
drivers/mmc/host/dw_mmc-rockchip.c
220
sample_phase = phase.valid ? phase.in_deg : priv->default_sample_phase;
drivers/mmc/host/dw_mmc-rockchip.c
222
} else if (phase.valid) {
drivers/mmc/host/dw_mmc-rockchip.c
223
rockchip_mmc_set_phase(host, true, phase.in_deg);
drivers/mmc/host/dw_mmc-rockchip.c
287
if (phase.valid)
drivers/mmc/host/dw_mmc-rockchip.c
288
drv_phase = phase.out_deg;
drivers/mmc/host/dw_mmc-rockchip.c
312
int phase;
drivers/mmc/host/dw_mmc-rockchip.c
412
phase = TUNING_ITERATION_TO_PHASE(middle_phase, priv->num_phases);
drivers/mmc/host/dw_mmc-rockchip.c
413
dev_info(host->dev, "Successfully tuned phase to %d\n", phase);
drivers/mmc/host/dw_mmc-rockchip.c
415
rockchip_mmc_set_phase(host, true, phase);
drivers/mmc/host/mmci_stm32_sdmmc.c
488
int unit, int phase, bool sampler)
drivers/mmc/host/mmci_stm32_sdmmc.c
495
FIELD_PREP(DLYB_CFGR_SEL_MASK, phase);
drivers/mmc/host/mmci_stm32_sdmmc.c
552
int unit __maybe_unused, int phase,
drivers/mmc/host/mmci_stm32_sdmmc.c
559
cr |= FIELD_PREP(DLYBSD_CR_RXTAPSEL_MASK, phase);
drivers/mmc/host/mmci_stm32_sdmmc.c
581
int phase, ret;
drivers/mmc/host/mmci_stm32_sdmmc.c
583
for (phase = 0; phase <= dlyb->max; phase++) {
drivers/mmc/host/mmci_stm32_sdmmc.c
584
ret = dlyb->ops->set_cfg(dlyb, dlyb->unit, phase, false);
drivers/mmc/host/mmci_stm32_sdmmc.c
596
end_of_len = phase;
drivers/mmc/host/mmci_stm32_sdmmc.c
609
phase = end_of_len - max_len / 2;
drivers/mmc/host/mmci_stm32_sdmmc.c
610
ret = dlyb->ops->set_cfg(dlyb, dlyb->unit, phase, false);
drivers/mmc/host/mmci_stm32_sdmmc.c
617
dlyb->unit, dlyb->max, phase);
drivers/mmc/host/mmci_stm32_sdmmc.c
71
int phase, bool sampler __maybe_unused);
drivers/mmc/host/sdhci-msm.c
1218
u8 phase, tuned_phases[16], tuned_phase_cnt = 0;
drivers/mmc/host/sdhci-msm.c
1266
phase = 0;
drivers/mmc/host/sdhci-msm.c
1269
rc = msm_config_cm_dll_phase(host, phase);
drivers/mmc/host/sdhci-msm.c
1276
tuned_phases[tuned_phase_cnt++] = phase;
drivers/mmc/host/sdhci-msm.c
1278
mmc_hostname(mmc), phase);
drivers/mmc/host/sdhci-msm.c
1280
} while (++phase < ARRAY_SIZE(tuned_phases));
drivers/mmc/host/sdhci-msm.c
1304
phase = rc;
drivers/mmc/host/sdhci-msm.c
1310
rc = msm_config_cm_dll_phase(host, phase);
drivers/mmc/host/sdhci-msm.c
1313
msm_host->saved_tuning_phase = phase;
drivers/mmc/host/sdhci-msm.c
1315
mmc_hostname(mmc), phase);
drivers/mmc/host/sdhci-msm.c
445
static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
drivers/mmc/host/sdhci-msm.c
458
if (phase > 0xf)
drivers/mmc/host/sdhci-msm.c
479
config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT;
drivers/mmc/host/sdhci-msm.c
499
mmc_hostname(mmc), phase);
drivers/mmc/host/sdhci-of-arasan.c
1250
clk_data->phase_map.phase[host->timing].in_deg);
drivers/mmc/host/sdhci-of-arasan.c
1252
clk_data->phase_map.phase[host->timing].out_deg);
drivers/mmc/host/sdhci-of-arasan.c
1289
clk_data->phase_map.phase[i].in_deg = zynqmp_iclk_phase[i];
drivers/mmc/host/sdhci-of-arasan.c
1290
clk_data->phase_map.phase[i].out_deg = zynqmp_oclk_phase[i];
drivers/mmc/host/sdhci-of-arasan.c
1301
clk_data->phase_map.phase[i].in_deg = versal_iclk_phase[i];
drivers/mmc/host/sdhci-of-arasan.c
1302
clk_data->phase_map.phase[i].out_deg = versal_oclk_phase[i];
drivers/mmc/host/sdhci-of-arasan.c
1312
clk_data->phase_map.phase[i].in_deg = versal_net_iclk_phase[i];
drivers/mmc/host/sdhci-of-arasan.c
1313
clk_data->phase_map.phase[i].out_deg = versal_net_oclk_phase[i];
drivers/mmc/host/sdhci-of-aspeed.c
227
params = &sdhci->phase_map.phase[host->timing];
drivers/mmc/host/sdhci-pci-core.c
1697
static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase)
drivers/mmc/host/sdhci-pci-core.c
1703
val |= (AMD_AUTO_TUNE_SEL | (phase << 1));
drivers/net/dsa/microchip/ksz_ptp.c
593
u8 phase;
drivers/net/dsa/microchip/ksz_ptp.c
601
ret = ksz_read8(dev, regs[PTP_RTC_SUB_NANOSEC], &phase);
drivers/net/dsa/microchip/ksz_ptp.c
614
ts->tv_nsec = nanoseconds + phase * 8;
drivers/net/dsa/sja1105/sja1105.h
29
#define SJA1105_RGMII_DELAY_PHASE_TO_PS(phase) \
drivers/net/dsa/sja1105/sja1105.h
30
((800 * (phase)) / 360)
drivers/net/dsa/sja1105/sja1105.h
31
#define SJA1105_RGMII_DELAY_PHASE_TO_HW(phase) \
drivers/net/dsa/sja1105/sja1105.h
32
(((phase) - 738) / 9)
drivers/net/ethernet/alibaba/eea/eea_adminq.c
155
desc->flags = cpu_to_le16(enet->adminq.phase);
drivers/net/ethernet/alibaba/eea/eea_adminq.c
164
enet->adminq.phase ^= EEA_RING_DESC_F_AQ_PHASE;
drivers/net/ethernet/alibaba/eea/eea_adminq.c
254
aq->phase = 0;
drivers/net/ethernet/alibaba/eea/eea_adminq.c
285
aq->phase = BIT(7);
drivers/net/ethernet/alibaba/eea/eea_adminq.h
60
u16 phase;
drivers/net/ethernet/alibaba/eea/eea_ring.c
120
cq->phase ^= EEA_RING_DESC_F_CQ_PHASE;
drivers/net/ethernet/alibaba/eea/eea_ring.c
197
ering->cq.phase = EEA_RING_DESC_F_CQ_PHASE;
drivers/net/ethernet/alibaba/eea/eea_ring.c
27
u8 phase;
drivers/net/ethernet/alibaba/eea/eea_ring.c
32
phase = READ_ONCE(*(u8 *)(desc + ering->cq.desc_size - 1));
drivers/net/ethernet/alibaba/eea/eea_ring.c
34
if ((phase & EEA_RING_DESC_F_CQ_PHASE) == ering->cq.phase) {
drivers/net/ethernet/alibaba/eea/eea_ring.h
60
u8 phase;
drivers/net/ethernet/amazon/ena/ena_com.c
108
sq->phase = 1;
drivers/net/ethernet/amazon/ena/ena_com.c
129
cq->phase = 1;
drivers/net/ethernet/amazon/ena/ena_com.c
151
aenq->phase = 1;
drivers/net/ethernet/amazon/ena/ena_com.c
2309
u8 phase;
drivers/net/ethernet/amazon/ena/ena_com.c
2312
phase = aenq->phase;
drivers/net/ethernet/amazon/ena/ena_com.c
2317
while ((READ_ONCE(aenq_common->flags) & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) == phase) {
drivers/net/ethernet/amazon/ena/ena_com.c
2340
phase = !phase;
drivers/net/ethernet/amazon/ena/ena_com.c
2347
aenq->phase = phase;
drivers/net/ethernet/amazon/ena/ena_com.c
236
cmd->aq_common_descriptor.flags |= admin_queue->sq.phase &
drivers/net/ethernet/amazon/ena/ena_com.c
262
admin_queue->sq.phase = !admin_queue->sq.phase;
drivers/net/ethernet/amazon/ena/ena_com.c
389
io_sq->phase = 1;
drivers/net/ethernet/amazon/ena/ena_com.c
423
io_cq->phase = 1;
drivers/net/ethernet/amazon/ena/ena_com.c
461
u8 phase;
drivers/net/ethernet/amazon/ena/ena_com.c
464
phase = admin_queue->cq.phase;
drivers/net/ethernet/amazon/ena/ena_com.c
470
ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK) == phase) {
drivers/net/ethernet/amazon/ena/ena_com.c
481
phase = !phase;
drivers/net/ethernet/amazon/ena/ena_com.c
488
admin_queue->cq.phase = phase;
drivers/net/ethernet/amazon/ena/ena_com.h
136
u8 phase;
drivers/net/ethernet/amazon/ena/ena_com.h
179
u8 phase;
drivers/net/ethernet/amazon/ena/ena_com.h
190
u8 phase;
drivers/net/ethernet/amazon/ena/ena_com.h
201
u8 phase;
drivers/net/ethernet/amazon/ena/ena_com.h
252
u8 phase;
drivers/net/ethernet/amazon/ena/ena_eth_com.c
16
expected_phase = io_cq->phase;
drivers/net/ethernet/amazon/ena/ena_eth_com.c
218
io_sq->phase ^= 1;
drivers/net/ethernet/amazon/ena/ena_eth_com.c
309
meta_desc->len_ctrl |= ((u32)io_sq->phase <<
drivers/net/ethernet/amazon/ena/ena_eth_com.c
457
desc->len_ctrl |= ((u32)io_sq->phase << ENA_ETH_IO_TX_DESC_PHASE_SHIFT) &
drivers/net/ethernet/amazon/ena/ena_eth_com.c
512
desc->len_ctrl |= ((u32)io_sq->phase <<
drivers/net/ethernet/amazon/ena/ena_eth_com.c
630
(io_sq->phase & ENA_ETH_IO_RX_DESC_PHASE_MASK);
drivers/net/ethernet/amazon/ena/ena_eth_com.c
84
io_sq->phase ^= 1;
drivers/net/ethernet/amazon/ena/ena_eth_com.h
197
io_cq->phase ^= 1;
drivers/net/ethernet/amazon/ena/ena_eth_com.h
208
expected_phase = io_cq->phase;
drivers/net/ethernet/brocade/bna/bfa_ioc.c
1331
drv_fwhdr->fwver.phase == fwhdr_to_cmp->fwver.phase &&
drivers/net/ethernet/brocade/bna/bfa_ioc.c
1350
if (fwhdr->fwver.phase == 0 &&
drivers/net/ethernet/brocade/bna/bfa_ioc.c
1382
if (fwhdr_to_cmp->fwver.phase > base_fwhdr->fwver.phase)
drivers/net/ethernet/brocade/bna/bfa_ioc.c
1384
else if (fwhdr_to_cmp->fwver.phase < base_fwhdr->fwver.phase)
drivers/net/ethernet/brocade/bna/bfi.h
239
u8 phase;
drivers/net/ethernet/brocade/bna/bfi.h
245
u8 phase;
drivers/net/ethernet/emulex/benet/be_cmds.c
1918
req->set_eqd[i].phase = 0;
drivers/net/ethernet/emulex/benet/be_cmds.h
1159
u32 phase;
drivers/net/ethernet/emulex/benet/be_cmds.h
382
u8 phase[2]; /* dword 2*/
drivers/net/ethernet/fungible/funeth/funeth_rx.c
352
q->phase ^= 1;
drivers/net/ethernet/fungible/funeth/funeth_rx.c
469
static u16 cqe_phase_mismatch(const struct fun_cqe_info *ci, u16 phase)
drivers/net/ethernet/fungible/funeth/funeth_rx.c
473
return (sf_p & 1) ^ phase;
drivers/net/ethernet/fungible/funeth/funeth_rx.c
488
while (budget && !cqe_phase_mismatch(q->next_cqe_info, q->phase)) {
drivers/net/ethernet/fungible/funeth/funeth_rx.c
714
q->phase = 1;
drivers/net/ethernet/fungible/funeth/funeth_txrx.h
172
u16 phase; /* CQ phase tag */
drivers/net/ethernet/intel/ice/ice_ptp.c
1698
u64 clk, period, start, phase;
drivers/net/ethernet/intel/ice/ice_ptp.c
1731
phase = start;
drivers/net/ethernet/intel/ice/ice_ptp.c
1733
div64_u64_rem(start, period, &phase);
drivers/net/ethernet/intel/ice/ice_ptp.c
1741
start = div64_u64(clk + period - 1, period) * period + phase;
drivers/net/ethernet/microchip/lan966x/lan966x_ptp.c
866
ts_phase.tv_sec = rq->perout.phase.sec;
drivers/net/ethernet/microchip/lan966x/lan966x_ptp.c
867
ts_phase.tv_nsec = rq->perout.phase.nsec;
drivers/net/ethernet/mscc/ocelot_ptp.c
243
ts_phase.tv_sec = rq->perout.phase.sec;
drivers/net/ethernet/mscc/ocelot_ptp.c
244
ts_phase.tv_nsec = rq->perout.phase.nsec;
drivers/net/ethernet/qlogic/qed/qed_hw.c
858
struct qed_ptt *p_ptt, const char *phase)
drivers/net/ethernet/qlogic/qed/qed_hw.c
871
phase);
drivers/net/ethernet/qlogic/qed/qed_hw.c
889
phase,
drivers/net/ethernet/qlogic/qed/qed_hw.c
898
phase, rc);
drivers/net/ethernet/qlogic/qed/qed_hw.c
911
phase,
drivers/net/ethernet/qlogic/qed/qed_hw.h
307
struct qed_ptt *p_ptt, const char *phase);
drivers/net/ethernet/qlogic/qed/qed_init_ops.c
535
u32 phase, u32 phase_id)
drivers/net/ethernet/qlogic/qed/qed_init_ops.c
540
if (!(GET_FIELD(data, INIT_IF_PHASE_OP_PHASE) == phase &&
drivers/net/ethernet/qlogic/qed/qed_init_ops.c
549
struct qed_ptt *p_ptt, int phase, int phase_id, int modes)
drivers/net/ethernet/qlogic/qed/qed_init_ops.c
551
bool b_dmae = (phase != PHASE_ENGINE);
drivers/net/ethernet/qlogic/qed/qed_init_ops.c
582
phase, phase_id);
drivers/net/ethernet/qlogic/qed/qed_init_ops.c
593
if (phase == PHASE_ENGINE &&
drivers/net/ethernet/qlogic/qed/qed_init_ops.h
36
int phase,
drivers/net/ethernet/ti/icssg/icss_iep.c
437
ts.tv_sec = req->phase.sec;
drivers/net/ethernet/ti/icssg/icss_iep.c
438
ts.tv_nsec = req->phase.nsec;
drivers/net/ethernet/wangxun/libwx/wx_ptp.c
430
if (rq->perout.phase.sec || rq->perout.phase.nsec) {
drivers/net/mdio/mdio-cavium.h
42
OCT_MDIO_BITFIELD_FIELD(u64 phase:8,
drivers/net/phy/nxp-c45-tja11xx.c
795
if (perout->phase.nsec != 0 &&
drivers/net/phy/nxp-c45-tja11xx.c
796
perout->phase.nsec != (NSEC_PER_SEC >> 1)) {
drivers/net/phy/nxp-c45-tja11xx.c
801
if (perout->phase.nsec == 0)
drivers/net/wireless/ath/ath9k/ar9003_calib.c
893
int magnitude, phase;
drivers/net/wireless/ath/ath9k/ar9003_calib.c
943
phase = coeff->phs_coeff[i][im][0];
drivers/net/wireless/ath/ath9k/ar9003_calib.c
946
(phase & 0x7f) | ((magnitude & 0x7f) << 7);
drivers/net/wireless/realtek/rtw88/coex.c
1290
static void rtw_coex_set_ant_path(struct rtw_dev *rtwdev, bool force, u8 phase)
drivers/net/wireless/realtek/rtw88/coex.c
1299
if (!force && coex_dm->cur_ant_pos_type == phase)
drivers/net/wireless/realtek/rtw88/coex.c
1302
coex_dm->cur_ant_pos_type = phase;
drivers/net/wireless/realtek/rtw88/coex.c
1311
switch (phase) {
drivers/net/wireless/realtek/rtw88/rtw8821a.c
766
u32 phase = coex_dm->cur_ant_pos_type;
drivers/net/wireless/realtek/rtw88/rtw8821a.c
771
switch (phase) {
drivers/net/wireless/realtek/rtw88/rtw8821a.c
819
__func__, phase);
drivers/net/wireless/virtual/mac80211_hwsim_nan.c
1236
if (data->nan.phase == MAC80211_HWSIM_NAN_PHASE_SCAN)
drivers/net/wireless/virtual/mac80211_hwsim_nan.c
274
data->nan.phase != MAC80211_HWSIM_NAN_PHASE_SCAN) ||
drivers/net/wireless/virtual/mac80211_hwsim_nan.c
437
data->nan.phase == MAC80211_HWSIM_NAN_PHASE_SCAN) {
drivers/net/wireless/virtual/mac80211_hwsim_nan.c
469
data->nan.phase = MAC80211_HWSIM_NAN_PHASE_UP;
drivers/net/wireless/virtual/mac80211_hwsim_nan.c
654
if (data->nan.phase == MAC80211_HWSIM_NAN_PHASE_SCAN) {
drivers/net/wireless/virtual/mac80211_hwsim_nan.c
655
data->nan.phase = MAC80211_HWSIM_NAN_PHASE_WARMUP;
drivers/net/wireless/virtual/mac80211_hwsim_nan.c
660
data->nan.phase = MAC80211_HWSIM_NAN_PHASE_UP;
drivers/net/wireless/virtual/mac80211_hwsim_nan.c
751
if (data->nan.phase == MAC80211_HWSIM_NAN_PHASE_UP) {
drivers/net/wireless/virtual/mac80211_hwsim_nan.c
808
data->nan.phase != MAC80211_HWSIM_NAN_PHASE_SCAN &&
drivers/net/wireless/virtual/mac80211_hwsim_nan.c
83
if (data->nan.phase == MAC80211_HWSIM_NAN_PHASE_UP) {
drivers/net/wireless/virtual/mac80211_hwsim_nan.c
880
if (data->nan.phase == MAC80211_HWSIM_NAN_PHASE_SCAN ||
drivers/net/wireless/virtual/mac80211_hwsim_nan.c
927
data->nan.phase = MAC80211_HWSIM_NAN_PHASE_SCAN;
drivers/net/wireless/virtual/mac80211_hwsim_nan.h
40
enum mac80211_hwsim_nan_phase phase;
drivers/net/wwan/iosm/iosm_ipc_imem.c
1233
ipc_imem->phase = IPC_P_OFF_REQ;
drivers/net/wwan/iosm/iosm_ipc_imem.c
1265
ipc_imem->phase = IPC_P_OFF;
drivers/net/wwan/iosm/iosm_ipc_imem.c
1275
enum ipc_phase phase;
drivers/net/wwan/iosm/iosm_ipc_imem.c
1286
phase = ipc_imem_phase_update(ipc_imem);
drivers/net/wwan/iosm/iosm_ipc_imem.c
1289
switch (phase) {
drivers/net/wwan/iosm/iosm_ipc_imem.c
1320
phase);
drivers/net/wwan/iosm/iosm_ipc_imem.c
1323
dev_err(ipc_imem->dev, "unexpected operation phase %d", phase);
drivers/net/wwan/iosm/iosm_ipc_imem.c
1329
ipc_imem->phase = IPC_P_OFF;
drivers/net/wwan/iosm/iosm_ipc_imem.c
1381
ipc_imem->phase = IPC_P_OFF;
drivers/net/wwan/iosm/iosm_ipc_imem.c
1488
ipc_imem->phase = ipc_imem_phase_update(ipc_imem);
drivers/net/wwan/iosm/iosm_ipc_imem.c
291
ipc_imem_phase_get_string(ipc_imem->phase),
drivers/net/wwan/iosm/iosm_ipc_imem.c
540
return (ipc_imem->phase == IPC_P_RUN &&
drivers/net/wwan/iosm/iosm_ipc_imem.c
572
if (ipc_imem->phase != IPC_P_RUN) {
drivers/net/wwan/iosm/iosm_ipc_imem.c
645
enum ipc_phase old_phase, phase;
drivers/net/wwan/iosm/iosm_ipc_imem.c
654
old_phase = ipc_imem->phase;
drivers/net/wwan/iosm/iosm_ipc_imem.c
664
phase = ipc_imem_phase_update(ipc_imem);
drivers/net/wwan/iosm/iosm_ipc_imem.c
666
switch (phase) {
drivers/net/wwan/iosm/iosm_ipc_imem.c
704
ipc_imem_phase_get_string(phase));
drivers/net/wwan/iosm/iosm_ipc_imem.c
772
if ((phase == IPC_P_PSI || phase == IPC_P_EBL) &&
drivers/net/wwan/iosm/iosm_ipc_imem.c
814
if (ipc_imem->phase != IPC_P_ROM) {
drivers/net/wwan/iosm/iosm_ipc_imem.c
819
ipc_imem->phase = IPC_P_ROM;
drivers/net/wwan/iosm/iosm_ipc_imem.c
823
ipc_imem->phase = IPC_P_PSI;
drivers/net/wwan/iosm/iosm_ipc_imem.c
827
ipc_imem->phase = IPC_P_EBL;
drivers/net/wwan/iosm/iosm_ipc_imem.c
831
if (ipc_imem->phase != IPC_P_RUN &&
drivers/net/wwan/iosm/iosm_ipc_imem.c
835
ipc_imem->phase = IPC_P_RUN;
drivers/net/wwan/iosm/iosm_ipc_imem.c
839
if (ipc_imem->phase != IPC_P_CRASH)
drivers/net/wwan/iosm/iosm_ipc_imem.c
842
ipc_imem->phase = IPC_P_CRASH;
drivers/net/wwan/iosm/iosm_ipc_imem.c
846
if (ipc_imem->phase != IPC_P_CD_READY)
drivers/net/wwan/iosm/iosm_ipc_imem.c
848
ipc_imem->phase = IPC_P_CD_READY;
drivers/net/wwan/iosm/iosm_ipc_imem.c
859
return ipc_imem->phase;
drivers/net/wwan/iosm/iosm_ipc_imem.c
914
return ipc_imem->phase == IPC_P_OFF_REQ ?
drivers/net/wwan/iosm/iosm_ipc_imem.c
915
ipc_imem->phase :
drivers/net/wwan/iosm/iosm_ipc_imem.c
919
const char *ipc_imem_phase_get_string(enum ipc_phase phase)
drivers/net/wwan/iosm/iosm_ipc_imem.c
921
switch (phase) {
drivers/net/wwan/iosm/iosm_ipc_imem.c
984
if (ipc_imem->phase == IPC_P_RUN) {
drivers/net/wwan/iosm/iosm_ipc_imem.h
363
enum ipc_phase phase;
drivers/net/wwan/iosm/iosm_ipc_imem.h
548
const char *ipc_imem_phase_get_string(enum ipc_phase phase);
drivers/net/wwan/iosm/iosm_ipc_imem_ops.c
146
enum ipc_phase phase;
drivers/net/wwan/iosm/iosm_ipc_imem_ops.c
149
phase = ipc_imem->phase;
drivers/net/wwan/iosm/iosm_ipc_imem_ops.c
152
switch (phase) {
drivers/net/wwan/iosm/iosm_ipc_imem_ops.c
174
channel->channel_id, phase);
drivers/net/wwan/iosm/iosm_ipc_imem_ops.c
19
ipc_imem_phase_get_string(ipc_imem->phase), if_id);
drivers/net/wwan/iosm/iosm_ipc_imem_ops.c
203
curr_phase = ipc_imem->phase;
drivers/net/wwan/iosm/iosm_ipc_imem_ops.c
24
ipc_imem_phase_get_string(ipc_imem->phase));
drivers/net/wwan/iosm/iosm_ipc_imem_ops.c
294
ipc_imem_phase_get_string(ipc_imem->phase));
drivers/net/wwan/iosm/iosm_ipc_imem_ops.c
323
ipc_imem->phase == IPC_P_OFF_REQ)
drivers/net/wwan/iosm/iosm_ipc_imem_ops.c
349
enum ipc_phase phase;
drivers/net/wwan/iosm/iosm_ipc_imem_ops.c
352
phase = ipc_imem_phase_update(ipc_imem);
drivers/net/wwan/iosm/iosm_ipc_imem_ops.c
353
switch (phase) {
drivers/net/wwan/iosm/iosm_ipc_imem_ops.c
393
dev_err(ipc_imem->dev, "SIO open refused, phase %d", phase);
drivers/net/wwan/iosm/iosm_ipc_imem_ops.c
529
ipc_imem->phase = IPC_P_PSI;
drivers/net/wwan/iosm/iosm_ipc_imem_ops.c
552
ipc_imem_phase_get_string(ipc_imem->phase),
drivers/net/wwan/iosm/iosm_ipc_imem_ops.c
585
if (ipc_imem->phase == IPC_P_ROM) {
drivers/net/wwan/iosm/iosm_ipc_imem_ops.c
66
if (ipc_imem->phase != IPC_P_RUN) {
drivers/net/wwan/iosm/iosm_ipc_imem_ops.c
68
ipc_imem_phase_get_string(ipc_imem->phase));
drivers/nvme/target/pci-epf.c
1286
cq->phase = 1;
drivers/nvme/target/pci-epf.c
1385
sq->phase = 0;
drivers/nvme/target/pci-epf.c
1794
cqe->status = cpu_to_le16((iod->status << 1) | cq->phase);
drivers/nvme/target/pci-epf.c
1800
cq->phase);
drivers/nvme/target/pci-epf.c
1808
cq->phase ^= 1;
drivers/nvme/target/pci-epf.c
96
u16 phase;
drivers/parport/ieee1284.c
242
if (port->ieee1284.phase != IEEE1284_PH_FWD_IDLE) {
drivers/parport/ieee1284.c
260
port->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
drivers/parport/ieee1284.c
296
port->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
drivers/parport/ieee1284.c
364
port->ieee1284.phase = IEEE1284_PH_NEGOTIATION;
drivers/parport/ieee1284.c
401
port->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
drivers/parport/ieee1284.c
498
port->ieee1284.phase = IEEE1284_PH_ECP_SETUP;
drivers/parport/ieee1284.c
513
port->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
drivers/parport/ieee1284.c
518
port->ieee1284.phase = IEEE1284_PH_REV_IDLE;
drivers/parport/ieee1284.c
521
port->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
drivers/parport/ieee1284.c
544
port->ieee1284.phase = IEEE1284_PH_HBUSY_DAVAIL;
drivers/parport/ieee1284.c
556
if (port->ieee1284.phase == IEEE1284_PH_REV_IDLE) {
drivers/parport/ieee1284_ops.c
138
port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
drivers/parport/ieee1284_ops.c
171
port->ieee1284.phase = IEEE1284_PH_REV_DATA;
drivers/parport/ieee1284_ops.c
221
port->physport->ieee1284.phase = IEEE1284_PH_REV_IDLE;
drivers/parport/ieee1284_ops.c
224
port->physport->ieee1284.phase = IEEE1284_PH_HBUSY_DAVAIL;
drivers/parport/ieee1284_ops.c
259
port->physport->ieee1284.phase = IEEE1284_PH_REV_DATA;
drivers/parport/ieee1284_ops.c
306
port->physport->ieee1284.phase = IEEE1284_PH_REV_IDLE;
drivers/parport/ieee1284_ops.c
309
port->physport->ieee1284.phase = IEEE1284_PH_HBUSY_DAVAIL;
drivers/parport/ieee1284_ops.c
345
port->ieee1284.phase = IEEE1284_PH_REV_IDLE;
drivers/parport/ieee1284_ops.c
348
port->ieee1284.phase = IEEE1284_PH_ECP_DIR_UNKNOWN;
drivers/parport/ieee1284_ops.c
374
port->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
drivers/parport/ieee1284_ops.c
378
port->ieee1284.phase = IEEE1284_PH_ECP_DIR_UNKNOWN;
drivers/parport/ieee1284_ops.c
401
if (port->ieee1284.phase != IEEE1284_PH_FWD_IDLE)
drivers/parport/ieee1284_ops.c
405
port->ieee1284.phase = IEEE1284_PH_FWD_DATA;
drivers/parport/ieee1284_ops.c
467
port->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
drivers/parport/ieee1284_ops.c
489
if (port->ieee1284.phase != IEEE1284_PH_REV_IDLE)
drivers/parport/ieee1284_ops.c
493
port->ieee1284.phase = IEEE1284_PH_REV_DATA;
drivers/parport/ieee1284_ops.c
52
port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
drivers/parport/ieee1284_ops.c
612
port->ieee1284.phase = IEEE1284_PH_REV_IDLE;
drivers/parport/ieee1284_ops.c
631
if (port->ieee1284.phase != IEEE1284_PH_FWD_IDLE)
drivers/parport/ieee1284_ops.c
635
port->ieee1284.phase = IEEE1284_PH_FWD_DATA;
drivers/parport/ieee1284_ops.c
698
port->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
drivers/parport/parport_ip32.c
1639
physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
drivers/parport/parport_ip32.c
1669
physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
drivers/parport/parport_ip32.c
1700
if (physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) {
drivers/parport/parport_ip32.c
1709
physport->ieee1284.phase = IEEE1284_PH_ECP_DIR_UNKNOWN;
drivers/parport/parport_ip32.c
1720
physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
drivers/parport/parport_ip32.c
1750
physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
drivers/parport/parport_pc.c
744
port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
drivers/parport/parport_pc.c
788
port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
drivers/parport/parport_pc.c
811
if (port->physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) {
drivers/parport/parport_pc.c
839
port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
drivers/parport/parport_pc.c
902
port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
drivers/parport/probe.c
197
if (port->physport->ieee1284.phase != IEEE1284_PH_HBUSY_DAVAIL) {
drivers/parport/share.c
453
tmp->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
drivers/ptp/ptp_chardev.c
283
if (perout->phase.sec > perout->period.sec ||
drivers/ptp/ptp_chardev.c
284
(perout->phase.sec == perout->period.sec &&
drivers/ptp/ptp_chardev.c
285
perout->phase.nsec >= perout->period.nsec))
drivers/ptp/ptp_ocp.c
2338
s->start = ktime_add(s->start, s->phase);
drivers/ptp/ptp_ocp.c
2372
s.phase = ktime_set(req->phase.sec, req->phase.nsec);
drivers/ptp/ptp_ocp.c
332
ktime_t phase;
drivers/ptp/ptp_ocp.c
3480
s.phase = bp->signal[gen].phase;
drivers/ptp/ptp_ocp.c
3493
err = kstrtou64(argv[argc], 0, &s.phase);
drivers/ptp/ptp_ocp.c
3538
signal->period, signal->duty, signal->phase, signal->polarity,
drivers/ptp/ptp_ocp.c
3581
return sysfs_emit(buf, "%llu\n", bp->signal[i].phase);
drivers/ptp/ptp_ocp.c
3583
static EXT_ATTR_RO(signal, phase, 0);
drivers/ptp/ptp_ocp.c
3584
static EXT_ATTR_RO(signal, phase, 1);
drivers/ptp/ptp_ocp.c
3585
static EXT_ATTR_RO(signal, phase, 2);
drivers/ptp/ptp_ocp.c
3586
static EXT_ATTR_RO(signal, phase, 3);
drivers/ptp/ptp_ocp.c
4343
signal->period, signal->duty, signal->phase,
drivers/regulator/pf8x00-regulator.c
238
int phase;
drivers/regulator/pf8x00-regulator.c
257
phase = val / 45;
drivers/regulator/pf8x00-regulator.c
259
if (phase >= 1)
drivers/regulator/pf8x00-regulator.c
260
phase -= 1;
drivers/regulator/pf8x00-regulator.c
262
phase = PF8X00_SWXPHASE_SHIFT;
drivers/regulator/pf8x00-regulator.c
266
phase);
drivers/scsi/FlashPoint.c
3952
void (*phase) (u32, unsigned char);
drivers/scsi/FlashPoint.c
3959
phase = FPT_s_PhaseTbl[phase_ref];
drivers/scsi/FlashPoint.c
3961
(*phase) (p_port, p_card); /* Call the correct phase func */
drivers/scsi/NCR5380.c
1198
phase = PHASE_MSGOUT;
drivers/scsi/NCR5380.c
1199
NCR5380_transfer_pio(instance, &phase, &len, &data, 0);
drivers/scsi/NCR5380.c
1247
unsigned char *phase, int *count,
drivers/scsi/NCR5380.c
1251
unsigned char p = *phase, tmp;
drivers/scsi/NCR5380.c
1352
*phase = tmp & PHASE_MASK;
drivers/scsi/NCR5380.c
1354
*phase = PHASE_UNKNOWN;
drivers/scsi/NCR5380.c
1396
unsigned char *msgptr, phase, tmp;
drivers/scsi/NCR5380.c
1435
phase = PHASE_MSGOUT;
drivers/scsi/NCR5380.c
1436
NCR5380_transfer_pio(instance, &phase, &len, &msgptr, can_sleep);
drivers/scsi/NCR5380.c
1470
unsigned char *phase, int *count,
drivers/scsi/NCR5380.c
1476
unsigned char p = *phase;
drivers/scsi/NCR5380.c
1482
*phase = tmp;
drivers/scsi/NCR5380.c
1486
ncmd->phase = p;
drivers/scsi/NCR5380.c
1668
unsigned char phase, tmp, extended_msg[10], old_phase = 0xff;
drivers/scsi/NCR5380.c
1681
phase = (tmp & PHASE_MASK);
drivers/scsi/NCR5380.c
1682
if (phase != old_phase) {
drivers/scsi/NCR5380.c
1683
old_phase = phase;
drivers/scsi/NCR5380.c
1687
if (phase == PHASE_CMDOUT &&
drivers/scsi/NCR5380.c
1710
if (sink && (phase != PHASE_MSGOUT)) {
drivers/scsi/NCR5380.c
1723
switch (phase) {
drivers/scsi/NCR5380.c
1763
if (NCR5380_transfer_dma(instance, &phase,
drivers/scsi/NCR5380.c
1783
NCR5380_transfer_pio(instance, &phase, &len,
drivers/scsi/NCR5380.c
1797
NCR5380_transfer_pio(instance, &phase, &len, &data, 0);
drivers/scsi/NCR5380.c
1903
phase = PHASE_MSGIN;
drivers/scsi/NCR5380.c
1904
NCR5380_transfer_pio(instance, &phase, &len, &data, 1);
drivers/scsi/NCR5380.c
1915
phase = PHASE_MSGIN;
drivers/scsi/NCR5380.c
1917
NCR5380_transfer_pio(instance, &phase, &len, &data, 1);
drivers/scsi/NCR5380.c
1964
NCR5380_transfer_pio(instance, &phase, &len, &data, 0);
drivers/scsi/NCR5380.c
1982
NCR5380_transfer_pio(instance, &phase, &len, &data, 0);
drivers/scsi/NCR5380.c
1988
NCR5380_transfer_pio(instance, &phase, &len, &data, 0);
drivers/scsi/NCR5380.c
2089
unsigned char phase = PHASE_MSGIN;
drivers/scsi/NCR5380.c
2091
NCR5380_transfer_pio(instance, &phase, &len, &data, 0);
drivers/scsi/NCR5380.c
763
p = ncmd->phase;
drivers/scsi/NCR5380.c
967
unsigned char tmp[3], phase;
drivers/scsi/NCR5380.h
189
#define PHASE_SR_TO_TCR(phase) ((phase) >> 2)
drivers/scsi/NCR5380.h
234
int phase;
drivers/scsi/NCR5380.h
287
static int NCR5380_transfer_dma(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data);
drivers/scsi/NCR5380.h
289
unsigned char *phase, int *count,
drivers/scsi/aha152x.c
1020
if (aha152x_priv(SCpnt)->phase & resetting)
drivers/scsi/aha152x.c
1106
if (aha152x_priv(SCpnt)->phase & resetted) {
drivers/scsi/aha152x.c
1405
acp->phase &= ~syncneg;
drivers/scsi/aha152x.c
1407
if (acp->phase & completed) {
drivers/scsi/aha152x.c
1411
} else if (acp->phase & aborted) {
drivers/scsi/aha152x.c
1414
} else if (acp->phase & resetted) {
drivers/scsi/aha152x.c
1417
} else if (acp->phase & disconnected) {
drivers/scsi/aha152x.c
1423
acp->phase |= 1 << 16;
drivers/scsi/aha152x.c
1442
if (aha152x_priv(DONE_SC)->phase & check_condition) {
drivers/scsi/aha152x.c
1458
if (!(aha152x_priv(DONE_SC)->phase & not_issued)) {
drivers/scsi/aha152x.c
1483
if (!(aha152x_priv(ptr)->phase & resetting)) {
drivers/scsi/aha152x.c
1511
acp->phase |= selecting;
drivers/scsi/aha152x.c
1545
acp->phase &= ~(selecting | not_issued);
drivers/scsi/aha152x.c
1560
if (acp->phase & aborting) {
drivers/scsi/aha152x.c
1562
} else if (acp->phase & resetting) {
drivers/scsi/aha152x.c
1565
acp->phase |= syncneg;
drivers/scsi/aha152x.c
1589
acp->phase &= ~selecting;
drivers/scsi/aha152x.c
1591
if (acp->phase & aborted)
drivers/scsi/aha152x.c
1621
if (!(acp->phase & not_issued))
drivers/scsi/aha152x.c
1718
acp->phase &= ~disconnected;
drivers/scsi/aha152x.c
1735
acp->phase |= disconnected;
drivers/scsi/aha152x.c
1739
acp->phase |= completed;
drivers/scsi/aha152x.c
1870
if ((aha152x_priv(CURRENT_SC)->phase & syncneg) &&
drivers/scsi/aha152x.c
1901
acp->phase |= identified;
drivers/scsi/aha152x.c
1904
acp->phase |= aborted;
drivers/scsi/aha152x.c
1907
acp->phase |= resetted;
drivers/scsi/aha152x.c
2240
(aha152x_priv(CURRENT_SC)->phase & selecting)) {
drivers/scsi/aha152x.c
2372
aha152x_priv(CURRENT_SC)->phase &= ~spiordy;
drivers/scsi/aha152x.c
2394
aha152x_priv(CURRENT_SC)->phase |= spiordy;
drivers/scsi/aha152x.c
2484
const int phase = aha152x_priv(ptr)->phase;
drivers/scsi/aha152x.c
2491
phase & not_issued ? "not issued|" : "",
drivers/scsi/aha152x.c
2492
phase & selecting ? "selecting|" : "",
drivers/scsi/aha152x.c
2493
phase & identified ? "identified|" : "",
drivers/scsi/aha152x.c
2494
phase & disconnected ? "disconnected|" : "",
drivers/scsi/aha152x.c
2495
phase & completed ? "completed|" : "",
drivers/scsi/aha152x.c
2496
phase & spiordy ? "spiordy|" : "",
drivers/scsi/aha152x.c
2497
phase & syncneg ? "syncneg|" : "",
drivers/scsi/aha152x.c
2498
phase & aborted ? "aborted|" : "",
drivers/scsi/aha152x.c
2499
phase & resetted ? "resetted|" : "",
drivers/scsi/aha152x.c
2533
const int phase = acp->phase;
drivers/scsi/aha152x.c
2546
if (phase & not_issued)
drivers/scsi/aha152x.c
2548
if (phase & selecting)
drivers/scsi/aha152x.c
2550
if (phase & disconnected)
drivers/scsi/aha152x.c
2552
if (phase & aborted)
drivers/scsi/aha152x.c
2554
if (phase & identified)
drivers/scsi/aha152x.c
2556
if (phase & completed)
drivers/scsi/aha152x.c
2558
if (phase & spiordy)
drivers/scsi/aha152x.c
2560
if (phase & syncneg)
drivers/scsi/aha152x.c
326
int phase;
drivers/scsi/aha152x.c
899
acp->phase |= 1 << 16;
drivers/scsi/aha152x.c
901
if (acp->phase & selecting) {
drivers/scsi/aha152x.c
906
SETPORT(SIMODE0, (acp->phase & spiordy) ? ENSPIORDY : 0);
drivers/scsi/aha152x.c
928
struct completion *complete, int phase)
drivers/scsi/aha152x.c
934
acp->phase = not_issued | phase;
drivers/scsi/aha152x.c
939
if (acp->phase & (resetting | check_condition)) {
drivers/scsi/aha152x.c
961
if ((phase & resetting) || !scsi_sglist(SCpnt)) {
drivers/scsi/aic7xxx/aic79xx.h
813
uint8_t phase;
drivers/scsi/aic7xxx/aic79xx_core.c
249
static const struct ahd_phase_table_entry* ahd_lookup_phase_entry(int phase);
drivers/scsi/aic7xxx/aic79xx_core.c
4309
ahd_lookup_phase_entry(int phase)
drivers/scsi/aic7xxx/aic79xx_core.c
4320
if (phase == entry->phase)
drivers/scsi/aic7xxx/aic7xxx.h
759
uint8_t phase;
drivers/scsi/aic7xxx/aic7xxx_core.c
1386
if (lastphase == ahc_phase_table[i].phase)
drivers/scsi/aic7xxx/aic7xxx_core.c
1642
if (errorphase == ahc_phase_table[i].phase)
drivers/scsi/aic7xxx/aic7xxx_core.c
1917
if (lastphase == ahc_phase_table[i].phase)
drivers/scsi/aic7xxx/aic7xxx_core.c
2777
ahc_lookup_phase_entry(int phase)
drivers/scsi/aic7xxx/aic7xxx_core.c
2788
if (phase == entry->phase)
drivers/scsi/aic94xx/aic94xx_tmf.c
141
enum clear_nexus_phase phase)
drivers/scsi/aic94xx/aic94xx_tmf.c
147
switch (phase) {
drivers/scsi/arm/acornscsi.c
1301
host->scsi.phase = PHASE_COMMAND;
drivers/scsi/arm/acornscsi.c
1463
if (host->scsi.phase == PHASE_RECONNECTED) {
drivers/scsi/arm/acornscsi.c
1473
host->scsi.phase = PHASE_MSGIN;
drivers/scsi/arm/acornscsi.c
1480
if (host->scsi.phase != PHASE_STATUSIN) {
drivers/scsi/arm/acornscsi.c
1485
host->scsi.phase = PHASE_DONE;
drivers/scsi/arm/acornscsi.c
1500
host->scsi.phase = PHASE_MSGIN;
drivers/scsi/arm/acornscsi.c
1515
host->scsi.phase = PHASE_MSGIN;
drivers/scsi/arm/acornscsi.c
1529
host->scsi.phase = PHASE_DISCONNECT;
drivers/scsi/arm/acornscsi.c
1632
host->scsi.phase = PHASE_MSGIN;
drivers/scsi/arm/acornscsi.c
1749
ADD_STATUS(target, 0x81, host->scsi.phase, 0);
drivers/scsi/arm/acornscsi.c
1752
host->scsi.phase = PHASE_RECONNECTED;
drivers/scsi/arm/acornscsi.c
1854
host->scsi.phase = PHASE_ABORTED;
drivers/scsi/arm/acornscsi.c
1884
print_sbic_status(asr, ssr, host->scsi.phase);
drivers/scsi/arm/acornscsi.c
1887
ADD_STATUS(8, ssr, host->scsi.phase, in_irq);
drivers/scsi/arm/acornscsi.c
1890
ADD_STATUS(host->SCpnt->device->id, ssr, host->scsi.phase, in_irq);
drivers/scsi/arm/acornscsi.c
1914
switch (host->scsi.phase) {
drivers/scsi/arm/acornscsi.c
1919
host->scsi.phase = PHASE_CONNECTED;
drivers/scsi/arm/acornscsi.c
1927
ADD_STATUS(8, ssr, host->scsi.phase, 1);
drivers/scsi/arm/acornscsi.c
1928
ADD_STATUS(host->SCpnt->device->id, ssr, host->scsi.phase, 1);
drivers/scsi/arm/acornscsi.c
1964
host->scsi.phase = PHASE_STATUSIN;
drivers/scsi/arm/acornscsi.c
1970
host->scsi.phase = PHASE_MSGOUT;
drivers/scsi/arm/acornscsi.c
2004
host->scsi.phase = PHASE_STATUSIN;
drivers/scsi/arm/acornscsi.c
2034
host->scsi.phase = PHASE_DATAOUT;
drivers/scsi/arm/acornscsi.c
2044
host->scsi.phase = PHASE_DATAIN;
drivers/scsi/arm/acornscsi.c
2050
host->scsi.phase = PHASE_STATUSIN;
drivers/scsi/arm/acornscsi.c
2074
host->scsi.phase = PHASE_IDLE;
drivers/scsi/arm/acornscsi.c
2104
ADD_STATUS(host->SCpnt->device->id, ssr, host->scsi.phase, in_irq);
drivers/scsi/arm/acornscsi.c
2112
host->scsi.phase = PHASE_DATAOUT;
drivers/scsi/arm/acornscsi.c
2121
host->scsi.phase = PHASE_DATAIN;
drivers/scsi/arm/acornscsi.c
2133
host->scsi.phase = PHASE_STATUSIN;
drivers/scsi/arm/acornscsi.c
2172
host->scsi.phase = PHASE_STATUSIN;
drivers/scsi/arm/acornscsi.c
2222
host->scsi.phase = PHASE_STATUSIN;
drivers/scsi/arm/acornscsi.c
2331
host->scsi.phase = PHASE_IDLE;
drivers/scsi/arm/acornscsi.c
2429
scsi_pointer->phase = (int)acornscsi_datadirection(SCpnt->cmnd[0]);
drivers/scsi/arm/acornscsi.c
2446
if (host->scsi.phase == PHASE_IDLE)
drivers/scsi/arm/acornscsi.c
2498
switch (host->scsi.phase) {
drivers/scsi/arm/acornscsi.c
2569
print_sbic_status(asr, ssr, host->scsi.phase);
drivers/scsi/arm/acornscsi.c
2652
print_sbic_status(asr, ssr, host->scsi.phase);
drivers/scsi/arm/acornscsi.c
376
host->scsi.phase = PHASE_IDLE;
drivers/scsi/arm/acornscsi.c
730
host->scsi.phase = PHASE_CONNECTING;
drivers/scsi/arm/acornscsi.c
855
host->scsi.phase = PHASE_IDLE;
drivers/scsi/arm/acornscsi.h
284
phase_t phase; /* current phase */
drivers/scsi/arm/arm_scsi.h
101
scsi_pointer->phase = scsi_bufflen(SCpnt);
drivers/scsi/arm/arm_scsi.h
125
scsi_pointer->phase =
drivers/scsi/arm/arm_scsi.h
134
scsi_pointer->phase = 0;
drivers/scsi/arm/fas216.c
1018
info->scsi.phase = PHASE_MSGIN;
drivers/scsi/arm/fas216.c
1034
info->scsi.phase = PHASE_MSGOUT_EXPECT;
drivers/scsi/arm/fas216.c
1051
info->scsi.phase = PHASE_MSGOUT_EXPECT;
drivers/scsi/arm/fas216.c
1107
info->scsi.phase = PHASE_MSGIN_DISCONNECT;
drivers/scsi/arm/fas216.c
1164
info->scsi.phase = PHASE_MSGOUT_EXPECT;
drivers/scsi/arm/fas216.c
1281
info->scsi.phase = PHASE_MSGOUT_EXPECT;
drivers/scsi/arm/fas216.c
1307
info->scsi.phase = PHASE_COMMAND;
drivers/scsi/arm/fas216.c
1343
info->scsi.phase = PHASE_MSGOUT;
drivers/scsi/arm/fas216.c
1360
stat, is, info->scsi.phase);
drivers/scsi/arm/fas216.c
1362
switch (info->scsi.phase) {
drivers/scsi/arm/fas216.c
1395
switch (STATE(stat & STAT_BUSMASK, info->scsi.phase)) {
drivers/scsi/arm/fas216.c
1400
info->scsi.phase = PHASE_DATAIN;
drivers/scsi/arm/fas216.c
1415
info->scsi.phase = PHASE_DATAOUT;
drivers/scsi/arm/fas216.c
1429
info->scsi.phase = PHASE_STATUS;
drivers/scsi/arm/fas216.c
1443
info->scsi.phase = PHASE_MSGIN;
drivers/scsi/arm/fas216.c
1454
info->scsi.phase = PHASE_COMMAND;
drivers/scsi/arm/fas216.c
1516
info->scsi.phase = PHASE_MSGOUT_EXPECT;
drivers/scsi/arm/fas216.c
1520
if (info->scsi.phase == PHASE_MSGIN_DISCONNECT) {
drivers/scsi/arm/fas216.c
1527
info->scsi.phase = PHASE_MSGOUT_EXPECT;
drivers/scsi/arm/fas216.c
1563
stat, is, info->scsi.phase);
drivers/scsi/arm/fas216.c
1565
switch (info->scsi.phase) {
drivers/scsi/arm/fas216.c
1575
info->scsi.phase = PHASE_DONE;
drivers/scsi/arm/fas216.c
1613
info->scsi.phase = PHASE_IDLE;
drivers/scsi/arm/fas216.c
1647
add_debug_list(stat, is, inst, info->scsi.phase);
drivers/scsi/arm/fas216.c
1719
info->scsi.phase = PHASE_SELSTEPS;
drivers/scsi/arm/fas216.c
1774
info->scsi.phase = PHASE_SELECTION;
drivers/scsi/arm/fas216.c
1853
info->scsi.phase = PHASE_SELECTION;
drivers/scsi/arm/fas216.c
202
info->scsi.type, info->scsi.phase);
drivers/scsi/arm/fas216.c
2151
info->scsi.phase = PHASE_IDLE;
drivers/scsi/arm/fas216.c
2185
if (info->scsi.phase == PHASE_IDLE)
drivers/scsi/arm/fas216.c
2237
if (result == 0 && info->scsi.phase == PHASE_IDLE)
drivers/scsi/arm/fas216.c
2385
switch (info->scsi.phase) {
drivers/scsi/arm/fas216.c
2525
if (info->scsi.phase == PHASE_IDLE)
drivers/scsi/arm/fas216.c
2611
info->scsi.phase = PHASE_IDLE;
drivers/scsi/arm/fas216.c
278
if (info->scsi.phase < ARRAY_SIZE(phases) &&
drivers/scsi/arm/fas216.c
279
phases[info->scsi.phase])
drivers/scsi/arm/fas216.c
280
return phases[info->scsi.phase];
drivers/scsi/arm/fas216.c
567
info->scsi.phase = PHASE_MSGOUT_EXPECT;
drivers/scsi/arm/fas216.c
608
info->scsi.phase = PHASE_MSGOUT_EXPECT;
drivers/scsi/arm/fas216.c
638
SCp->phase -= bytes_transferred;
drivers/scsi/arm/fas216.c
720
total = info->scsi.SCp.phase;
drivers/scsi/arm/fas216.c
738
if (info->scsi.phase == PHASE_DATAOUT)
drivers/scsi/arm/fas216.c
758
info->scsi.SCp.phase);
drivers/scsi/arm/fas216.c
778
if (info->scsi.phase == PHASE_DATAOUT)
drivers/scsi/arm/fas216.c
789
fas216_set_stc(info, info->scsi.SCp.phase);
drivers/scsi/arm/fas216.c
842
if (info->scsi.phase == PHASE_DATAIN) {
drivers/scsi/arm/fas216.c
892
info->scsi.phase);
drivers/scsi/arm/fas216.c
896
switch (info->scsi.phase) {
drivers/scsi/arm/fas216.c
904
info->scsi.phase = PHASE_IDLE;
drivers/scsi/arm/fas216.c
907
if (info->scsi.phase == PHASE_IDLE)
drivers/scsi/arm/fas216.c
949
WARN_ON(info->scsi.phase == PHASE_SELECTION ||
drivers/scsi/arm/fas216.c
950
info->scsi.phase == PHASE_SELSTEPS);
drivers/scsi/arm/fas216.c
955
info->scsi.phase, cfis);
drivers/scsi/arm/fas216.h
233
phase_t phase; /* current phase */
drivers/scsi/be2iscsi/be_cmds.h
1106
u32 phase;
drivers/scsi/be2iscsi/be_cmds.h
307
u8 phase[2]; /* dword 2 */
drivers/scsi/be2iscsi/be_cmds.h
329
u32 phase;
drivers/scsi/be2iscsi/be_cmds.h
707
__le32 phase;
drivers/scsi/be2iscsi/be_mgmt.c
336
req->delay[i].phase = 0;
drivers/scsi/bfa/bfa_ioc.c
1550
drv_fwhdr->fwver.phase == fwhdr_to_cmp->fwver.phase &&
drivers/scsi/bfa/bfa_ioc.c
1569
if (fwhdr->fwver.phase == 0 &&
drivers/scsi/bfa/bfa_ioc.c
1607
if (fwhdr_to_cmp->fwver.phase > base_fwhdr->fwver.phase)
drivers/scsi/bfa/bfa_ioc.c
1609
else if (fwhdr_to_cmp->fwver.phase < base_fwhdr->fwver.phase)
drivers/scsi/bfa/bfi.h
332
uint8_t phase;
drivers/scsi/bfa/bfi.h
338
uint8_t phase;
drivers/scsi/dc395x.c
1327
u16 phase;
drivers/scsi/dc395x.c
1366
phase = (u16)srb->scsi_phase;
drivers/scsi/dc395x.c
1381
dc395x_statev = dc395x_scsi_phase0[phase];
drivers/scsi/dc395x.c
1390
phase = (u16)scsi_status & PHASEMASK;
drivers/scsi/dc395x.c
1404
dc395x_statev = dc395x_scsi_phase1[phase];
drivers/scsi/elx/libefc_sli/sli4.c
1210
if ((wflags & SLI4_EQE_VALID) != q->phase) {
drivers/scsi/elx/libefc_sli/sli4.c
1231
q->phase ^= (u16)0x1;
drivers/scsi/elx/libefc_sli/sli4.c
1254
if (valid_bit_set != q->phase) {
drivers/scsi/elx/libefc_sli/sli4.c
1275
q->phase ^= (u16)0x1;
drivers/scsi/elx/libefc_sli/sli4.c
3646
req->eq_delay_record[i].phase = cpu_to_le32(shift);
drivers/scsi/elx/libefc_sli/sli4.c
530
q->phase = 1;
drivers/scsi/elx/libefc_sli/sli4.h
3533
u16 phase; /* For if_type = 6, this value toggle
drivers/scsi/elx/libefc_sli/sli4.h
686
__le32 phase;
drivers/scsi/esp_scsi.c
1377
u32 fflags, phase;
drivers/scsi/esp_scsi.c
1391
phase = esp->sreg & ESP_STAT_PMASK;
drivers/scsi/esp_scsi.c
1394
if ((phase == ESP_DOP &&
drivers/scsi/esp_scsi.c
1396
(phase == ESP_DIP &&
drivers/scsi/esp_scsi.c
2097
u8 phase;
drivers/scsi/esp_scsi.c
2129
phase = (esp->sreg & ESP_STAT_PMASK);
drivers/scsi/esp_scsi.c
2131
if (((phase != ESP_DIP && phase != ESP_DOP) &&
drivers/scsi/esp_scsi.c
2824
u8 phase = esp->sreg & ESP_STAT_PMASK;
drivers/scsi/esp_scsi.c
2831
u8 mask = ~(phase == ESP_MIP ? ESP_INTR_FDONE : ESP_INTR_BSERV);
drivers/scsi/esp_scsi.c
2850
if ((esp->sreg & ESP_STAT_PMASK) != phase)
drivers/scsi/esp_scsi.c
2859
if (phase == ESP_MIP)
drivers/scsi/esp_scsi.c
2884
if ((esp->sreg & ESP_STAT_PMASK) != phase)
drivers/scsi/fdomain.c
278
if (scsi_pointer->phase & in_arbitration) {
drivers/scsi/fdomain.c
285
scsi_pointer->phase = in_selection;
drivers/scsi/fdomain.c
294
} else if (scsi_pointer->phase & in_selection) {
drivers/scsi/fdomain.c
306
scsi_pointer->phase = in_other;
drivers/scsi/fdomain.c
374
if (scsi_pointer->phase & disconnect) {
drivers/scsi/fdomain.c
416
scsi_pointer->phase = in_arbitration;
drivers/scsi/fdomain.c
451
fdomain_scsi_pointer(fd->cur_cmd)->phase |= aborted;
drivers/scsi/imm.c
1005
if (imm_scsi_pointer(cmd)->phase)
drivers/scsi/imm.c
74
imm_scsi_pointer(dev->cur_cmd)->phase = 1;
drivers/scsi/imm.c
779
if (imm_scsi_pointer(cmd)->phase > 1)
drivers/scsi/imm.c
804
switch (scsi_pointer->phase) {
drivers/scsi/imm.c
818
scsi_pointer->phase++;
drivers/scsi/imm.c
826
scsi_pointer->phase++;
drivers/scsi/imm.c
836
scsi_pointer->phase++;
drivers/scsi/imm.c
850
scsi_pointer->phase++;
drivers/scsi/imm.c
869
scsi_pointer->phase++;
drivers/scsi/imm.c
885
scsi_pointer->phase++;
drivers/scsi/imm.c
897
scsi_pointer->phase++;
drivers/scsi/imm.c
940
imm_scsi_pointer(cmd)->phase = 0; /* bus free */
drivers/scsi/imm.c
979
switch (imm_scsi_pointer(cmd)->phase) {
drivers/scsi/initio.c
1147
host->phase = host->jsstatus0 & TSS_PH_MASK;
drivers/scsi/initio.c
1305
if (host->phase == MSG_OUT) {
drivers/scsi/initio.c
1385
switch (host->phase) {
drivers/scsi/initio.c
1392
if (host->phase == CMD_OUT)
drivers/scsi/initio.c
1456
switch (host->phase) {
drivers/scsi/initio.c
1543
if ((cnt == 1) && (host->phase == DATA_OUT)) {
drivers/scsi/initio.c
1603
switch (host->phase) {
drivers/scsi/initio.c
1653
switch (host->phase) {
drivers/scsi/initio.c
1742
if (host->phase != DATA_IN) {
drivers/scsi/initio.c
1767
if (host->phase != DATA_OUT) { /* Disable wide CPU to allow read 16 bits */
drivers/scsi/initio.c
1787
if (host->phase == MSG_OUT) {
drivers/scsi/initio.c
1795
if (host->phase == MSG_IN) {
drivers/scsi/initio.c
1800
if (host->phase != MSG_OUT)
drivers/scsi/initio.c
1923
if (host->phase != MSG_IN)
drivers/scsi/initio.c
1938
if (host->phase != MSG_IN)
drivers/scsi/initio.c
2009
if (host->phase != MSG_OUT)
drivers/scsi/initio.c
2032
if (host->phase != MSG_OUT)
drivers/scsi/initio.c
2092
if (host->phase != MSG_IN)
drivers/scsi/initio.c
2093
return host->phase;
drivers/scsi/initio.c
2105
if (host->phase == MSG_OUT) {
drivers/scsi/initio.c
2110
return host->phase;
drivers/scsi/initio.c
2125
return host->phase;
drivers/scsi/initio.c
2138
return host->phase;
drivers/scsi/initio.c
2163
return host->phase;
drivers/scsi/initio.c
2199
return host->phase;
drivers/scsi/initio.c
2360
if (host->phase != MSG_OUT)
drivers/scsi/initio.c
2413
host->phase = host->jsstatus0 & TSS_PH_MASK;
drivers/scsi/initio.c
2449
return host->phase;
drivers/scsi/initio.c
2450
return host->phase;
drivers/scsi/initio.h
487
u8 phase; /* 0F */
drivers/scsi/lpfc/lpfc_hw4.h
1167
uint32_t phase;
drivers/scsi/lpfc/lpfc_sli.c
16075
eq_delay->u.request.eq[cnt].phase = 0;
drivers/scsi/mac53c94.c
150
if (state->phase != idle || state->current_req != NULL)
drivers/scsi/mac53c94.c
175
state->phase = selecting;
drivers/scsi/mac53c94.c
211
intr, stat, seq, state->phase);
drivers/scsi/mac53c94.c
224
intr, stat, seq, state->phase);
drivers/scsi/mac53c94.c
232
intr, stat, seq, state->phase);
drivers/scsi/mac53c94.c
246
switch (state->phase) {
drivers/scsi/mac53c94.c
277
state->phase = dataing;
drivers/scsi/mac53c94.c
282
state->phase = completing;
drivers/scsi/mac53c94.c
317
state->phase = completing;
drivers/scsi/mac53c94.c
328
state->phase = busfreeing;
drivers/scsi/mac53c94.c
337
printk(KERN_DEBUG "don't know about phase %d\n", state->phase);
drivers/scsi/mac53c94.c
351
state->phase = idle;
drivers/scsi/mac53c94.c
54
enum fsc_phase phase; /* what we're currently trying to do */
drivers/scsi/mac53c94.c
95
if (state->phase == idle)
drivers/scsi/mesh.c
1003
ms->phase = idle;
drivers/scsi/mesh.c
1111
if (ms->phase > selecting && (in_8(&mr->bus_status1) & BS1_BSY)) {
drivers/scsi/mesh.c
1213
ms->phase = disconnecting;
drivers/scsi/mesh.c
1364
int phase;
drivers/scsi/mesh.c
1368
phase = in_8(&mr->bus_status0) & BS0_PHASE;
drivers/scsi/mesh.c
1369
if (ms->msgphase == msg_out_xxx && phase == BP_MSGOUT) {
drivers/scsi/mesh.c
1395
switch (phase) {
drivers/scsi/mesh.c
1398
ms->phase = dataing;
drivers/scsi/mesh.c
1402
ms->phase = dataing;
drivers/scsi/mesh.c
1405
ms->phase = commanding;
drivers/scsi/mesh.c
1408
ms->phase = statusing;
drivers/scsi/mesh.c
1431
printk(KERN_DEBUG "mesh: unknown scsi phase %x\n", phase);
drivers/scsi/mesh.c
153
enum mesh_phase phase; /* what we're currently trying to do */
drivers/scsi/mesh.c
1537
switch (ms->phase) {
drivers/scsi/mesh.c
1611
ms->phase = idle;
drivers/scsi/mesh.c
1617
++ms->phase;
drivers/scsi/mesh.c
1642
if (ms->phase == idle)
drivers/scsi/mesh.c
1665
ms->phase, ms->msgphase);
drivers/scsi/mesh.c
1770
if (ms->phase == sleeping)
drivers/scsi/mesh.c
1775
while(ms->phase != idle) {
drivers/scsi/mesh.c
1780
ms->phase = sleeping;
drivers/scsi/mesh.c
1793
if (ms->phase != sleeping)
drivers/scsi/mesh.c
222
tlp->phase = (ms->msgphase << 4) + ms->phase;
drivers/scsi/mesh.c
253
t, lp->bs1, lp->bs0, lp->phase);
drivers/scsi/mesh.c
278
lp->bs1, lp->bs0, lp->phase, lp->tgt);
drivers/scsi/mesh.c
323
ms->phase, ms->msgphase, ms->conn_tgt, ms->data_ptr);
drivers/scsi/mesh.c
391
ms->phase = idle;
drivers/scsi/mesh.c
419
ms->phase = arbitrating;
drivers/scsi/mesh.c
459
if (ms->phase != arbitrating)
drivers/scsi/mesh.c
467
ms->phase = idle;
drivers/scsi/mesh.c
497
if (ms->phase != arbitrating)
drivers/scsi/mesh.c
553
if (ms->phase != idle || ms->current_req != NULL) {
drivers/scsi/mesh.c
555
ms->phase, ms);
drivers/scsi/mesh.c
559
while (ms->phase == idle) {
drivers/scsi/mesh.c
615
ms->phase = idle;
drivers/scsi/mesh.c
757
switch (ms->phase) {
drivers/scsi/mesh.c
812
ms->phase);
drivers/scsi/mesh.c
857
switch (ms->phase) {
drivers/scsi/mesh.c
872
ms->phase = reselecting;
drivers/scsi/mesh.c
879
ms->msgphase, ms->phase, ms->conn_tgt);
drivers/scsi/mesh.c
889
ms->phase = dataing;
drivers/scsi/mesh.c
96
u8 phase;
drivers/scsi/ncr53c8xx.c
5993
int phase = -1;
drivers/scsi/ncr53c8xx.c
6024
phase = (dbc >> 24) & 7;
drivers/scsi/ncr53c8xx.c
6025
if (phase == 7)
drivers/scsi/ncr53c8xx.c
6037
if (phase == 1)
drivers/scsi/ncr53c8xx.h
1226
#define WHEN(phase) (0x00030000 | (phase))
drivers/scsi/ncr53c8xx.h
1227
#define IF(phase) (0x00020000 | (phase))
drivers/scsi/nsp32.c
457
unsigned char phase;
drivers/scsi/nsp32.c
467
phase = nsp32_read1(base, SCSI_BUS_MONITOR);
drivers/scsi/nsp32.c
468
if (phase != BUSMON_BUS_FREE) {
drivers/scsi/nsp32.c
470
show_busphase(phase & BUSMON_PHASE_MASK);
drivers/scsi/nsp32.c
588
unsigned char phase;
drivers/scsi/nsp32.c
604
phase = nsp32_read1(base, SCSI_BUS_MONITOR);
drivers/scsi/nsp32.c
605
if ((phase & BUSMON_BSY) || (phase & BUSMON_SEL)) {
drivers/scsi/pcmcia/nsp_cs.c
1007
phase = nsp_index_read(base, SCSIBUSMON);
drivers/scsi/pcmcia/nsp_cs.c
1055
nsp_msg(KERN_ERR, "CurrentSC==NULL irq_status=0x%x phase=0x%x irq_phase=0x%x this can't be happen. reset everything", irq_status, phase, irq_phase);
drivers/scsi/pcmcia/nsp_cs.c
1085
switch (scsi_pointer->phase) {
drivers/scsi/pcmcia/nsp_cs.c
1088
if ((phase & BUSMON_BSY) == 0) {
drivers/scsi/pcmcia/nsp_cs.c
1108
scsi_pointer->phase = PH_SELECTED;
drivers/scsi/pcmcia/nsp_cs.c
1117
if ((phase & BUSMON_PHASE_MASK) != BUSPHASE_MESSAGE_IN) {
drivers/scsi/pcmcia/nsp_cs.c
1137
if ((scsi_pointer->phase == PH_MSG_IN ||
drivers/scsi/pcmcia/nsp_cs.c
1138
scsi_pointer->phase == PH_MSG_OUT) &&
drivers/scsi/pcmcia/nsp_cs.c
1140
nsp_dbg(NSP_DEBUG_INTR, "normal disconnect irq_status=0x%x, phase=0x%x, irq_phase=0x%x", irq_status, phase, irq_phase);
drivers/scsi/pcmcia/nsp_cs.c
1160
if (phase == 0) {
drivers/scsi/pcmcia/nsp_cs.c
1161
nsp_msg(KERN_DEBUG, "unexpected bus free. irq_status=0x%x, phase=0x%x, irq_phase=0x%x", irq_status, phase, irq_phase);
drivers/scsi/pcmcia/nsp_cs.c
1169
switch (phase & BUSMON_PHASE_MASK) {
drivers/scsi/pcmcia/nsp_cs.c
1172
if ((phase & BUSMON_REQ) == 0) {
drivers/scsi/pcmcia/nsp_cs.c
1177
scsi_pointer->phase = PH_COMMAND;
drivers/scsi/pcmcia/nsp_cs.c
1193
scsi_pointer->phase = PH_DATA;
drivers/scsi/pcmcia/nsp_cs.c
1203
scsi_pointer->phase = PH_DATA;
drivers/scsi/pcmcia/nsp_cs.c
1214
scsi_pointer->phase = PH_STATUS;
drivers/scsi/pcmcia/nsp_cs.c
1224
if ((phase & BUSMON_REQ) == 0) {
drivers/scsi/pcmcia/nsp_cs.c
1228
scsi_pointer->phase = PH_MSG_OUT;
drivers/scsi/pcmcia/nsp_cs.c
1257
if ((phase & BUSMON_REQ) == 0) {
drivers/scsi/pcmcia/nsp_cs.c
1261
scsi_pointer->phase = PH_MSG_IN;
drivers/scsi/pcmcia/nsp_cs.c
231
scsi_pointer->phase = PH_UNDETERMINED;
drivers/scsi/pcmcia/nsp_cs.c
371
unsigned char phase, arbit;
drivers/scsi/pcmcia/nsp_cs.c
375
phase = nsp_index_read(base, SCSIBUSMON);
drivers/scsi/pcmcia/nsp_cs.c
376
if(phase != BUSMON_BUS_FREE) {
drivers/scsi/pcmcia/nsp_cs.c
383
scsi_pointer->phase = PH_ARBSTART;
drivers/scsi/pcmcia/nsp_cs.c
403
scsi_pointer->phase = PH_SELSTART;
drivers/scsi/pcmcia/nsp_cs.c
548
unsigned char phase, i_src;
drivers/scsi/pcmcia/nsp_cs.c
554
phase = nsp_index_read(base, SCSIBUSMON);
drivers/scsi/pcmcia/nsp_cs.c
555
if (phase == 0xff) {
drivers/scsi/pcmcia/nsp_cs.c
564
if ((phase & mask) != 0 && (phase & BUSMON_PHASE_MASK) == current_phase) {
drivers/scsi/pcmcia/nsp_cs.c
577
static int nsp_xfer(struct scsi_cmnd *const SCpnt, int phase)
drivers/scsi/pcmcia/nsp_cs.c
590
ret = nsp_expect_signal(SCpnt, phase, BUSMON_REQ);
drivers/scsi/pcmcia/nsp_cs.c
597
if (len == 1 && scsi_pointer->phase == PH_MSG_OUT) {
drivers/scsi/pcmcia/nsp_cs.c
602
if (phase & BUSMON_IO) {
drivers/scsi/pcmcia/nsp_cs.c
641
scsi_pointer->phase = PH_DATA;
drivers/scsi/pcmcia/nsp_cs.c
964
unsigned char irq_status, irq_phase, phase;
drivers/scsi/pcmcia/nsp_cs.h
322
static int nsp_xfer (struct scsi_cmnd *SCpnt, int phase);
drivers/scsi/pcmcia/nsp_debug.c
148
int i = nsp_scsi_pointer(SCpnt)->phase;
drivers/scsi/pcmcia/sym53c500_cs.c
198
int phase;
drivers/scsi/pcmcia/sym53c500_cs.c
407
if (scp->phase != message_in) { /* Unexpected disconnect */
drivers/scsi/pcmcia/sym53c500_cs.c
422
scp->phase = data_out;
drivers/scsi/pcmcia/sym53c500_cs.c
441
scp->phase = data_in;
drivers/scsi/pcmcia/sym53c500_cs.c
456
scp->phase = command_ph;
drivers/scsi/pcmcia/sym53c500_cs.c
461
scp->phase = status_ph;
drivers/scsi/pcmcia/sym53c500_cs.c
474
scp->phase = message_out;
drivers/scsi/pcmcia/sym53c500_cs.c
481
scp->phase = message_in;
drivers/scsi/pcmcia/sym53c500_cs.c
501
scp->phase = idle;
drivers/scsi/pcmcia/sym53c500_cs.c
566
scp->phase = command_ph;
drivers/scsi/pm8001/pm8001_sas.h
608
u32 phase;/*ret code phase*/
drivers/scsi/ppa.c
689
if (ppa_scsi_pointer(cmd)->phase > 1)
drivers/scsi/ppa.c
69
ppa_scsi_pointer(dev->cur_cmd)->phase = 1;
drivers/scsi/ppa.c
712
switch (scsi_pointer->phase) {
drivers/scsi/ppa.c
747
scsi_pointer->phase++;
drivers/scsi/ppa.c
756
scsi_pointer->phase++;
drivers/scsi/ppa.c
766
scsi_pointer->phase++;
drivers/scsi/ppa.c
781
scsi_pointer->phase++;
drivers/scsi/ppa.c
794
scsi_pointer->phase++;
drivers/scsi/ppa.c
831
ppa_scsi_pointer(cmd)->phase = 0; /* bus free */
drivers/scsi/ppa.c
872
switch (ppa_scsi_pointer(cmd)->phase) {
drivers/scsi/ppa.c
894
if (ppa_scsi_pointer(cmd)->phase)
drivers/scsi/qla2xxx/qla_isr.c
1958
uint phase = mb[2] >> 12 & 0xf;
drivers/scsi/qla2xxx/qla_isr.c
1962
phase >> 1);
drivers/scsi/qlogicfas408.c
100
static int ql_pdma(struct qlogicfas408_priv *priv, int phase, char *request,
drivers/scsi/qlogicfas408.c
106
if (phase & 1) { /* in */
drivers/scsi/qlogicfas408.c
270
unsigned int phase; /* recorded scsi phase */
drivers/scsi/qlogicfas408.c
311
if (reqlen && !((phase = inb(qbase + 4)) & 6)) { /* data phase */
drivers/scsi/qlogicfas408.c
329
if (ql_pdma(priv, phase, buf, sg->length))
drivers/scsi/sym53c8xx_2/sym_defs.h
709
#define WHEN(phase) (0x00030000 | (phase))
drivers/scsi/sym53c8xx_2/sym_defs.h
710
#define IF(phase) (0x00020000 | (phase))
drivers/scsi/sym53c8xx_2/sym_hipd.c
2305
int phase = cmd & 7;
drivers/scsi/sym53c8xx_2/sym_hipd.c
2331
if ((cmd & 0xc0) || !(phase & 1) || !(sbcl & 0x8))
drivers/scsi/sym53c8xx_2/sym_hipd.c
2343
np->msgout[0] = (phase == 7) ? M_PARITY : M_ID_ERROR;
drivers/scsi/sym53c8xx_2/sym_hipd.c
2352
if (phase == 1 || phase == 5) {
drivers/scsi/sym53c8xx_2/sym_hipd.c
2365
else if (phase == 7) /* We definitely cannot handle parity errors */
drivers/scsi/wd33c93.c
492
scsi_pointer->phase = 0; /* assume no disconnect */
drivers/scsi/wd33c93.c
509
WD33C93_scsi_pointer(prev)->phase = 1;
drivers/scsi/wd33c93.c
517
scsi_pointer->phase = 1;
drivers/scsi/wd33c93.c
525
write_wd33c93(regs, WD_SOURCE_ID, scsi_pointer->phase ? SRCID_ER : 0);
drivers/scsi/wd33c93.c
594
if (scsi_pointer->phase == 0 && hostdata->no_dma == 0) {
drivers/scsi/wd33c93.c
621
printk("%s)EX-2 ", scsi_pointer->phase ? "d:" : ""))
drivers/scsi/wd33c93.c
722
(hostdata->level2 == L2_BASIC && scsi_pointer->phase == 0)) {
drivers/scsi/wd33c93.c
834
if (WD33C93_scsi_pointer(cmd)->phase)
drivers/scsi/zorro_esp.c
263
u8 phase = esp->sreg & ESP_STAT_PMASK;
drivers/scsi/zorro_esp.c
270
if (phase == ESP_MIP && addr == esp->command_block_dma) {
drivers/scsi/zorro_esp.c
314
u8 phase = esp->sreg & ESP_STAT_PMASK;
drivers/scsi/zorro_esp.c
317
if (phase == ESP_MIP && addr == esp->command_block_dma) {
drivers/scsi/zorro_esp.c
359
u8 phase = esp->sreg & ESP_STAT_PMASK;
drivers/scsi/zorro_esp.c
362
if (phase == ESP_MIP && addr == esp->command_block_dma) {
drivers/scsi/zorro_esp.c
405
u8 phase = esp->sreg & ESP_STAT_PMASK;
drivers/scsi/zorro_esp.c
409
if (phase == ESP_MIP && addr == esp->command_block_dma) {
drivers/scsi/zorro_esp.c
456
u8 phase = esp->sreg & ESP_STAT_PMASK;
drivers/scsi/zorro_esp.c
459
if (phase == ESP_MIP && addr == esp->command_block_dma) {
drivers/scsi/zorro_esp.c
498
u8 phase = esp->sreg & ESP_STAT_PMASK;
drivers/scsi/zorro_esp.c
502
if (phase == ESP_MIP && addr == esp->command_block_dma) {
drivers/soc/mediatek/mtk-svs.c
1280
enum svsb_phase phase)
drivers/soc/mediatek/mtk-svs.c
1286
svsb->reg_data[phase][rg_i] = svs_readl_relaxed(svsp, rg_i);
drivers/soc/mediatek/mtk-svs.c
1306
svsb->phase = SVSB_PHASE_ERROR;
drivers/soc/mediatek/mtk-svs.c
1324
svsb->phase = SVSB_PHASE_INIT01;
drivers/soc/mediatek/mtk-svs.c
1353
svsb->phase = SVSB_PHASE_INIT02;
drivers/soc/mediatek/mtk-svs.c
1368
svsb->phase = SVSB_PHASE_MON;
drivers/soc/mediatek/mtk-svs.c
1417
if (svsb->phase == SVSB_PHASE_INIT01 ||
drivers/soc/mediatek/mtk-svs.c
1418
svsb->phase == SVSB_PHASE_INIT02)
drivers/soc/mediatek/mtk-svs.c
522
enum svsb_phase phase;
drivers/soc/mediatek/mtk-svs.c
642
svsb->phase = SVSB_PHASE_ERROR;
drivers/soc/mediatek/mtk-svs.c
651
if (svsb->phase == SVSB_PHASE_MON && (bdata->type == SVSB_TYPE_HIGH ||
drivers/soc/mediatek/mtk-svs.c
660
switch (svsb->phase) {
drivers/soc/mediatek/mtk-svs.c
675
dev_err(svsb->dev, "unknown phase: %u\n", svsb->phase);
drivers/soc/mediatek/mtk-svs.c
712
svsb->phase = SVSB_PHASE_ERROR;
drivers/soc/mediatek/mtk-svs.c
765
switch (svsb->phase) {
drivers/soc/mediatek/mtk-svs.c
944
if (svsb->phase == SVSB_PHASE_MON &&
drivers/staging/iio/frequency/ad9832.c
153
unsigned long addr, unsigned long phase)
drivers/staging/iio/frequency/ad9832.c
158
if (phase >= BIT(AD9832_PHASE_BITS))
drivers/staging/iio/frequency/ad9832.c
161
put_unaligned_be16(phase, phase_bytes);
drivers/staging/iio/frequency/ad9834.c
133
unsigned long addr, unsigned long phase)
drivers/staging/iio/frequency/ad9834.c
135
if (phase >= BIT(AD9834_PHASE_BITS))
drivers/staging/iio/frequency/ad9834.c
137
st->data = cpu_to_be16(addr | phase);
drivers/staging/media/ipu3/ipu3-css-params.c
49
int tap, phase, phase_sum_left, phase_sum_right;
drivers/staging/media/ipu3/ipu3-css-params.c
55
for (phase = 0; phase < IMGU_SCALER_PHASES; phase++) {
drivers/staging/media/ipu3/ipu3-css-params.c
56
phase_taps = phase * IMGU_SCALER_FILTER_TAPS;
drivers/staging/media/ipu3/ipu3-css-params.c
72
for (phase = 0; phase < IMGU_SCALER_PHASES; phase++) {
drivers/staging/media/ipu3/ipu3-css-params.c
73
phase_taps = phase * IMGU_SCALER_FILTER_TAPS;
drivers/staging/media/ipu3/ipu3-css-params.c
77
((tap * (coeffs_size / taps)) + phase) - 1];
drivers/target/iscsi/iscsi_target_parameters.c
1176
int phase,
drivers/target/iscsi/iscsi_target_parameters.c
1213
if (!phase)
drivers/target/iscsi/iscsi_target_parameters.c
1216
if (!(param->phase & phase)) {
drivers/target/iscsi/iscsi_target_parameters.c
1219
switch (phase) {
drivers/target/iscsi/iscsi_target_parameters.c
1238
u8 phase,
drivers/target/iscsi/iscsi_target_parameters.c
1248
if (!(param->phase & phase))
drivers/target/iscsi/iscsi_target_parameters.c
1265
if (!(param->phase & phase))
drivers/target/iscsi/iscsi_target_parameters.c
1305
u8 phase,
drivers/target/iscsi/iscsi_target_parameters.c
1332
if (phase & PHASE_SECURITY) {
drivers/target/iscsi/iscsi_target_parameters.c
1339
param = iscsi_check_key(key, phase, sender, param_list);
drivers/target/iscsi/iscsi_target_parameters.c
1399
u8 phase,
drivers/target/iscsi/iscsi_target_parameters.c
1411
if (iscsi_enforce_integrity_rules(phase, param_list) < 0)
drivers/target/iscsi/iscsi_target_parameters.c
1420
(param->phase & phase)) {
drivers/target/iscsi/iscsi_target_parameters.c
1435
(param->phase & phase)) {
drivers/target/iscsi/iscsi_target_parameters.c
555
new_param->phase = param->phase;
drivers/target/iscsi/iscsi_target_parameters.c
71
char *name, char *value, u8 phase, u8 scope, u8 sender,
drivers/target/iscsi/iscsi_target_parameters.c
95
param->phase = phase;
drivers/target/iscsi/iscsi_target_parameters.h
18
u8 phase;
drivers/target/iscsi/iscsi_target_parameters.h
206
#define IS_PHASE_SECURITY(p) ((p)->phase & PHASE_SECURITY)
drivers/target/iscsi/iscsi_target_parameters.h
207
#define IS_PHASE_OPERATIONAL(p) ((p)->phase & PHASE_OPERATIONAL)
drivers/target/iscsi/iscsi_target_parameters.h
208
#define IS_PHASE_DECLARATIVE(p) ((p)->phase & PHASE_DECLARATIVE)
drivers/target/iscsi/iscsi_target_parameters.h
209
#define IS_PHASE_FFP0(p) ((p)->phase & PHASE_FFP0)
drivers/usb/atm/cxacru.c
985
char *phase, const struct firmware **fw_p)
drivers/usb/atm/cxacru.c
991
sprintf(buf, "cxacru-%s.bin", phase);
drivers/usb/atm/cxacru.c
995
usb_dbg(usbatm, "no stage %s firmware found\n", phase);
drivers/usb/atm/speedtch.c
349
int phase, const struct firmware **fw_p)
drivers/usb/atm/speedtch.c
357
sprintf(buf, "speedtch-%d.bin.%x.%02x", phase, major_revision, minor_revision);
drivers/usb/atm/speedtch.c
361
sprintf(buf, "speedtch-%d.bin.%x", phase, major_revision);
drivers/usb/atm/speedtch.c
365
sprintf(buf, "speedtch-%d.bin", phase);
drivers/usb/atm/speedtch.c
369
usb_err(usbatm, "%s: no stage %d firmware found!\n", __func__, phase);
drivers/usb/atm/speedtch.c
375
usb_info(usbatm, "found stage %d firmware %s\n", phase, buf);
drivers/usb/dwc3/debug.h
316
int phase = DEPEVT_STATUS_CONTROL_PHASE(event->status);
drivers/usb/dwc3/debug.h
318
switch (phase) {
drivers/usb/host/ehci-q.c
807
qh->ps.phase = NO_FRAME;
drivers/usb/host/ehci-sched.c
1010
stream->ps.phase = NO_FRAME;
drivers/usb/host/ehci-sched.c
1311
if (stream->ps.phase == NO_FRAME) /* Bandwidth wasn't reserved */
drivers/usb/host/ehci-sched.c
1494
if (stream->ps.phase == NO_FRAME) {
drivers/usb/host/ehci-sched.c
1534
stream->ps.phase = (start >> 3) &
drivers/usb/host/ehci-sched.c
1536
stream->ps.bw_phase = stream->ps.phase &
drivers/usb/host/ehci-sched.c
1544
start = (stream->ps.phase << 3) + stream->ps.phase_uf;
drivers/usb/host/ehci-sched.c
201
ps->phase, ps->phase_uf, ps->period,
drivers/usb/host/ehci-sched.c
215
if (qh->ps.phase == NO_FRAME) /* Bandwidth wasn't reserved */
drivers/usb/host/ehci-sched.c
529
qh, qh->ps.phase, qh->ps.usecs, qh->ps.c_usecs);
drivers/usb/host/ehci-sched.c
535
for (i = qh->ps.phase; i < ehci->periodic_size; i += period) {
drivers/usb/host/ehci-sched.c
610
for (i = qh->ps.phase; i < ehci->periodic_size; i += period)
drivers/usb/host/ehci-sched.c
622
qh, qh->ps.phase, qh->ps.usecs, qh->ps.c_usecs);
drivers/usb/host/ehci-sched.c
846
if (qh->ps.phase != NO_FRAME) {
drivers/usb/host/ehci-sched.c
886
qh->ps.phase = (qh->ps.period ? ehci->random_frame &
drivers/usb/host/ehci-sched.c
888
qh->ps.bw_phase = qh->ps.phase & (qh->ps.bw_period - 1);
drivers/usb/host/ehci.h
55
u16 phase; /* actual phase, frame part */
drivers/usb/host/uhci-debug.c
188
space, "", qh->period, qh->phase, qh->load,
drivers/usb/host/uhci-debug.c
192
space, "", qh->period, qh->phase, qh->load);
drivers/usb/host/uhci-hcd.h
171
short phase; /* Between 0 and period-1 */
drivers/usb/host/uhci-q.c
1102
qh->phase = (qh->period / 2) & (MAX_PHASE - 1);
drivers/usb/host/uhci-q.c
1273
qh->phase = -1; /* Find the best phase */
drivers/usb/host/uhci-q.c
1280
frame = qh->phase;
drivers/usb/host/uhci-q.c
610
static int uhci_highest_load(struct uhci_hcd *uhci, int phase, int period)
drivers/usb/host/uhci-q.c
612
int highest_load = uhci->load[phase];
drivers/usb/host/uhci-q.c
614
for (phase += period; phase < MAX_PHASE; phase += period)
drivers/usb/host/uhci-q.c
615
highest_load = max_t(int, highest_load, uhci->load[phase]);
drivers/usb/host/uhci-q.c
629
if (qh->phase >= 0)
drivers/usb/host/uhci-q.c
630
minimax_load = uhci_highest_load(uhci, qh->phase, qh->period);
drivers/usb/host/uhci-q.c
632
int phase, load;
drivers/usb/host/uhci-q.c
635
qh->phase = 0;
drivers/usb/host/uhci-q.c
636
minimax_load = uhci_highest_load(uhci, qh->phase, qh->period);
drivers/usb/host/uhci-q.c
637
for (phase = 1; phase < max_phase; ++phase) {
drivers/usb/host/uhci-q.c
638
load = uhci_highest_load(uhci, phase, qh->period);
drivers/usb/host/uhci-q.c
641
qh->phase = phase;
drivers/usb/host/uhci-q.c
650
qh->period, qh->phase, minimax_load, qh->load);
drivers/usb/host/uhci-q.c
665
for (i = qh->phase; i < MAX_PHASE; i += qh->period) {
drivers/usb/host/uhci-q.c
686
qh->period, qh->phase, load);
drivers/usb/host/uhci-q.c
698
for (i = qh->phase; i < MAX_PHASE; i += qh->period) {
drivers/usb/host/uhci-q.c
719
qh->period, qh->phase, load);
fs/ceph/debugfs.c
404
enum ceph_client_reset_phase phase = CEPH_CLIENT_RESET_IDLE;
fs/ceph/debugfs.c
422
phase = st->phase;
fs/ceph/debugfs.c
430
seq_printf(s, "phase: %s\n", ceph_reset_phase_name(phase));
fs/ceph/mds_client.c
5299
const char *ceph_reset_phase_name(enum ceph_client_reset_phase phase)
fs/ceph/mds_client.c
5301
switch (phase) {
fs/ceph/mds_client.c
5365
if (st->phase != CEPH_CLIENT_RESET_IDLE) {
fs/ceph/mds_client.c
5397
st->phase = CEPH_CLIENT_RESET_IDLE;
fs/ceph/mds_client.c
5490
st->phase = CEPH_CLIENT_RESET_DRAINING;
fs/ceph/mds_client.c
5612
st->phase = CEPH_CLIENT_RESET_TEARDOWN;
fs/ceph/mds_client.c
5742
if (st->phase != CEPH_CLIENT_RESET_IDLE) {
fs/ceph/mds_client.c
5747
st->phase = CEPH_CLIENT_RESET_QUIESCING;
fs/ceph/mds_client.c
5758
st->phase = CEPH_CLIENT_RESET_IDLE;
fs/ceph/mds_client.c
6856
if (mdsc->reset_state.phase != CEPH_CLIENT_RESET_IDLE) {
fs/ceph/mds_client.c
6857
mdsc->reset_state.phase = CEPH_CLIENT_RESET_IDLE;
fs/ceph/mds_client.h
110
enum ceph_client_reset_phase phase; /* current reset phase */
fs/ceph/mds_client.h
123
return READ_ONCE(st->phase) == CEPH_CLIENT_RESET_IDLE;
fs/ceph/mds_client.h
621
extern const char *ceph_reset_phase_name(enum ceph_client_reset_phase phase);
fs/f2fs/gc.c
1048
int phase = 0;
fs/f2fs/gc.c
1058
if (fggc && phase == 2)
fs/f2fs/gc.c
1074
if (phase == 0) {
fs/f2fs/gc.c
1080
if (phase == 1) {
fs/f2fs/gc.c
1112
if (++phase < 3) {
fs/f2fs/gc.c
1593
int phase = 0;
fs/f2fs/gc.c
1622
if (phase == 0) {
fs/f2fs/gc.c
1628
if (phase == 1) {
fs/f2fs/gc.c
1637
if (phase == 2) {
fs/f2fs/gc.c
1644
if (phase == 3) {
fs/f2fs/gc.c
1755
if (++phase < 5) {
fs/fs_context.c
549
fc->phase = FS_CONTEXT_AWAITING_RECONF;
fs/fs_context.c
556
if (fc->phase != FS_CONTEXT_AWAITING_RECONF)
fs/fs_context.c
562
fc->phase = FS_CONTEXT_FAILED;
fs/fs_context.c
566
fc->phase = FS_CONTEXT_RECONF_PARAMS;
fs/fsopen.c
147
fc->phase = FS_CONTEXT_CREATE_PARAMS;
fs/fsopen.c
200
fc->phase = FS_CONTEXT_RECONF_PARAMS;
fs/fsopen.c
222
if (fc->phase != FS_CONTEXT_CREATE_PARAMS)
fs/fsopen.c
228
fc->phase = FS_CONTEXT_CREATING;
fs/fsopen.c
233
fc->phase = FS_CONTEXT_FAILED;
fs/fsopen.c
241
fc->phase = FS_CONTEXT_FAILED;
fs/fsopen.c
247
fc->phase = FS_CONTEXT_AWAITING_MOUNT;
fs/fsopen.c
256
if (fc->phase != FS_CONTEXT_RECONF_PARAMS)
fs/fsopen.c
259
fc->phase = FS_CONTEXT_RECONFIGURING;
fs/fsopen.c
263
fc->phase = FS_CONTEXT_FAILED;
fs/fsopen.c
271
fc->phase = FS_CONTEXT_FAILED;
fs/fsopen.c
299
if (fc->phase != FS_CONTEXT_CREATE_PARAMS &&
fs/fsopen.c
300
fc->phase != FS_CONTEXT_RECONF_PARAMS)
fs/namespace.c
4500
if (fc->phase != FS_CONTEXT_AWAITING_MOUNT)
include/linux/clk.h
274
static inline long clk_set_phase(struct clk *clk, int phase)
include/linux/fs_context.h
108
enum fs_context_phase phase:8; /* The phase the context is in */
include/linux/greybus/greybus_protocols.h
60
__u8 phase;
include/linux/greybus/hd.h
30
u8 phase, unsigned int timeout);
include/linux/mmc/host.h
100
struct mmc_clk_phase phase[MMC_NUM_CLK_PHASES];
include/linux/parport.h
179
volatile enum ieee1284_phase phase;
include/linux/ptp_clock_kernel.h
206
int (*adjphase)(struct ptp_clock_info *ptp, s32 phase);
include/net/netfilter/nf_tables.h
1035
enum nft_trans_phase phase);
include/net/netfilter/nf_tables.h
1504
enum nft_trans_phase phase);
include/net/netfilter/nf_tables.h
680
enum nft_trans_phase phase);
include/net/netfilter/nf_tables.h
965
enum nft_trans_phase phase);
include/scsi/scsi_cmnd.h
48
volatile int phase;
include/trace/events/clk.h
200
TP_PROTO(struct clk_core *core, int phase),
include/trace/events/clk.h
202
TP_ARGS(core, phase),
include/trace/events/clk.h
206
__field( int, phase )
include/trace/events/clk.h
211
__entry->phase = phase;
include/trace/events/clk.h
214
TP_printk("%s %d", __get_str(name), (int)__entry->phase)
include/trace/events/clk.h
219
TP_PROTO(struct clk_core *core, int phase),
include/trace/events/clk.h
221
TP_ARGS(core, phase)
include/trace/events/clk.h
226
TP_PROTO(struct clk_core *core, int phase),
include/trace/events/clk.h
228
TP_ARGS(core, phase)
include/trace/events/f2fs.h
1604
TP_PROTO(struct super_block *sb, int reason, u16 phase),
include/trace/events/f2fs.h
1606
TP_ARGS(sb, reason, phase),
include/trace/events/f2fs.h
1611
__field(u16, phase)
include/trace/events/f2fs.h
1617
__entry->phase = phase;
include/trace/events/f2fs.h
1623
show_cp_phase(__entry->phase))
include/trace/events/f2fs.h
181
#define show_cp_phase(phase) \
include/trace/events/f2fs.h
182
__print_symbolic(phase, \
include/uapi/linux/input.h
411
__u16 phase;
include/uapi/linux/ptp_clock.h
131
struct ptp_clock_time phase;
include/uapi/rdma/bnxt_re-abi.h
119
__u32 phase;
kernel/bpf/btf.c
1637
if (env->phase != CHECK_META)
kernel/bpf/btf.c
1675
if (env->phase != CHECK_META)
kernel/bpf/btf.c
323
enum verifier_phase phase;
kernel/bpf/btf.c
5519
env->phase++;
kernel/torture.c
319
static void torture_online_all(char *phase)
kernel/torture.c
331
__func__, phase, torture_type, cpu, ret);
lib/zstd/compress/zstd_cwksp.h
168
ZSTD_cwksp_alloc_phase_e phase;
lib/zstd/compress/zstd_cwksp.h
303
ZSTD_cwksp_internal_advance_phase(ZSTD_cwksp* ws, ZSTD_cwksp_alloc_phase_e phase)
lib/zstd/compress/zstd_cwksp.h
305
assert(phase >= ws->phase);
lib/zstd/compress/zstd_cwksp.h
306
if (phase > ws->phase) {
lib/zstd/compress/zstd_cwksp.h
308
if (ws->phase < ZSTD_cwksp_alloc_aligned_init_once &&
lib/zstd/compress/zstd_cwksp.h
309
phase >= ZSTD_cwksp_alloc_aligned_init_once) {
lib/zstd/compress/zstd_cwksp.h
327
ws->phase = phase;
lib/zstd/compress/zstd_cwksp.h
345
ZSTD_cwksp_reserve_internal(ZSTD_cwksp* ws, size_t bytes, ZSTD_cwksp_alloc_phase_e phase)
lib/zstd/compress/zstd_cwksp.h
348
if (ZSTD_isError(ZSTD_cwksp_internal_advance_phase(ws, phase)) || bytes == 0) {
lib/zstd/compress/zstd_cwksp.h
413
const ZSTD_cwksp_alloc_phase_e phase = ZSTD_cwksp_alloc_aligned_init_once;
lib/zstd/compress/zstd_cwksp.h
420
if(ws->phase < phase) {
lib/zstd/compress/zstd_cwksp.h
421
if (ZSTD_isError(ZSTD_cwksp_internal_advance_phase(ws, phase))) {
lib/zstd/compress/zstd_cwksp.h
465
if (ws->phase != ZSTD_cwksp_alloc_objects || end > ws->workspaceEnd) {
lib/zstd/compress/zstd_cwksp.h
551
if (ws->phase > ZSTD_cwksp_alloc_aligned_init_once) {
lib/zstd/compress/zstd_cwksp.h
552
ws->phase = ZSTD_cwksp_alloc_aligned_init_once;
lib/zstd/compress/zstd_cwksp.h
579
ws->phase = ZSTD_cwksp_alloc_objects;
net/netfilter/nf_tables_api.c
5992
enum nft_trans_phase phase)
net/netfilter/nf_tables_api.c
5996
switch (phase) {
net/netfilter/nf_tables_api.c
6025
phase == NFT_TRANS_COMMIT);
net/netfilter/nf_tables_api.c
705
enum nft_trans_phase phase)
net/netfilter/nf_tables_api.c
712
expr->ops->deactivate(ctx, expr, phase);
net/netfilter/nf_tables_api.c
8820
enum nft_trans_phase phase)
net/netfilter/nf_tables_api.c
8822
switch (phase) {
net/netfilter/nft_dynset.c
349
enum nft_trans_phase phase)
net/netfilter/nft_dynset.c
353
nf_tables_deactivate_set(ctx, priv->set, &priv->binding, phase);
net/netfilter/nft_flow_offload.c
182
enum nft_trans_phase phase)
net/netfilter/nft_flow_offload.c
186
nf_tables_deactivate_flowtable(ctx, priv->flowtable, phase);
net/netfilter/nft_immediate.c
130
enum nft_trans_phase phase)
net/netfilter/nft_immediate.c
139
nft_rule_expr_deactivate(&chain_ctx, rule, phase);
net/netfilter/nft_immediate.c
144
enum nft_trans_phase phase)
net/netfilter/nft_immediate.c
158
switch (phase) {
net/netfilter/nft_immediate.c
164
nft_immediate_chain_deactivate(ctx, chain, phase);
net/netfilter/nft_immediate.c
168
nft_immediate_chain_deactivate(ctx, chain, phase);
net/netfilter/nft_immediate.c
180
if (phase == NFT_TRANS_COMMIT)
net/netfilter/nft_lookup.c
201
enum nft_trans_phase phase)
net/netfilter/nft_lookup.c
205
nf_tables_deactivate_set(ctx, priv->set, &priv->binding, phase);
net/netfilter/nft_objref.c
103
if (phase == NFT_TRANS_COMMIT)
net/netfilter/nft_objref.c
206
enum nft_trans_phase phase)
net/netfilter/nft_objref.c
210
nf_tables_deactivate_set(ctx, priv->set, &priv->binding, phase);
net/netfilter/nft_objref.c
99
enum nft_trans_phase phase)
sound/firewire/amdtp-stream.c
383
unsigned int phase = state;
sound/firewire/amdtp-stream.c
395
desc->data_blocks = 5 + ((phase & 1) ^ (phase == 0 || phase >= 40));
sound/firewire/amdtp-stream.c
398
desc->data_blocks = 11 * (sfc >> 1) + (phase == 0);
sound/firewire/amdtp-stream.c
399
if (++phase >= (80 >> (sfc >> 1)))
sound/firewire/amdtp-stream.c
400
phase = 0;
sound/firewire/amdtp-stream.c
401
state = phase;
sound/firewire/amdtp-stream.c
429
unsigned int phase = *syt_offset_state;
sound/firewire/amdtp-stream.c
430
unsigned int index = phase % 13;
sound/firewire/amdtp-stream.c
434
phase == 146);
sound/firewire/amdtp-stream.c
435
if (++phase >= 147)
sound/firewire/amdtp-stream.c
436
phase = 0;
sound/firewire/amdtp-stream.c
437
*syt_offset_state = phase;
sound/soc/mediatek/mt8188/mt8188-mt6359.c
377
int phase;
sound/soc/mediatek/mt8188/mt8188-mt6359.c
423
for (phase = 0;
sound/soc/mediatek/mt8188/mt8188-mt6359.c
424
phase <= mtkaif_calibration_num_phase && mtkaif_calibration_ok;
sound/soc/mediatek/mt8188/mt8188-mt6359.c
425
phase++) {
sound/soc/mediatek/mt8188/mt8188-mt6359.c
427
phase, phase, phase);
sound/soc/mediatek/mt8188/mt8188-mt6359.c
459
if (phase == 0) {
sound/soc/mediatek/mt8188/mt8188-mt6359.c
466
mtkaif_chosen_phase[MT8188_MTKAIF_MISO_0] = phase - 1;
sound/soc/mediatek/mt8188/mt8188-mt6359.c
472
mtkaif_chosen_phase[MT8188_MTKAIF_MISO_1] = phase - 1;
sound/soc/mediatek/mt8192/mt8192-mt6359-rt1015-rt5682.c
158
int phase;
sound/soc/mediatek/mt8192/mt8192-mt6359-rt1015-rt5682.c
189
for (phase = 0;
sound/soc/mediatek/mt8192/mt8192-mt6359-rt1015-rt5682.c
190
phase <= afe_priv->mtkaif_calibration_num_phase &&
sound/soc/mediatek/mt8192/mt8192-mt6359-rt1015-rt5682.c
192
phase++) {
sound/soc/mediatek/mt8192/mt8192-mt6359-rt1015-rt5682.c
194
phase, phase, phase);
sound/soc/mediatek/mt8192/mt8192-mt6359-rt1015-rt5682.c
234
if (phase == 0) {
sound/soc/mediatek/mt8192/mt8192-mt6359-rt1015-rt5682.c
242
afe_priv->mtkaif_chosen_phase[0] = phase - 1;
sound/soc/mediatek/mt8192/mt8192-mt6359-rt1015-rt5682.c
248
afe_priv->mtkaif_chosen_phase[1] = phase - 1;
sound/soc/mediatek/mt8192/mt8192-mt6359-rt1015-rt5682.c
254
afe_priv->mtkaif_chosen_phase[2] = phase - 1;
sound/soc/mediatek/mt8195/mt8195-mt6359.c
173
int phase;
sound/soc/mediatek/mt8195/mt8195-mt6359.c
201
for (phase = 0;
sound/soc/mediatek/mt8195/mt8195-mt6359.c
202
phase <= mtkaif_calibration_num_phase && mtkaif_calibration_ok;
sound/soc/mediatek/mt8195/mt8195-mt6359.c
203
phase++) {
sound/soc/mediatek/mt8195/mt8195-mt6359.c
205
phase, phase, phase);
sound/soc/mediatek/mt8195/mt8195-mt6359.c
242
if (phase == 0) {
sound/soc/mediatek/mt8195/mt8195-mt6359.c
250
mtkaif_chosen_phase[MT8195_MTKAIF_MISO_0] = phase - 1;
sound/soc/mediatek/mt8195/mt8195-mt6359.c
256
mtkaif_chosen_phase[MT8195_MTKAIF_MISO_1] = phase - 1;
sound/soc/mediatek/mt8195/mt8195-mt6359.c
262
mtkaif_chosen_phase[MT8195_MTKAIF_MISO_2] = phase - 1;
sound/usb/card.h
116
unsigned int phase; /* phase accumulator */
sound/usb/endpoint.c
1386
ep->phase = 0;
sound/usb/endpoint.c
1581
ep->phase = 0;
sound/usb/endpoint.c
166
unsigned int phase;
sound/usb/endpoint.c
173
phase = (ep->phase & 0xffff) + (ep->freqm << ep->datainterval);
sound/usb/endpoint.c
174
ret = min(phase >> 16, ep->maxframesize);
sound/usb/endpoint.c
178
ep->phase = phase;
tools/testing/selftests/bpf/progs/btf_dump_test_case_padding.c
168
short phase;
tools/testing/selftests/kvm/x86/evmcs_smm_controls_test.c
38
static inline void sync_with_host(u64 phase)
tools/testing/selftests/kvm/x86/evmcs_smm_controls_test.c
41
: "+a" (phase));
tools/testing/selftests/kvm/x86/smm_test.c
43
static inline void sync_with_host(u64 phase)
tools/testing/selftests/kvm/x86/smm_test.c
46
: "+a" (phase));
tools/testing/selftests/ptp/testptp.c
530
perout_request.phase.sec = perout_phase / NSEC_PER_SEC;
tools/testing/selftests/ptp/testptp.c
531
perout_request.phase.nsec = perout_phase % NSEC_PER_SEC;
