CONFIG
config = REG_GET_FLD(VPU_HW_BTRS_LNL_TILE_FUSE, CONFIG, fuse);
val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2, CONFIG, wp->cfg, val);
val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2, CONFIG, wp->cfg, val);
cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1;
cmdq_mask = CONFIG | DATA_ID;
SR(dispc, CONFIG);
RR(dispc, CONFIG);
#define DEFINE_SRIOV_GT_GRP_CFG_DEBUGFS_ATTRIBUTE(CONFIG) \
static int sched_groups_##CONFIG##_show(struct seq_file *m, void *data) \
xe_gt_sriov_pf_config_get_groups_##CONFIG); \
static int sched_groups_##CONFIG##_open(struct inode *inode, struct file *file) \
return single_open(file, sched_groups_##CONFIG##_show, \
static ssize_t sched_groups_##CONFIG##_write(struct file *file, \
xe_gt_sriov_pf_config_set_groups_##CONFIG); \
static const struct file_operations sched_groups_##CONFIG##_fops = { \
.open = sched_groups_##CONFIG##_open, \
.write = sched_groups_##CONFIG##_write, \
#define DEFINE_SRIOV_GT_CONFIG_DEBUGFS_ATTRIBUTE(CONFIG, TYPE, FORMAT) \
static int CONFIG##_set(void *data, u64 val) \
xe_gt_sriov_pf_config_set_##CONFIG(gt, vfid, val); \
static int CONFIG##_get(void *data, u64 *val) \
*val = xe_gt_sriov_pf_config_get_##CONFIG(gt, vfid); \
DEFINE_DEBUGFS_ATTRIBUTE(CONFIG##_fops, CONFIG##_get, CONFIG##_set, FORMAT)
#define DEFINE_SRIOV_TILE_CONFIG_DEBUGFS_ATTRIBUTE(NAME, CONFIG, TYPE, FORMAT) \
xe_gt_sriov_pf_config_set_##CONFIG(gt, vfid, val); \
*val = xe_gt_sriov_pf_config_get_##CONFIG(gt, vfid); \
REG_CMDQV(cmdqv, CONFIG),
REG_VINTF(vintf, CONFIG),
REG_VCMDQ_PAGE0(vcmdq, CONFIG),
writel(regval, REG_VINTF(vintf, CONFIG));
vintf->hyp_own = !!(VINTF_HYP_OWN & readl(REG_VINTF(vintf, CONFIG)));
regval = readl_relaxed(REG_CMDQV(cmdqv, CONFIG));
ret = mt312_writereg(state, CONFIG,
ret = mt312_readreg(state, CONFIG, &config_val);
ret = mt312_readreg(state, CONFIG, &config);
ret = mt312_writereg(state, CONFIG, config & 0x7f);
(mt352_read_register(state, CONFIG) & 0x20) == 0) {
write_i2c_reg(pd->regs, CONFIG, pd->config);
write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM);
write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM | PM_LUT_SEL);
write_i2c_reg(pd->regs, CONFIG, pd->config); /* ACQ_MODE_EVEN */
request = CONFIG;
request = CONFIG;
static const u8 config[] = { CONFIG, 0x3d };
writel_relaxed(nand->config, ctrl->regs + CONFIG);
writel_relaxed(nand->config_ecc, ctrl->regs + CONFIG);
writel_relaxed(nand->config, ctrl->regs + CONFIG);
outw( inw( ioaddr + CONFIG ) & ~CFG_AUI_SELECT,
ioaddr + CONFIG );
outw( inw( ioaddr + CONFIG ) | CFG_AUI_SELECT,
ioaddr + CONFIG );
configuration_register = inw( ioaddr + CONFIG );
outw(smc->cfg | CFG_AUI_SELECT, ioaddr + CONFIG);
outw(smc->cfg, ioaddr + CONFIG);
media |= (inw(ioaddr + CONFIG) & CFG_AUI_SELECT) ? 2 : 1;
tmp = inw(ioaddr + CONFIG);
s = inb(ioaddr + CONFIG);
outb(s, ioaddr + CONFIG);
smc->cfg = inw(ioaddr + CONFIG) & ~CFG_AUI_SELECT;
ath_dbg(common, CONFIG, "Force rf_pwd_icsyndiv to %1d on %4d\n",
ath_dbg(common, CONFIG, "Added interface at beacon slot: %d\n",
ath_dbg(common, CONFIG, "Removing interface at beacon slot: %d\n",
ath_dbg(common, CONFIG,
ath_dbg(common, CONFIG, "tsfadjust is: %lld for bslot: %d\n",
ath_dbg(common, CONFIG, "Unsupported beaconing mode\n");
ath_dbg(common, CONFIG, "Set channel: %d MHz width: %d\n",
ath_dbg(common, CONFIG, "TX streams %d, RX streams: %d\n",
ath_dbg(common, CONFIG, "spectral scan: background mode enabled\n");
ath_dbg(common, CONFIG, "spectral scan: channel scan mode enabled\n");
ath_dbg(common, CONFIG, "spectral scan: manual mode enabled\n");
ath_dbg(common, CONFIG, "spectral scan: disabled\n");
ath_dbg(common, CONFIG, "Enable WLAN/BT RX Antenna diversity: %d\n",
ath_dbg(common, CONFIG, "Added interface at beacon slot: %d\n",
ath_dbg(common, CONFIG, "Removed interface at beacon slot: %d\n",
ath_dbg(common, CONFIG, "tsfadjust is: %llu for bslot: %d\n",
ath_dbg(common, CONFIG,
ath_dbg(common, CONFIG,
ath_dbg(common, CONFIG,
ath_dbg(common, CONFIG, "Unsupported beaconing mode\n");
ath_dbg(common, CONFIG, "Unsupported beaconing mode\n");
ath_dbg(common, CONFIG,
ath_dbg(common, CONFIG, "Driver halt\n");
ath_dbg(common, CONFIG, "Attach a VIF of type: %d at idx: %d\n",
ath_dbg(common, CONFIG, "Detach Interface at idx: %d\n", avp->index);
ath_dbg(common, CONFIG, "Set channel: %d MHz\n",
ath_dbg(ath9k_hw_common(priv->ah), CONFIG, "Set HW RX filter: 0x%x\n",
ath_dbg(common, CONFIG,
ath_dbg(common, CONFIG,
ath_dbg(common, CONFIG,
ath_dbg(common, CONFIG, "Set HW Key\n");
ath_dbg(common, CONFIG, "BSSID: %pM aid: 0x%x\n",
ath_dbg(common, CONFIG, "BSS Changed ASSOC %d\n",
ath_dbg(common, CONFIG, "Beacon enabled for BSS: %pM\n",
ath_dbg(common, CONFIG,
ath_dbg(common, CONFIG,
ath_dbg(common, CONFIG, "Set bitrate masks: 0x%x, 0x%x\n",
ath_dbg(common, CONFIG,
ath_dbg(common, CONFIG,
ath_dbg(common, CONFIG,
ath_dbg(common, CONFIG,
ath_dbg(common, CONFIG,
ath_dbg(common, CONFIG,
ath_dbg(common, CONFIG,
ath_dbg(common, CONFIG,
ath_dbg(common, CONFIG,
ath_dbg(common, CONFIG,
ath_dbg(common, CONFIG,
ath_dbg(common, CONFIG,
ath_dbg(common, CONFIG,
ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
ath_dbg(common, CONFIG, "%s DMA: %u buffers %u desc/buf\n",
ath_dbg(common, CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
ath_dbg(common, CONFIG, "parsing configuration from OF node\n");
ath_dbg(common, CONFIG,
ath_dbg(common, CONFIG,
ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
ath_dbg(common, CONFIG, "Change Interface\n");
ath_dbg(common, CONFIG, "Detach Interface\n");
ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
ath_dbg(common, CONFIG,
ath_dbg(common, CONFIG,
ath_dbg(common, CONFIG,
ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd);
ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
ath_dbg(common, CONFIG, "vif %pM power %d dbm power_type %d\n",
ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
ath_dbg(common, CONFIG,
ath_dbg(common, CONFIG, "Driver halt\n");
ath_dbg(common, CONFIG, "cachelsz %u rxbufsize %u\n",
ctx->cp0_regs[CONFIG] = read_c0_brcm_config();
write_c0_brcm_config(ctx->cp0_regs[CONFIG]);
svs_writel_relaxed(svsp, SVSB_DET_MAX, CONFIG);
[CONFIG] = 0x2c,
ret = regmap_update_bits(map, CONFIG_ADDR, CONFIG_MASK, CONFIG);
dump_register(CONFIG),
SR(CONFIG);
RR(CONFIG);