pll_ctl
vidc->pll_ctl = acornfb_vidc20_find_pll(var->pixclock / div);
uint64_t pll_ctl:10;
uint64_t pll_ctl:10;
uint64_t pll_ctl:10;
uint64_t pll_ctl:10;
uint64_t pll_ctl:10;
uint64_t pll_ctl:10;
uint64_t pll_ctl:10;
uint64_t pll_ctl:10;
uint64_t pll_ctl:10;
uint64_t pll_ctl:10;
uint64_t pll_ctl:10;
uint64_t pll_ctl:10;
uint64_t pll_ctl:10;
uint64_t pll_ctl:10;
u16 pll_ctl;
pll_ctl = ioread16(mmio_base + PDC_PLL_CTL);
dev_dbg(host->dev, "pll_ctl[%X]\n", pll_ctl);
pll_ctl = (R << 8) | F;
dev_dbg(host->dev, "Writing pll_ctl[%X]\n", pll_ctl);
iowrite16(pll_ctl, mmio_base + PDC_PLL_CTL);
pll_ctl = ioread16(mmio_base + PDC_PLL_CTL);
dev_dbg(host->dev, "pll_ctl[%X]\n", pll_ctl);
u32 pll_ctl, pll_div;
pll_ctl = config->dsi_pll.ctrl;
pll_ctl &= DSI_PLL_P1_POST_DIV_MASK;
pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2);
p = fls(pll_ctl);
u32 pll_ctl, pll_div;
pll_ctl = vlv_cck_read(display->drm, CCK_REG_DSI_PLL_CONTROL);
config->dsi_pll.ctrl = pll_ctl & ~DSI_PLL_LOCK;
vidc_writel(0xd0000000 | vidc.pll_ctl);
printk(KERN_DEBUG " PLL Ctrl (D) : 0x%08X\n", vidc.pll_ctl);
u_int pll_ctl;
pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT |
snd_soc_component_write(component, SGTL5000_CHIP_PLL_CTRL, pll_ctl);
int pll_ctl;
static const struct pll_ctl *get_pll_ctl(int input_freq)
const struct pll_ctl *pll_ctl = NULL;
pll_ctl = &pll_ctls[i];
return pll_ctl;
const struct pll_ctl *pll_ctl;
pll_ctl = get_pll_ctl(input_freq);
if (!pll_ctl) {
pll_ctl->settings[i].addr,
pll_ctl->settings[i].mask,
pll_ctl->settings[i].val);
static const struct pll_ctl pll_ctls[] = {
static const struct pll_ctl pll_ctls[] = {
static inline const struct pll_ctl *get_pll_ctl(unsigned long freq_in)
struct pll_ctl const *pll_ctl = NULL;
pll_ctl = &pll_ctls[i];
return pll_ctl;
struct pll_ctl const *pll_ctl;
pll_ctl = get_pll_ctl(freq);
if (!pll_ctl) {
pll_ctl->settings[i].addr,
pll_ctl->settings[i].val);