drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10620

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10645

if (dm->dc->current_state->res_ctx.pipe_ctx[i].stream == crtc_state->stream) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10646

pipe = &dm->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1297

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1301

pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1302

if (pipe_ctx->stream &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1303

pipe_ctx->stream->link == link)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1310

if (pipe_ctx && pipe_ctx->stream_res.tg &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1311

pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1312

pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments(pipe_ctx->stream_res.tg, &segments);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1567

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1577

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1578

if (pipe_ctx->stream &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1579

pipe_ctx->stream->link == aconnector->dc_link &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1580

pipe_ctx->stream->sink &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1581

pipe_ctx->stream->sink == aconnector->dc_sink)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1585

dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1646

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1679

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1680

if (pipe_ctx->stream &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1681

pipe_ctx->stream->link == aconnector->dc_link &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1682

pipe_ctx->stream->sink &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1683

pipe_ctx->stream->sink == aconnector->dc_sink)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1687

if (!pipe_ctx->stream)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1753

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1763

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1764

if (pipe_ctx->stream &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1765

pipe_ctx->stream->link == aconnector->dc_link &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1766

pipe_ctx->stream->sink &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1767

pipe_ctx->stream->sink == aconnector->dc_sink)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1771

dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1826

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1863

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1864

if (pipe_ctx->stream &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1865

pipe_ctx->stream->link == aconnector->dc_link &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1866

pipe_ctx->stream->sink &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1867

pipe_ctx->stream->sink == aconnector->dc_sink)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1871

if (!pipe_ctx->stream)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1895

pipe_ctx->stream->timing.h_addressable,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1937

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1947

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1948

if (pipe_ctx->stream &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1949

pipe_ctx->stream->link == aconnector->dc_link &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1950

pipe_ctx->stream->sink &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1951

pipe_ctx->stream->sink == aconnector->dc_sink)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1955

dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2014

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2047

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2048

if (pipe_ctx->stream &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2049

pipe_ctx->stream->link == aconnector->dc_link &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2050

pipe_ctx->stream->sink &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2051

pipe_ctx->stream->sink == aconnector->dc_sink)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2055

if (!pipe_ctx->stream)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2079

pipe_ctx->stream->timing.v_addressable,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2117

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2127

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2128

if (pipe_ctx->stream &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2129

pipe_ctx->stream->link == aconnector->dc_link &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2130

pipe_ctx->stream->sink &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2131

pipe_ctx->stream->sink == aconnector->dc_sink)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2135

dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2191

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2224

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2225

if (pipe_ctx->stream &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2226

pipe_ctx->stream->link == aconnector->dc_link &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2227

pipe_ctx->stream->sink &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2228

pipe_ctx->stream->sink == aconnector->dc_sink)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2232

if (!pipe_ctx->stream)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2292

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2302

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2303

if (pipe_ctx->stream &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2304

pipe_ctx->stream->link == aconnector->dc_link &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2305

pipe_ctx->stream->sink &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2306

pipe_ctx->stream->sink == aconnector->dc_sink)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2310

dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2346

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2356

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2357

if (pipe_ctx->stream &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2358

pipe_ctx->stream->link == aconnector->dc_link &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2359

pipe_ctx->stream->sink &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2360

pipe_ctx->stream->sink == aconnector->dc_sink)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2364

dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2415

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2425

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2426

if (pipe_ctx->stream &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2427

pipe_ctx->stream->link == aconnector->dc_link &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2428

pipe_ctx->stream->sink &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2429

pipe_ctx->stream->sink == aconnector->dc_sink)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2433

dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2484

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2494

pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2495

if (pipe_ctx->stream &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2496

pipe_ctx->stream->link == aconnector->dc_link &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2497

pipe_ctx->stream->sink &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2498

pipe_ctx->stream->sink == aconnector->dc_sink)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2502

dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1242

struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1243

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1256

pipe_ctx = &pipes[i];

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1261

if (pipe_ctx == NULL)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1322

&& pipe_ctx->stream->timing.display_color_depth != requestColorDepth)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1324

&& pipe_ctx->stream->timing.pixel_encoding != requestPixelEncoding)) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1327

pipe_ctx->stream->timing.display_color_depth,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1328

pipe_ctx->stream->timing.pixel_encoding,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1331

pipe_ctx->stream->timing.display_color_depth = requestColorDepth;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1332

pipe_ctx->stream->timing.pixel_encoding = requestPixelEncoding;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1334

dc_link_update_dsc_config(pipe_ctx);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1339

*aconnector->timing_requested = pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1345

pipe_ctx->stream->test_pattern.type = test_pattern;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1346

pipe_ctx->stream->test_pattern.color_space = test_pattern_color_space;

drivers/gpu/drm/amd/display/dc/basics/dc_common.c

53

bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/basics/dc_common.c

55

if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)

drivers/gpu/drm/amd/display/dc/basics/dc_common.c

57

if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))

drivers/gpu/drm/amd/display/dc/basics/dc_common.c

62

bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/basics/dc_common.c

64

if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)

drivers/gpu/drm/amd/display/dc/basics/dc_common.c

66

if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))

drivers/gpu/drm/amd/display/dc/basics/dc_common.c

71

bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/basics/dc_common.c

73

if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)

drivers/gpu/drm/amd/display/dc/basics/dc_common.c

75

if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))

drivers/gpu/drm/amd/display/dc/basics/dc_common.c

77

if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))

drivers/gpu/drm/amd/display/dc/basics/dc_common.h

33

bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/basics/dc_common.h

35

bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/basics/dc_common.h

37

bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

2786

const struct pipe_ctx pipe[], int pipe_count, struct bw_calcs_data *data)

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

3009

static bool all_displays_in_sync(const struct pipe_ctx pipe[],

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

3012

const struct pipe_ctx *active_pipes[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

3044

const struct pipe_ctx pipe[],

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

171

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

173

if (pipe_ctx->stream == NULL)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

177

if (pipe_ctx->top_pipe)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

180

if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 > max_pix_clk)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

181

max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

186

if (dc_is_dp_signal(pipe_ctx->stream->signal) &&

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

187

pipe_ctx->stream_res.pix_clk_params.requested_sym_clk > max_pix_clk)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

188

max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

138

const struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

141

if (stream == context->res_ctx.pipe_ctx[k].stream) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

142

pipe_ctx = &context->res_ctx.pipe_ctx[k];

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

146

ASSERT(pipe_ctx != NULL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

153

cfg->signal = pipe_ctx->stream->signal;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

154

cfg->pipe_idx = pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

164

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

166

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

169

pipe_ctx->plane_res.dpp->funcs->dpp_dppclk_control(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

170

pipe_ctx->plane_res.dpp,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

117

dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

153

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

156

struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

160

if (!resource_is_pipe_type(pipe_ctx, OTG_MASTER))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

174

pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

184

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

186

struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

191

if (!resource_is_pipe_type(pipe_ctx, OTG_MASTER))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

202

pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

120

dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

120

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

155

struct pipe_ctx *pipe = safe_to_lower

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

156

? &context->res_ctx.pipe_ctx[i]

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

157

: &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

106

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

90

static bool should_disable_otg(struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

109

struct pipe_ctx *pipe = safe_to_lower

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

110

? &context->res_ctx.pipe_ctx[i]

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

111

: &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

275

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

279

if (pipe_ctx->stream_res.tg &&

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

280

!(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

281

tg_mask |= (1 << pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

283

dto_params.otg_inst = pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

323

dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

325

if (context->res_ctx.pipe_ctx[i].plane_res.dpp)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

326

dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

327

else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

332

} else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

372

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

375

struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

379

if (!resource_is_pipe_type(pipe_ctx, OTG_MASTER))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

393

pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

426

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

428

struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

433

if (!resource_is_pipe_type(pipe_ctx, OTG_MASTER))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

444

pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

490

static bool dcn32_check_native_scaling(struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

514

struct pipe_ctx *pipe_ctx_list[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

518

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

520

if (pipe_ctx->stream && dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

521

pipe_ctx_list[active_pipe_count] = pipe_ctx;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

572

struct pipe_ctx *curr_pipe_ctx = pipe_ctx_list[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

199

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

200

struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

203

struct pipe_ctx *pipe = safe_to_lower

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

204

? &context->res_ctx.pipe_ctx[i]

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

205

: &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

263

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

267

if (pipe_ctx->stream_res.tg &&

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

268

!(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

269

tg_mask |= (1 << pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

271

dto_params.otg_inst = pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

291

dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

293

if (context->res_ctx.pipe_ctx[i].plane_res.dpp)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

294

dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

295

else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

300

} else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

317

struct dpp *old_dpp = clk_mgr->base.ctx->dc->current_state->res_ctx.pipe_ctx[i].plane_res.dpp;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

395

static bool dcn401_check_native_scaling(struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

418

struct pipe_ctx *pipe_ctx_list[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

422

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

424

if (pipe_ctx->stream && dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

425

pipe_ctx_list[active_pipe_count] = pipe_ctx;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

474

struct pipe_ctx *curr_pipe_ctx = pipe_ctx_list[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

530

struct pipe_ctx *otg_master;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

565

dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

567

if (context->res_ctx.pipe_ctx[i].plane_res.dpp)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

568

dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

569

else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

574

} else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {

drivers/gpu/drm/amd/display/dc/core/dc.c

1227

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

1228

struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

1231

if (stream == pipe_ctx->stream) {

drivers/gpu/drm/amd/display/dc/core/dc.c

1232

if (resource_is_pipe_type(pipe_ctx, OPP_HEAD) &&

drivers/gpu/drm/amd/display/dc/core/dc.c

1233

(pipe_ctx->plane_state || old_pipe_ctx->plane_state))

drivers/gpu/drm/amd/display/dc/core/dc.c

1234

dc->hwss.pipe_control_lock(dc, pipe_ctx, lock);

drivers/gpu/drm/amd/display/dc/core/dc.c

1240

static void dc_update_visual_confirm_color(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc.c

1243

memcpy(&pipe_ctx->visual_confirm_color, &pipe_ctx->plane_state->visual_confirm_color,

drivers/gpu/drm/amd/display/dc/core/dc.c

1244

sizeof(pipe_ctx->visual_confirm_color));

drivers/gpu/drm/amd/display/dc/core/dc.c

1249

memset(&pipe_ctx->visual_confirm_color, 0, sizeof(struct tg_color));

drivers/gpu/drm/amd/display/dc/core/dc.c

1252

get_hdr_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));

drivers/gpu/drm/amd/display/dc/core/dc.c

1254

get_surface_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));

drivers/gpu/drm/amd/display/dc/core/dc.c

1256

get_surface_tile_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));

drivers/gpu/drm/amd/display/dc/core/dc.c

1258

get_cursor_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));

drivers/gpu/drm/amd/display/dc/core/dc.c

1260

get_dcc_visual_confirm_color(dc, pipe_ctx, &(pipe_ctx->visual_confirm_color));

drivers/gpu/drm/amd/display/dc/core/dc.c

1264

dc, pipe_ctx->stream->output_color_space, &(pipe_ctx->visual_confirm_color));

drivers/gpu/drm/amd/display/dc/core/dc.c

1268

get_mpctree_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));

drivers/gpu/drm/amd/display/dc/core/dc.c

1270

get_subvp_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));

drivers/gpu/drm/amd/display/dc/core/dc.c

1272

get_mclk_switch_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));

drivers/gpu/drm/amd/display/dc/core/dc.c

1274

get_fams2_visual_confirm_color(dc, context, pipe_ctx, &(pipe_ctx->visual_confirm_color));

drivers/gpu/drm/amd/display/dc/core/dc.c

1276

get_vabc_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));

drivers/gpu/drm/amd/display/dc/core/dc.c

1287

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc.c

1299

pipe_ctx = dc_stream_get_pipe_ctx(stream_state);

drivers/gpu/drm/amd/display/dc/core/dc.c

1300

if (!pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc.c

1302

dc_dmub_srv_get_visual_confirm_color_cmd(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

1316

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

1331

struct pipe_ctx *pipe;

drivers/gpu/drm/amd/display/dc/core/dc.c

1339

dc->current_state->res_ctx.pipe_ctx[i].stream;

drivers/gpu/drm/amd/display/dc/core/dc.c

1343

if ((context->res_ctx.pipe_ctx[i].top_pipe) &&

drivers/gpu/drm/amd/display/dc/core/dc.c

1344

(dc->current_state->res_ctx.pipe_ctx[i].top_pipe))

drivers/gpu/drm/amd/display/dc/core/dc.c

1345

pipe_split_change = context->res_ctx.pipe_ctx[i].top_pipe->pipe_idx !=

drivers/gpu/drm/amd/display/dc/core/dc.c

1346

dc->current_state->res_ctx.pipe_ctx[i].top_pipe->pipe_idx;

drivers/gpu/drm/amd/display/dc/core/dc.c

1348

pipe_split_change = context->res_ctx.pipe_ctx[i].top_pipe !=

drivers/gpu/drm/amd/display/dc/core/dc.c

1349

dc->current_state->res_ctx.pipe_ctx[i].top_pipe;

drivers/gpu/drm/amd/display/dc/core/dc.c

1361

if (old_stream && !dc->current_state->res_ctx.pipe_ctx[i].top_pipe &&

drivers/gpu/drm/amd/display/dc/core/dc.c

1362

!dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe) {

drivers/gpu/drm/amd/display/dc/core/dc.c

1363

struct pipe_ctx *old_pipe, *new_pipe;

drivers/gpu/drm/amd/display/dc/core/dc.c

1365

old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

1366

new_pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

1374

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

1444

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

1446

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

1607

struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL };

drivers/gpu/drm/amd/display/dc/core/dc.c

1610

if (!ctx->res_ctx.pipe_ctx[i].stream ||

drivers/gpu/drm/amd/display/dc/core/dc.c

1611

!ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.enabled)

drivers/gpu/drm/amd/display/dc/core/dc.c

1613

if (ctx->res_ctx.pipe_ctx[i].stream == ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.event_source)

drivers/gpu/drm/amd/display/dc/core/dc.c

1615

multisync_pipes[multisync_count] = &ctx->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

1633

struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };

drivers/gpu/drm/amd/display/dc/core/dc.c

1636

if (!ctx->res_ctx.pipe_ctx[i].stream

drivers/gpu/drm/amd/display/dc/core/dc.c

1637

|| ctx->res_ctx.pipe_ctx[i].top_pipe

drivers/gpu/drm/amd/display/dc/core/dc.c

1638

|| ctx->res_ctx.pipe_ctx[i].prev_odm_pipe)

drivers/gpu/drm/amd/display/dc/core/dc.c

1641

unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

1647

struct pipe_ctx *pipe_set[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/core/dc.c

2002

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc.c

2005

return (pipe_ctx->stream && pipe_ctx->stream == stream);

drivers/gpu/drm/amd/display/dc/core/dc.c

2010

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc.c

2013

return (pipe_ctx->plane_state == plane_state);

drivers/gpu/drm/amd/display/dc/core/dc.c

2023

struct pipe_ctx *pipe;

drivers/gpu/drm/amd/display/dc/core/dc.c

2029

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

2032

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

2059

if (context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/core/dc.c

2089

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

2097

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

2107

resource_calculate_det_for_stream(dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i])) {

drivers/gpu/drm/amd/display/dc/core/dc.c

2128

struct pipe_ctx *pipe;

drivers/gpu/drm/amd/display/dc/core/dc.c

2138

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

2164

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

2209

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

2247

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

2284

pipe = &context->res_ctx.pipe_ctx[k];

drivers/gpu/drm/amd/display/dc/core/dc.c

2373

struct pipe_ctx *pipe;

drivers/gpu/drm/amd/display/dc/core/dc.c

2421

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

2510

if (res_ctx->pipe_ctx[pipe_idx].stream == stream) {

drivers/gpu/drm/amd/display/dc/core/dc.c

2512

mpcc_id = res_ctx->pipe_ctx[pipe_idx].plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/core/dc.c

2532

struct pipe_ctx *pipe;

drivers/gpu/drm/amd/display/dc/core/dc.c

2535

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

2593

if (context->res_ctx.pipe_ctx[i].stream == NULL ||

drivers/gpu/drm/amd/display/dc/core/dc.c

2594

context->res_ctx.pipe_ctx[i].plane_state == NULL) {

drivers/gpu/drm/amd/display/dc/core/dc.c

2595

context->res_ctx.pipe_ctx[i].pipe_idx = i;

drivers/gpu/drm/amd/display/dc/core/dc.c

2596

dc->hwss.disable_plane(dc, context, &context->res_ctx.pipe_ctx[i]);

drivers/gpu/drm/amd/display/dc/core/dc.c

2665

const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc.c

2667

if (plane_state == pipe_ctx->plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc.c

3636

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc.c

3638

if (pipe_ctx->plane_state != surface)

drivers/gpu/drm/amd/display/dc/core/dc.c

3641

resource_build_scaling_params(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

3698

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc.c

3700

if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) && pipe_ctx->stream == stream) {

drivers/gpu/drm/amd/display/dc/core/dc.c

3703

dc->hwss.setup_periodic_interrupt(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

3713

resource_build_info_frame(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

3714

dc->hwss.update_info_frame(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

3716

if (dc_is_dp_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/core/dc.c

3718

pipe_ctx->stream->link,

drivers/gpu/drm/amd/display/dc/core/dc.c

3725

pipe_ctx->stream->dmdata_address.quad_part != 0)

drivers/gpu/drm/amd/display/dc/core/dc.c

3726

dc->hwss.set_dmdata_attributes(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

3735

struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;

drivers/gpu/drm/amd/display/dc/core/dc.c

3736

resource_build_bit_depth_reduction_params(pipe_ctx->stream,

drivers/gpu/drm/amd/display/dc/core/dc.c

3737

&pipe_ctx->stream->bit_depth_params);

drivers/gpu/drm/amd/display/dc/core/dc.c

3738

pipe_ctx->stream_res.opp->funcs->opp_program_fmt(pipe_ctx->stream_res.opp,

drivers/gpu/drm/amd/display/dc/core/dc.c

3760

dc->link_srv->update_dsc_config(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

3764

dc->link_srv->increase_mst_payload(pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc.c

3767

dc->link_srv->reduce_mst_payload(pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc.c

3791

resource_build_test_pattern_params(&context->res_ctx, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

3796

dc->link_srv->set_dpms_off(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

3798

if (pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only)

drivers/gpu/drm/amd/display/dc/core/dc.c

3799

pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);

drivers/gpu/drm/amd/display/dc/core/dc.c

3806

dc->link_srv->set_dpms_on(dc->current_state, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

3808

} else if (pipe_ctx->stream->link->wa_flags.blank_stream_on_ocs_change && stream_update->output_color_space

drivers/gpu/drm/amd/display/dc/core/dc.c

3809

&& !stream->dpms_off && dc_is_dp_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/core/dc.c

3814

dc->link_srv->set_dpms_on(dc->current_state, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

3817

if (stream_update->abm_level && pipe_ctx->stream_res.abm) {

drivers/gpu/drm/amd/display/dc/core/dc.c

3821

if (pipe_ctx->stream_res.tg->funcs->is_blanked)

drivers/gpu/drm/amd/display/dc/core/dc.c

3822

if (pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg))

drivers/gpu/drm/amd/display/dc/core/dc.c

3827

dc->hwss.set_abm_immediate_disable(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

3829

pipe_ctx->stream_res.abm->funcs->set_abm_level(

drivers/gpu/drm/amd/display/dc/core/dc.c

3830

pipe_ctx->stream_res.abm, stream->abm_level);

drivers/gpu/drm/amd/display/dc/core/dc.c

3897

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc.c

3899

if (pipe_ctx->stream != stream)

drivers/gpu/drm/amd/display/dc/core/dc.c

3901

if (pipe_ctx->plane_state != plane_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

3906

update_dirty_rect->otg_inst = pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/core/dc.c

3958

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc.c

3960

if (pipe_ctx->stream != stream)

drivers/gpu/drm/amd/display/dc/core/dc.c

3962

if (pipe_ctx->plane_state != plane_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

3966

update_dirty_rect->otg_inst = pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/core/dc.c

4031

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc.c

4033

if (!should_update_pipe_for_stream(context, pipe_ctx, stream))

drivers/gpu/drm/amd/display/dc/core/dc.c

4036

if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))

drivers/gpu/drm/amd/display/dc/core/dc.c

4040

if (pipe_ctx->plane_state->update_flags.bits.addr_update)

drivers/gpu/drm/amd/display/dc/core/dc.c

4041

dc->hwss.update_plane_addr(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

4062

struct pipe_ctx *top_pipe_to_program = NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

4102

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

4117

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc.c

4119

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

4121

if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))

drivers/gpu/drm/amd/display/dc/core/dc.c

4124

pipe_ctx->plane_state->triplebuffer_flips = false;

drivers/gpu/drm/amd/display/dc/core/dc.c

4127

!pipe_ctx->plane_state->flip_immediate && dc->debug.enable_tri_buf) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4129

pipe_ctx->plane_state->triplebuffer_flips = true;

drivers/gpu/drm/amd/display/dc/core/dc.c

4181

struct pipe_ctx *top_pipe_to_program = NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

4203

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

4235

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

4244

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

4253

struct pipe_ctx *mpcc_pipe;

drivers/gpu/drm/amd/display/dc/core/dc.c

4254

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/core/dc.c

432

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

4350

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc.c

4354

pipe_ctx->stream && pipe_ctx->plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4359

dc->hwss.update_visual_confirm_color(dc, pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc.c

4360

pipe_ctx->plane_res.hubp->inst);

drivers/gpu/drm/amd/display/dc/core/dc.c

4370

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc.c

4371

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

4373

if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))

drivers/gpu/drm/amd/display/dc/core/dc.c

4375

pipe_ctx->plane_state->triplebuffer_flips = false;

drivers/gpu/drm/amd/display/dc/core/dc.c

4378

!pipe_ctx->plane_state->flip_immediate && dc->debug.enable_tri_buf) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4380

pipe_ctx->plane_state->triplebuffer_flips = true;

drivers/gpu/drm/amd/display/dc/core/dc.c

4392

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc.c

4394

if (!pipe_ctx->top_pipe &&

drivers/gpu/drm/amd/display/dc/core/dc.c

4395

!pipe_ctx->prev_odm_pipe &&

drivers/gpu/drm/amd/display/dc/core/dc.c

4396

should_update_pipe_for_stream(context, pipe_ctx, stream)) {

drivers/gpu/drm/amd/display/dc/core/dc.c

4399

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

4407

stream_get_status(context, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/core/dc.c

4411

dc, pipe_ctx->stream, stream_status->plane_count, context);

drivers/gpu/drm/amd/display/dc/core/dc.c

4416

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc.c

4418

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

4425

ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);

drivers/gpu/drm/amd/display/dc/core/dc.c

4429

dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);

drivers/gpu/drm/amd/display/dc/core/dc.c

4439

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc.c

4441

dc->hwseq->funcs.set_wait_for_update_needed_for_pipe(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

4447

struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

4453

&context->res_ctx.pipe_ctx[i].rq_regs,

drivers/gpu/drm/amd/display/dc/core/dc.c

4454

&context->res_ctx.pipe_ctx[i].dlg_regs,

drivers/gpu/drm/amd/display/dc/core/dc.c

4455

&context->res_ctx.pipe_ctx[i].ttu_regs);

drivers/gpu/drm/amd/display/dc/core/dc.c

4467

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc.c

4469

if (!should_update_pipe_for_stream(context, pipe_ctx, stream))

drivers/gpu/drm/amd/display/dc/core/dc.c

4472

if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))

drivers/gpu/drm/amd/display/dc/core/dc.c

4476

dc->hwss.set_flip_control_gsl(pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc.c

4477

pipe_ctx->plane_state->flip_immediate);

drivers/gpu/drm/amd/display/dc/core/dc.c

4486

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc.c

4488

if (!should_update_pipe_for_stream(context, pipe_ctx, stream))

drivers/gpu/drm/amd/display/dc/core/dc.c

4491

if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))

drivers/gpu/drm/amd/display/dc/core/dc.c

4500

dc->hwss.trigger_3dlut_dma_load(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

4506

dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);

drivers/gpu/drm/amd/display/dc/core/dc.c

4508

if (pipe_ctx->plane_state->update_flags.bits.addr_update)

drivers/gpu/drm/amd/display/dc/core/dc.c

4509

dc->hwss.update_plane_addr(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

4592

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc.c

4594

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

4597

if (pipe_ctx->bottom_pipe || pipe_ctx->next_odm_pipe ||

drivers/gpu/drm/amd/display/dc/core/dc.c

4598

!pipe_ctx->stream || !should_update_pipe_for_stream(context, pipe_ctx, stream) ||

drivers/gpu/drm/amd/display/dc/core/dc.c

4599

!pipe_ctx->plane_state->update_flags.bits.addr_update ||

drivers/gpu/drm/amd/display/dc/core/dc.c

4600

pipe_ctx->plane_state->skip_manual_trigger)

drivers/gpu/drm/amd/display/dc/core/dc.c

4604

dc->hwss.program_cursor_offload_now(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

4605

if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger)

drivers/gpu/drm/amd/display/dc/core/dc.c

4606

pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);

drivers/gpu/drm/amd/display/dc/core/dc.c

4679

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

4778

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc.c

4792

pipe_ctx = &new_context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

4794

if (pipe_ctx->plane_state && pipe_ctx->stream == stream)

drivers/gpu/drm/amd/display/dc/core/dc.c

4795

pipe_ctx->plane_state->force_full_update = false;

drivers/gpu/drm/amd/display/dc/core/dc.c

496

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

4971

struct pipe_ctx *pipe = &transition_base_context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

4981

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

4993

struct pipe_ctx *pipe = &transition_base_context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

538

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

5695

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

5732

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

5790

struct pipe_ctx *pipe;

drivers/gpu/drm/amd/display/dc/core/dc.c

5794

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

5814

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

599

struct pipe_ctx *pipe;

drivers/gpu/drm/amd/display/dc/core/dc.c

604

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

6055

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

6066

res_ctx->pipe_ctx[i].stream &&

drivers/gpu/drm/amd/display/dc/core/dc.c

6067

res_ctx->pipe_ctx[i].stream->link &&

drivers/gpu/drm/amd/display/dc/core/dc.c

6068

res_ctx->pipe_ctx[i].stream->link == link &&

drivers/gpu/drm/amd/display/dc/core/dc.c

6069

res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6070

pipe_ctx = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

6076

if (pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc.c

6077

otg_inst = pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/core/dc.c

6081

if (dc->hwss.set_pipe && pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc.c

6082

dc->hwss.set_pipe(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc.c

6333

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

6346

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

6388

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

6397

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

6616

if (res_ctx->pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/core/dc.c

6622

struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

6625

if (!pipe_ctx->stream)

drivers/gpu/drm/amd/display/dc/core/dc.c

6631

if (pipe_ctx->stream_res.tg)

drivers/gpu/drm/amd/display/dc/core/dc.c

6632

state->hubp[i].vtg_sel = pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/core/dc.c

6634

state->hubp[i].hubp_clock_enable = (pipe_ctx->plane_res.hubp != NULL) ? 1 : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

6637

if (pipe_ctx->plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6639

state->hubp[i].surface_pixel_format = pipe_ctx->plane_state->format;

drivers/gpu/drm/amd/display/dc/core/dc.c

6640

state->hubp[i].rotation_angle = pipe_ctx->plane_state->rotation;

drivers/gpu/drm/amd/display/dc/core/dc.c

6641

state->hubp[i].h_mirror_en = pipe_ctx->plane_state->horizontal_mirror ? 1 : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

6644

if (pipe_ctx->plane_state->plane_size.surface_size.width > 0) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6645

state->hubp[i].surface_size_width = pipe_ctx->plane_state->plane_size.surface_size.width;

drivers/gpu/drm/amd/display/dc/core/dc.c

6646

state->hubp[i].surface_size_height = pipe_ctx->plane_state->plane_size.surface_size.height;

drivers/gpu/drm/amd/display/dc/core/dc.c

665

struct pipe_ctx *pipe;

drivers/gpu/drm/amd/display/dc/core/dc.c

6650

if (pipe_ctx->plane_state->src_rect.width > 0) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6651

state->hubp[i].pri_viewport_width = pipe_ctx->plane_state->src_rect.width;

drivers/gpu/drm/amd/display/dc/core/dc.c

6652

state->hubp[i].pri_viewport_height = pipe_ctx->plane_state->src_rect.height;

drivers/gpu/drm/amd/display/dc/core/dc.c

6653

state->hubp[i].pri_viewport_x_start = pipe_ctx->plane_state->src_rect.x;

drivers/gpu/drm/amd/display/dc/core/dc.c

6654

state->hubp[i].pri_viewport_y_start = pipe_ctx->plane_state->src_rect.y;

drivers/gpu/drm/amd/display/dc/core/dc.c

6658

state->hubp[i].surface_dcc_en = (pipe_ctx->plane_state->dcc.enable) ? 1 : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

6659

state->hubp[i].surface_dcc_ind_64b_blk = pipe_ctx->plane_state->dcc.independent_64b_blks;

drivers/gpu/drm/amd/display/dc/core/dc.c

6660

state->hubp[i].surface_dcc_ind_128b_blk = pipe_ctx->plane_state->dcc.dcc_ind_blk;

drivers/gpu/drm/amd/display/dc/core/dc.c

6663

state->hubp[i].surface_pitch = pipe_ctx->plane_state->plane_size.surface_pitch;

drivers/gpu/drm/amd/display/dc/core/dc.c

6664

state->hubp[i].meta_pitch = pipe_ctx->plane_state->dcc.meta_pitch;

drivers/gpu/drm/amd/display/dc/core/dc.c

6665

state->hubp[i].chroma_pitch = pipe_ctx->plane_state->plane_size.chroma_pitch;

drivers/gpu/drm/amd/display/dc/core/dc.c

6666

state->hubp[i].meta_pitch_c = pipe_ctx->plane_state->dcc.meta_pitch_c;

drivers/gpu/drm/amd/display/dc/core/dc.c

6669

state->hubp[i].primary_surface_address_low = pipe_ctx->plane_state->address.grph.addr.low_part;

drivers/gpu/drm/amd/display/dc/core/dc.c

6670

state->hubp[i].primary_surface_address_high = pipe_ctx->plane_state->address.grph.addr.high_part;

drivers/gpu/drm/amd/display/dc/core/dc.c

6671

state->hubp[i].primary_meta_surface_address_low = pipe_ctx->plane_state->address.grph.meta_addr.low_part;

drivers/gpu/drm/amd/display/dc/core/dc.c

6672

state->hubp[i].primary_meta_surface_address_high = pipe_ctx->plane_state->address.grph.meta_addr.high_part;

drivers/gpu/drm/amd/display/dc/core/dc.c

6675

state->hubp[i].primary_surface_tmz = pipe_ctx->plane_state->address.tmz_surface;

drivers/gpu/drm/amd/display/dc/core/dc.c

6676

state->hubp[i].primary_meta_surface_tmz = pipe_ctx->plane_state->address.tmz_surface;

drivers/gpu/drm/amd/display/dc/core/dc.c

6680

if (pipe_ctx->plane_state->tiling_info.gfxversion >= DcGfxVersion9) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6682

state->hubp[i].sw_mode = pipe_ctx->plane_state->tiling_info.gfx9.swizzle;

drivers/gpu/drm/amd/display/dc/core/dc.c

6683

state->hubp[i].num_pipes = pipe_ctx->plane_state->tiling_info.gfx9.num_pipes;

drivers/gpu/drm/amd/display/dc/core/dc.c

6684

state->hubp[i].num_banks = pipe_ctx->plane_state->tiling_info.gfx9.num_banks;

drivers/gpu/drm/amd/display/dc/core/dc.c

6685

state->hubp[i].pipe_interleave = pipe_ctx->plane_state->tiling_info.gfx9.pipe_interleave;

drivers/gpu/drm/amd/display/dc/core/dc.c

6686

state->hubp[i].num_shader_engines = pipe_ctx->plane_state->tiling_info.gfx9.num_shader_engines;

drivers/gpu/drm/amd/display/dc/core/dc.c

6687

state->hubp[i].num_rb_per_se = pipe_ctx->plane_state->tiling_info.gfx9.num_rb_per_se;

drivers/gpu/drm/amd/display/dc/core/dc.c

6688

state->hubp[i].num_pkrs = pipe_ctx->plane_state->tiling_info.gfx9.num_pkrs;

drivers/gpu/drm/amd/display/dc/core/dc.c

6693

if (pipe_ctx->rq_regs.rq_regs_l.chunk_size > 0) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6694

state->hubp[i].rq_chunk_size = pipe_ctx->rq_regs.rq_regs_l.chunk_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

6695

state->hubp[i].rq_min_chunk_size = pipe_ctx->rq_regs.rq_regs_l.min_chunk_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

6696

state->hubp[i].rq_meta_chunk_size = pipe_ctx->rq_regs.rq_regs_l.meta_chunk_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

6697

state->hubp[i].rq_min_meta_chunk_size = pipe_ctx->rq_regs.rq_regs_l.min_meta_chunk_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

6698

state->hubp[i].rq_dpte_group_size = pipe_ctx->rq_regs.rq_regs_l.dpte_group_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

6699

state->hubp[i].rq_mpte_group_size = pipe_ctx->rq_regs.rq_regs_l.mpte_group_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

670

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

6700

state->hubp[i].rq_swath_height_l = pipe_ctx->rq_regs.rq_regs_l.swath_height;

drivers/gpu/drm/amd/display/dc/core/dc.c

6701

state->hubp[i].rq_pte_row_height_l = pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear;

drivers/gpu/drm/amd/display/dc/core/dc.c

6705

if (pipe_ctx->rq_regs.rq_regs_c.chunk_size > 0) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6706

state->hubp[i].rq_chunk_size_c = pipe_ctx->rq_regs.rq_regs_c.chunk_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

6707

state->hubp[i].rq_min_chunk_size_c = pipe_ctx->rq_regs.rq_regs_c.min_chunk_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

6708

state->hubp[i].rq_meta_chunk_size_c = pipe_ctx->rq_regs.rq_regs_c.meta_chunk_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

6709

state->hubp[i].rq_min_meta_chunk_size_c = pipe_ctx->rq_regs.rq_regs_c.min_meta_chunk_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

6710

state->hubp[i].rq_dpte_group_size_c = pipe_ctx->rq_regs.rq_regs_c.dpte_group_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

6711

state->hubp[i].rq_mpte_group_size_c = pipe_ctx->rq_regs.rq_regs_c.mpte_group_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

6712

state->hubp[i].rq_swath_height_c = pipe_ctx->rq_regs.rq_regs_c.swath_height;

drivers/gpu/drm/amd/display/dc/core/dc.c

6713

state->hubp[i].rq_pte_row_height_c = pipe_ctx->rq_regs.rq_regs_c.pte_row_height_linear;

drivers/gpu/drm/amd/display/dc/core/dc.c

6717

state->hubp[i].drq_expansion_mode = pipe_ctx->rq_regs.drq_expansion_mode;

drivers/gpu/drm/amd/display/dc/core/dc.c

6718

state->hubp[i].prq_expansion_mode = pipe_ctx->rq_regs.prq_expansion_mode;

drivers/gpu/drm/amd/display/dc/core/dc.c

6719

state->hubp[i].mrq_expansion_mode = pipe_ctx->rq_regs.mrq_expansion_mode;

drivers/gpu/drm/amd/display/dc/core/dc.c

6720

state->hubp[i].crq_expansion_mode = pipe_ctx->rq_regs.crq_expansion_mode;

drivers/gpu/drm/amd/display/dc/core/dc.c

6723

state->hubp[i].dst_y_per_vm_vblank = pipe_ctx->dlg_regs.dst_y_per_vm_vblank;

drivers/gpu/drm/amd/display/dc/core/dc.c

6724

state->hubp[i].dst_y_per_row_vblank = pipe_ctx->dlg_regs.dst_y_per_row_vblank;

drivers/gpu/drm/amd/display/dc/core/dc.c

6725

state->hubp[i].dst_y_per_vm_flip = pipe_ctx->dlg_regs.dst_y_per_vm_flip;

drivers/gpu/drm/amd/display/dc/core/dc.c

6726

state->hubp[i].dst_y_per_row_flip = pipe_ctx->dlg_regs.dst_y_per_row_flip;

drivers/gpu/drm/amd/display/dc/core/dc.c

6729

state->hubp[i].dst_y_prefetch = pipe_ctx->dlg_regs.dst_y_prefetch;

drivers/gpu/drm/amd/display/dc/core/dc.c

6730

state->hubp[i].vratio_prefetch = pipe_ctx->dlg_regs.vratio_prefetch;

drivers/gpu/drm/amd/display/dc/core/dc.c

6731

state->hubp[i].vratio_prefetch_c = pipe_ctx->dlg_regs.vratio_prefetch_c;

drivers/gpu/drm/amd/display/dc/core/dc.c

6734

state->hubp[i].qos_level_low_wm = pipe_ctx->ttu_regs.qos_level_low_wm;

drivers/gpu/drm/amd/display/dc/core/dc.c

6735

state->hubp[i].qos_level_high_wm = pipe_ctx->ttu_regs.qos_level_high_wm;

drivers/gpu/drm/amd/display/dc/core/dc.c

6736

state->hubp[i].qos_level_flip = pipe_ctx->ttu_regs.qos_level_flip;

drivers/gpu/drm/amd/display/dc/core/dc.c

6737

state->hubp[i].min_ttu_vblank = pipe_ctx->ttu_regs.min_ttu_vblank;

drivers/gpu/drm/amd/display/dc/core/dc.c

6744

uint32_t det_size = res_ctx->pipe_ctx[i].det_buffer_size_kb;

drivers/gpu/drm/amd/display/dc/core/dc.c

6768

struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

6770

if (!pipe_ctx->stream)

drivers/gpu/drm/amd/display/dc/core/dc.c

6773

state->dpp[i].dpp_clock_enable = (pipe_ctx->plane_res.dpp != NULL) ? 1 : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

6775

if (pipe_ctx->plane_state && pipe_ctx->plane_res.scl_data.recout.width > 0) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6777

struct dscl_prog_data *dscl_data = &pipe_ctx->plane_res.scl_data.dscl_prog_data;

drivers/gpu/drm/amd/display/dc/core/dc.c

6809

struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

6810

if (pipe_ctx->stream) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6813

state->dccg.pixclk_khz[i] = pipe_ctx->stream->timing.pix_clk_100hz / 10;

drivers/gpu/drm/amd/display/dc/core/dc.c

6817

if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||

drivers/gpu/drm/amd/display/dc/core/dc.c

6818

pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6836

struct pipe_ctx *pipe_ctx = (i < dc->res_pool->pipe_count) ? &res_ctx->pipe_ctx[i] : NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

6837

if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->timing.dsc_cfg.num_slices_h > 0) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6853

struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

6855

if (pipe_ctx->stream && pipe_ctx->stream->timing.dsc_cfg.num_slices_h > 0) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6860

struct dc_dsc_config *dsc_cfg = &pipe_ctx->stream->timing.dsc_cfg;

drivers/gpu/drm/amd/display/dc/core/dc.c

6866

if (pipe_ctx->stream_res.opp) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6868

state->dsc[i].dscrm_dsc_opp_pipe_source = pipe_ctx->stream_res.opp->inst;

drivers/gpu/drm/amd/display/dc/core/dc.c

6881

struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

6883

if (pipe_ctx->plane_state && pipe_ctx->stream) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6884

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/core/dc.c

6897

if (pipe_ctx->bottom_pipe) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6898

state->mpc.mpcc_bot_sel[i] = pipe_ctx->bottom_pipe->pipe_idx;

drivers/gpu/drm/amd/display/dc/core/dc.c

6902

state->mpc.mpcc_top_sel[i] = pipe_ctx->pipe_idx; /* This pipe's DPP ID */

drivers/gpu/drm/amd/display/dc/core/dc.c

6916

if (pipe_ctx->stream_res.opp) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6917

state->mpc.mpcc_opp_id[i] = pipe_ctx->stream_res.opp->inst;

drivers/gpu/drm/amd/display/dc/core/dc.c

6949

struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

6951

if (!pipe_ctx->stream)

drivers/gpu/drm/amd/display/dc/core/dc.c

6954

if (pipe_ctx->stream_res.opp) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6955

struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/core/dc.c

6961

if (pipe_ctx->stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7032

if (pipe_ctx->next_odm_pipe) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7052

state->opp[i].dscrm_dsc_opp_pipe_source = pipe_ctx->stream_res.opp->inst;

drivers/gpu/drm/amd/display/dc/core/dc.c

7067

struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

7069

if (!pipe_ctx->stream)

drivers/gpu/drm/amd/display/dc/core/dc.c

7072

if (pipe_ctx->stream_res.tg) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7073

struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/core/dc.c

7075

state->optc[i].otg_master_inst = pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/core/dc.c

7091

state->optc[i].otg_h_timing_div_mode = (pipe_ctx->next_odm_pipe) ? 1 : 0; /* ODM divide mode */

drivers/gpu/drm/amd/display/dc/core/dc.c

7110

if (pipe_ctx->next_odm_pipe) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7111

state->optc[i].optc_seg0_src_sel = pipe_ctx->stream_res.opp ? pipe_ctx->stream_res.opp->inst : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7112

state->optc[i].optc_seg1_src_sel = pipe_ctx->next_odm_pipe->stream_res.opp ? pipe_ctx->next_odm_pipe->stream_res.opp->inst : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7115

state->optc[i].optc_seg0_src_sel = pipe_ctx->stream_res.opp ? pipe_ctx->stream_res.opp->inst : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7139

state->optc[i].optc_segment_width = (pipe_ctx->next_odm_pipe) ? (timing->h_addressable / 2) : timing->h_addressable;

drivers/gpu/drm/amd/display/dc/core/dc.c

715

struct pipe_ctx *pipe;

drivers/gpu/drm/amd/display/dc/core/dc.c

789

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

795

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

816

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc.c

821

if (dc->current_state->res_ctx.pipe_ctx[i].stream

drivers/gpu/drm/amd/display/dc/core/dc.c

823

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

824

pipe_ctx->stream_res.opp->dyn_expansion = option;

drivers/gpu/drm/amd/display/dc/core/dc.c

825

pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(

drivers/gpu/drm/amd/display/dc/core/dc.c

826

pipe_ctx->stream_res.opp,

drivers/gpu/drm/amd/display/dc/core/dc.c

839

struct pipe_ctx *pipes = NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

843

if (link->dc->current_state->res_ctx.pipe_ctx[i].stream ==

drivers/gpu/drm/amd/display/dc/core/dc.c

845

pipes = &link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

879

struct pipe_ctx *pipes;

drivers/gpu/drm/amd/display/dc/core/dc.c

884

if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {

drivers/gpu/drm/amd/display/dc/core/dc.c

885

pipes = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

898

struct pipe_ctx *pipes;

drivers/gpu/drm/amd/display/dc/core/dc.c

903

if (dc->current_state->res_ctx.pipe_ctx[i].stream

drivers/gpu/drm/amd/display/dc/core/dc.c

906

pipes = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc.c

925

struct pipe_ctx *pipes_affected[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/core/dc.c

934

if (dc->current_state->res_ctx.pipe_ctx[j].stream

drivers/gpu/drm/amd/display/dc/core/dc.c

937

&dc->current_state->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1000

params->update_visual_confirm_params.pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1035

params->program_cursor_update_now_params.pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1042

dc->hwss.apply_update_flags_for_phantom(params->apply_update_flags_for_phantom_params.pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1047

params->update_phantom_vp_position_params.pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1331

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1336

seq_state->steps[*seq_state->num_steps].params.pipe_control_lock_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1363

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1368

seq_state->steps[*seq_state->num_steps].params.program_triplebuffer_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1380

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1384

seq_state->steps[*seq_state->num_steps].params.update_plane_addr_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1395

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1400

seq_state->steps[*seq_state->num_steps].params.set_input_transfer_func_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1411

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1414

seq_state->steps[*seq_state->num_steps].params.program_gamut_remap_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1423

void hwss_add_dpp_program_bias_and_scale(struct block_sequence_state *seq_state, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1426

seq_state->steps[*seq_state->num_steps].params.program_bias_and_scale_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1436

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1439

seq_state->steps[*seq_state->num_steps].params.program_manual_trigger_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1450

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1455

seq_state->steps[*seq_state->num_steps].params.set_output_transfer_func_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1467

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1472

seq_state->steps[*seq_state->num_steps].params.update_visual_confirm_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1573

struct pipe_ctx *top_pipe_to_program)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1600

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1603

seq_state->steps[*seq_state->num_steps].params.apply_update_flags_for_phantom_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1615

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1620

seq_state->steps[*seq_state->num_steps].params.update_phantom_vp_position_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1865

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1869

seq_state->steps[*seq_state->num_steps].params.set_abm_pipe_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1939

struct pipe_ctx *pipe_ctx = params->program_manual_trigger_params.pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1941

if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1942

pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1947

struct pipe_ctx *pipe_ctx = params->setup_dpp_params.pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1948

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1949

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1967

struct pipe_ctx *pipe_ctx = params->program_bias_and_scale_params.pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1968

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1969

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2058

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2063

struct pipe_ctx *bottom_pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2088

struct pipe_ctx *opp_head;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2096

opp_head = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2108

struct pipe_ctx *otg_master;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2113

otg_master = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2134

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2165

const struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2168

pipe_ctx = &dc_context->res_ctx.pipe_ctx[pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2170

if (!pipe_ctx->stream)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2177

if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) && dc->hwss.wait_for_all_pending_updates) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2178

dc->hwss.wait_for_all_pending_updates(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2181

hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2320

struct pipe_ctx *pipe_ctx = params->dsc_calculate_and_set_config_params.pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2321

struct pipe_ctx *top_pipe = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2325

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2326

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2355

struct pipe_ctx *pipe_ctx = params->dsc_enable_with_opp_params.pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2356

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2359

dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2459

struct pipe_ctx *pipe_ctx = params->opp_program_bit_depth_reduction_params.pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2465

resource_build_bit_depth_reduction_params(pipe_ctx->stream, &bit_depth_params);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2492

struct pipe_ctx *pipe_ctx = params->set_abm_pipe_params.pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2494

dc->hwss.set_pipe(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2509

struct pipe_ctx *pipe_ctx = params->set_abm_immediate_disable_params.pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2512

dc->hwss.set_abm_immediate_disable(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3024

struct pipe_ctx *pipe_ctx = params->mpc_update_mpcc_params.pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3028

hws->funcs.update_mpcc(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3087

struct pipe_ctx *pipe_ctx = params->abort_cursor_offload_update_params.pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3090

dc->hwss.abort_cursor_offload_update(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3096

struct pipe_ctx *pipe_ctx = params->set_cursor_attribute_params.pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3099

dc->hwss.set_cursor_attribute(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3105

struct pipe_ctx *pipe_ctx = params->set_cursor_position_params.pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3108

dc->hwss.set_cursor_position(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3114

struct pipe_ctx *pipe_ctx = params->set_cursor_sdr_white_level_params.pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3117

dc->hwss.set_cursor_sdr_white_level(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3123

struct pipe_ctx *pipe_ctx = params->program_output_csc_params.pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3129

dc->hwss.program_output_csc(dc, pipe_ctx, colorspace, matrix, opp_id);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3162

struct pipe_ctx *pipe_ctx, bool enable, int opp_cnt)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3166

seq_state->steps[*seq_state->num_steps].params.dsc_calculate_and_set_config_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

319

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3208

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3212

seq_state->steps[*seq_state->num_steps].params.dsc_enable_with_opp_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3251

struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3256

seq_state->steps[*seq_state->num_steps].params.set_abm_immediate_disable_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

331

struct pipe_ctx *top_pipe = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3362

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3368

seq_state->steps[*seq_state->num_steps].params.opp_program_bit_depth_reduction_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

340

const struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

345

switch (pipe_ctx->plane_res.scl_data.format) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

349

if (pipe_ctx->plane_state->layer_index > 0) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

359

if (pipe_ctx->plane_state->layer_index > 0) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

378

if (pipe_ctx->plane_state->layer_index > 0) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

390

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3902

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3906

seq_state->steps[*seq_state->num_steps].params.setup_dpp_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3953

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3958

seq_state->steps[*seq_state->num_steps].params.abort_cursor_offload_update_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3965

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

397

struct pipe_ctx *top_pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3970

seq_state->steps[*seq_state->num_steps].params.set_cursor_attribute_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3977

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3982

seq_state->steps[*seq_state->num_steps].params.set_cursor_position_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3989

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3994

seq_state->steps[*seq_state->num_steps].params.set_cursor_sdr_white_level_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4001

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4009

seq_state->steps[*seq_state->num_steps].params.program_output_csc_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

465

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

471

if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

472

if (pipe_ctx->stream->link->connector_signal == SIGNAL_TYPE_EDP)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

473

edp_link = pipe_ctx->stream->link;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

502

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

506

if (pipe_ctx) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

507

switch (pipe_ctx->p_state_type) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

530

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

535

if (pipe_ctx) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

536

switch (pipe_ctx->p_state_type) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

574

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

579

if (pipe_ctx->stream && pipe_ctx->stream->cursor_position.enable) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

592

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

597

if (!pipe_ctx->plane_state->dcc.enable) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

611

uint32_t first_id = pipe_ctx->mcache_regs.main.p0.mcache_id_first;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

612

uint32_t second_id = pipe_ctx->mcache_regs.main.p0.mcache_id_second;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

640

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

645

if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !vba)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

648

pipe_ctx->p_state_type = P_STATE_UNKNOWN;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

652

if (!pipe_ctx->has_vactive_margin) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

654

pipe_ctx->p_state_type = P_STATE_V_BLANK;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

658

pipe_ctx->p_state_type = P_STATE_FPO;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

662

pipe_ctx->p_state_type = P_STATE_V_ACTIVE;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

669

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

674

pipe_ctx->p_state_type = P_STATE_SUB_VP;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

677

if (pipe_ctx->stream == pipe->stream)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

683

if (enable_subvp && dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_NONE) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

684

if (pipe_ctx->stream->allow_freesync == 1) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

686

pipe_ctx->p_state_type = P_STATE_DRR_SUB_VP;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

689

pipe_ctx->p_state_type = P_STATE_V_BLANK_SUB_VP;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

696

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

701

if (pipe_ctx && pipe_ctx->stream_res.tg &&

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

702

pipe_ctx->stream_res.tg->funcs->set_drr)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

703

pipe_ctx->stream_res.tg->funcs->set_drr(

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

704

pipe_ctx->stream_res.tg, params);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

713

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

718

if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !context || !dc->debug.fams2_config.bits.enable)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

735

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

739

struct dc_plane_state *plane = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

740

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

742

struct pipe_ctx *current_pipe = NULL;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

743

struct pipe_ctx *current_mpc_pipe = NULL;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

754

block_sequence[*num_steps].params.wait_for_dcc_meta_propagation_params.top_pipe_to_program = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

779

block_sequence[*num_steps].params.pipe_control_lock_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

792

current_pipe = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

805

block_sequence[*num_steps].params.program_triplebuffer_params.pipe_ctx = current_mpc_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

821

block_sequence[*num_steps].params.update_plane_addr_params.pipe_ctx = current_mpc_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

828

block_sequence[*num_steps].params.set_input_transfer_func_params.pipe_ctx = current_mpc_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

835

block_sequence[*num_steps].params.program_gamut_remap_params.pipe_ctx = current_mpc_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

840

block_sequence[*num_steps].params.setup_dpp_params.pipe_ctx = current_mpc_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

845

block_sequence[*num_steps].params.program_bias_and_scale_params.pipe_ctx = current_mpc_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

852

block_sequence[*num_steps].params.set_output_transfer_func_params.pipe_ctx = current_mpc_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

860

block_sequence[*num_steps].params.update_visual_confirm_params.pipe_ctx = current_mpc_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

896

block_sequence[*num_steps].params.pipe_control_lock_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

916

current_pipe = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

927

block_sequence[*num_steps].params.program_cursor_update_now_params.pipe_ctx = current_mpc_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

932

block_sequence[*num_steps].params.program_manual_trigger_params.pipe_ctx = current_mpc_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

959

params->pipe_control_lock_params.pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

969

params->program_triplebuffer_params.pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

974

params->update_plane_addr_params.pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

978

params->set_input_transfer_func_params.pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

982

dc->hwss.program_gamut_remap(params->program_gamut_remap_params.pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

995

params->set_output_transfer_func_params.pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

147

bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

149

struct dc_link *link = pipe_ctx->stream->link;

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

151

return link->dc->link_srv->update_dsc_config(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1002

calculate_adjust_recout_for_visual_confirm(pipe_ctx, &base_offset,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1009

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1013

calculate_adjust_recout_for_visual_confirm(pipe_ctx, &base_offset,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1024

static void calculate_recout(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1152

plane_clip = calculate_plane_rec_in_timing_active(pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1153

&pipe_ctx->plane_state->clip_rect);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1156

&pipe_ctx->stream->dst);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1158

pipe_ctx, &plane_clip);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1159

odm_slice_src = resource_get_odm_slice_src_rect(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1166

pipe_ctx->plane_res.scl_data.recout = shift_rec(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1170

&pipe_ctx->plane_res.scl_data.recout,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1171

pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1174

memset(&pipe_ctx->plane_res.scl_data.recout, 0,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1180

static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1182

const struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1183

const struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1191

if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1192

pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1195

pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1198

pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1203

pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1205

pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1207

pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1208

pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1209

pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1210

pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1212

pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1213

pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1215

if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1216

|| pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1217

pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1218

pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1220

pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1221

pipe_ctx->plane_res.scl_data.ratios.horz, 19);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1222

pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1223

pipe_ctx->plane_res.scl_data.ratios.vert, 19);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1224

pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1225

pipe_ctx->plane_res.scl_data.ratios.horz_c, 19);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1226

pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1227

pipe_ctx->plane_res.scl_data.ratios.vert_c, 19);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1296

static void calculate_inits_and_viewports(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1298

const struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1299

struct scaler_data *data = &pipe_ctx->plane_res.scl_data;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1305

struct rect odm_slice_src = resource_get_odm_slice_src_rect(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1313

pipe_ctx, &plane_state->dst_rect);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1452

struct pipe_ctx *otg_master)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1454

struct pipe_ctx *opp_heads[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1485

bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1487

const struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1488

struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1489

const struct rect odm_slice_src = resource_get_odm_slice_src_rect(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1493

DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1510

pipe_ctx->stream->dst.x += timing->h_border_left;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1511

pipe_ctx->stream->dst.y += timing->v_border_top;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1514

pipe_ctx->plane_res.scl_data.h_active = odm_slice_src.width;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1515

pipe_ctx->plane_res.scl_data.v_active = odm_slice_src.height;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1516

pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1517

pipe_ctx->plane_state->format);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1520

if ((pipe_ctx->stream->ctx->dc->config.use_spl) && (!pipe_ctx->stream->ctx->dc->debug.disable_spl)) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1521

struct spl_in *spl_in = &pipe_ctx->plane_res.spl_in;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1522

struct spl_out *spl_out = &pipe_ctx->plane_res.spl_out;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1525

pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1527

pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1529

pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1532

translate_SPL_in_params_from_pipe_ctx(pipe_ctx, spl_in);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1534

calculate_adjust_recout_for_visual_confirm(pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1538

spl_out->dscl_prog_data = resource_get_dscl_prog_data(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1542

translate_SPL_out_params_to_pipe_ctx(pipe_ctx, spl_out);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1550

calculate_recout(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1552

calculate_scaling_ratios(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1567

pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1569

pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1571

pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1575

pipe_ctx->plane_res.scl_data.viewport.width = 100;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1576

pipe_ctx->plane_res.scl_data.viewport.height = 100;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1577

pipe_ctx->plane_res.scl_data.viewport_c.width = 100;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1578

pipe_ctx->plane_res.scl_data.viewport_c.height = 100;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1579

if (pipe_ctx->plane_res.xfm != NULL)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1580

res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1581

pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1583

if (pipe_ctx->plane_res.dpp != NULL)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1584

res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1585

pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1587

temp = pipe_ctx->plane_res.scl_data.taps;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1589

calculate_inits_and_viewports(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1591

if (pipe_ctx->plane_res.xfm != NULL)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1592

res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1593

pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1595

if (pipe_ctx->plane_res.dpp != NULL)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1596

res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1597

pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1602

pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1604

if (pipe_ctx->plane_res.xfm != NULL)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1605

res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1606

pipe_ctx->plane_res.xfm,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1607

&pipe_ctx->plane_res.scl_data,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1610

if (pipe_ctx->plane_res.dpp != NULL)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1611

res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1612

pipe_ctx->plane_res.dpp,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1613

&pipe_ctx->plane_res.scl_data,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1621

if (res && (pipe_ctx->plane_res.scl_data.taps.v_taps != temp.v_taps ||

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1622

pipe_ctx->plane_res.scl_data.taps.h_taps != temp.h_taps ||

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1623

pipe_ctx->plane_res.scl_data.taps.v_taps_c != temp.v_taps_c ||

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1624

pipe_ctx->plane_res.scl_data.taps.h_taps_c != temp.h_taps_c))

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1625

calculate_inits_and_viewports(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1632

if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state == plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1634

(pipe_ctx->stream->view_format != VIEW_3D_FORMAT_TOP_AND_BOTTOM &&

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1635

pipe_ctx->stream->view_format != VIEW_3D_FORMAT_SIDE_BY_SIDE));

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1636

if (pipe_ctx->stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1637

pipe_ctx->plane_res.scl_data.recout.y += pipe_ctx->plane_res.scl_data.recout.height;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1638

else if (pipe_ctx->stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1639

pipe_ctx->plane_res.scl_data.recout.x += pipe_ctx->plane_res.scl_data.recout.width;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1643

if (pipe_ctx->plane_res.scl_data.viewport.height < MIN_VIEWPORT_SIZE)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1644

pipe_ctx->plane_res.scl_data.viewport.height = MIN_VIEWPORT_SIZE;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1645

if (pipe_ctx->plane_res.scl_data.viewport.width < MIN_VIEWPORT_SIZE)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1646

pipe_ctx->plane_res.scl_data.viewport.width = MIN_VIEWPORT_SIZE;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1653

pipe_ctx->pipe_idx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1654

pipe_ctx->plane_res.scl_data.viewport.height,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1655

pipe_ctx->plane_res.scl_data.viewport.width,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1656

pipe_ctx->plane_res.scl_data.viewport.x,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1657

pipe_ctx->plane_res.scl_data.viewport.y,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1658

pipe_ctx->plane_res.scl_data.recout.height,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1659

pipe_ctx->plane_res.scl_data.recout.width,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1660

pipe_ctx->plane_res.scl_data.recout.x,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1661

pipe_ctx->plane_res.scl_data.recout.y,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1662

pipe_ctx->plane_res.scl_data.h_active,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1663

pipe_ctx->plane_res.scl_data.v_active,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1677

pipe_ctx->stream->dst.x -= timing->h_border_left;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1678

pipe_ctx->stream->dst.y -= timing->v_border_top;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1683

bool resource_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1685

struct pipe_ctx *test_pipe, *split_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1686

struct rect r1 = pipe_ctx->plane_res.scl_data.recout;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1688

int cur_layer = pipe_ctx->plane_state->layer_index;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1690

reverse_adjust_recout_for_visual_confirm(&r1, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1699

for (test_pipe = pipe_ctx->top_pipe; test_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1718

for (split_pipe = pipe_ctx->top_pipe; split_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1747

if (context->res_ctx.pipe_ctx[i].plane_state != NULL &&

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1748

context->res_ctx.pipe_ctx[i].stream != NULL)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1749

if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1756

struct pipe_ctx *resource_find_free_secondary_pipe_legacy(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1759

const struct pipe_ctx *primary_pipe)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1762

struct pipe_ctx *secondary_pipe = NULL;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1794

if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1795

secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1806

if (res_ctx->pipe_ctx[i].stream == NULL) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1807

secondary_pipe = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1819

const struct pipe_ctx *cur_otg_master)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1821

const struct pipe_ctx *cur_sec_opp_head = cur_otg_master->next_odm_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1822

struct pipe_ctx *new_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1826

new_pipe = &new_res_ctx->pipe_ctx[cur_sec_opp_head->pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1840

const struct pipe_ctx *cur_opp_head)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1842

const struct pipe_ctx *cur_sec_dpp = cur_opp_head->bottom_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1843

struct pipe_ctx *new_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1851

new_pipe = &new_res_ctx->pipe_ctx[cur_sec_dpp->pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1868

const struct pipe_ctx *new_pipe, *cur_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1872

cur_pipe = &cur_res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1873

new_pipe = &new_res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1891

const struct pipe_ctx *new_pipe, *cur_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1895

cur_pipe = &cur_res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1896

new_pipe = &new_res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1914

const struct pipe_ctx *new_pipe, *cur_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1918

cur_pipe = &cur_res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1919

new_pipe = &new_res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1938

const struct pipe_ctx *new_pipe, *cur_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1942

cur_pipe = &cur_res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1943

new_pipe = &new_res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1961

const struct pipe_ctx *new_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1965

new_pipe = &new_res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1976

bool resource_is_pipe_type(const struct pipe_ctx *pipe_ctx, enum pipe_type type)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1980

return !pipe_ctx->prev_odm_pipe &&

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1981

!pipe_ctx->top_pipe &&

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1982

pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1984

return !pipe_ctx->top_pipe && pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1986

return pipe_ctx->plane_state && pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1988

return !pipe_ctx->plane_state && !pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1994

struct pipe_ctx *resource_get_otg_master_for_stream(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2001

if (res_ctx->pipe_ctx[i].stream == stream &&

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2002

resource_is_pipe_type(&res_ctx->pipe_ctx[i], OTG_MASTER))

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2003

return &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2008

int resource_get_opp_heads_for_otg_master(const struct pipe_ctx *otg_master,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2010

struct pipe_ctx *opp_heads[MAX_PIPES])

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2012

struct pipe_ctx *opp_head = &res_ctx->pipe_ctx[otg_master->pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2033

int resource_get_dpp_pipes_for_opp_head(const struct pipe_ctx *opp_head,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2035

struct pipe_ctx *dpp_pipes[MAX_PIPES])

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2037

struct pipe_ctx *pipe = &res_ctx->pipe_ctx[opp_head->pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2054

struct pipe_ctx *dpp_pipes[MAX_PIPES])

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2057

struct pipe_ctx *pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2060

pipe = &res_ctx->pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2083

struct pipe_ctx *resource_get_otg_master(const struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2085

struct pipe_ctx *otg_master = resource_get_opp_head(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2092

struct pipe_ctx *resource_get_opp_head(const struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2094

struct pipe_ctx *opp_head = (struct pipe_ctx *) pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2102

struct pipe_ctx *resource_get_primary_dpp_pipe(const struct pipe_ctx *dpp_pipe)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2104

struct pipe_ctx *pri_dpp_pipe = (struct pipe_ctx *) dpp_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2116

int resource_get_mpc_slice_index(const struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2118

struct pipe_ctx *split_pipe = pipe_ctx->top_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2121

while (split_pipe && split_pipe->plane_state == pipe_ctx->plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2129

int resource_get_mpc_slice_count(const struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2132

const struct pipe_ctx *other_pipe = pipe->bottom_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2147

int resource_get_odm_slice_count(const struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2160

int resource_get_odm_slice_index(const struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2164

pipe_ctx = resource_get_opp_head(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2165

if (!pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2168

while (pipe_ctx->prev_odm_pipe) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2170

pipe_ctx = pipe_ctx->prev_odm_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2176

int resource_get_odm_slice_dst_width(struct pipe_ctx *otg_master,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2214

struct rect resource_get_odm_slice_dst_rect(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2216

const struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2217

bool is_last_odm_slice = pipe_ctx->next_odm_pipe == NULL;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2218

struct pipe_ctx *otg_master = resource_get_otg_master(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2219

int odm_slice_idx = resource_get_odm_slice_index(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2233

struct rect resource_get_odm_slice_src_rect(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2237

struct pipe_ctx *opp_head = resource_get_opp_head(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2247

opp, pipe_ctx->stream->timing.pixel_encoding,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2262

const struct pipe_ctx *pipe_a, *pipe_b;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2268

pipe_a = &state_a->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2269

pipe_b = &state_b->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2304

bool resource_is_odm_topology_changed(const struct pipe_ctx *otg_master_a,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2305

const struct pipe_ctx *otg_master_b)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2307

const struct pipe_ctx *opp_head_a = otg_master_a;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2308

const struct pipe_ctx *opp_head_b = otg_master_b;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2346

static void resource_log_pipe(struct dc *dc, struct pipe_ctx *pipe,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2420

struct pipe_ctx *otg_master, int stream_idx, bool is_phantom_pipe)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2422

struct pipe_ctx *opp_heads[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2423

struct pipe_ctx *dpp_pipes[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2479

struct pipe_ctx *otg_master;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2521

static struct pipe_ctx *get_tail_pipe(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2522

struct pipe_ctx *head_pipe)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2524

struct pipe_ctx *tail_pipe = head_pipe->bottom_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2534

static struct pipe_ctx *get_last_opp_head(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2535

struct pipe_ctx *opp_head)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2543

static struct pipe_ctx *get_last_dpp_pipe_in_mpcc_combine(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2544

struct pipe_ctx *dpp_pipe)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2554

struct pipe_ctx *otg_master,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2559

struct pipe_ctx *pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2563

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2582

struct pipe_ctx *pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2586

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2601

struct pipe_ctx *split_pipe = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2709

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2725

pipe_ctx->link_res.hpo_dp_link_enc = pool->hpo_dp_link_enc[enc_index];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2727

return pipe_ctx->link_res.hpo_dp_link_enc != NULL;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2731

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2740

pipe_ctx->link_res.hpo_dp_link_enc = NULL;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2774

if ((res_ctx->pipe_ctx[i].stream == stream) &&

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2775

(res_ctx->pipe_ctx[i].stream_res.stream_enc != NULL)) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2776

stream_enc_inst = res_ctx->pipe_ctx[i].stream_res.stream_enc->id;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2857

struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2859

if (pipe_ctx && pipe_ctx->link_res.dio_link_enc == pool->link_encoders[old_encoder])

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2860

pipe_ctx->link_res.dio_link_enc = pool->link_encoders[new_encoder];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2867

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2903

pipe_ctx->link_res.dio_link_enc = pool->link_encoders[enc_index];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2905

return pipe_ctx->link_res.dio_link_enc != NULL;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2909

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2919

pipe_ctx->link_res.dio_link_enc = NULL;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2929

if (resource_is_pipe_type(&context->res_ctx.pipe_ctx[i], FREE_PIPE))

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2947

struct pipe_ctx *otg_master = resource_get_otg_master_for_stream(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3016

static bool add_plane_to_opp_head_pipes(struct pipe_ctx *otg_master_pipe,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3020

struct pipe_ctx *opp_head_pipe = otg_master_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3066

struct pipe_ctx *otg_master_pipe,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3072

struct pipe_ctx *sec_pipe, *tail_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3073

struct pipe_ctx *opp_heads[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3117

struct pipe_ctx *otg_master_pipe,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3149

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3151

if (pipe_ctx->plane_state == plane_state) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3152

if (pipe_ctx->top_pipe)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3153

pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3159

if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3160

pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3166

if (!pipe_ctx->top_pipe)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3167

pipe_ctx->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3169

memset(pipe_ctx, 0, sizeof(*pipe_ctx));

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3208

struct pipe_ctx *otg_master_pipe,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3213

struct pipe_ctx *last_opp_head = get_last_opp_head(otg_master_pipe);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3214

struct pipe_ctx *new_opp_head;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3215

struct pipe_ctx *last_top_dpp_pipe, *last_bottom_dpp_pipe,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3288

struct pipe_ctx *otg_master_pipe,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3292

struct pipe_ctx *last_opp_head = get_last_opp_head(otg_master_pipe);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3293

struct pipe_ctx *tail_pipe = get_tail_pipe(last_opp_head);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3347

struct pipe_ctx *dpp_pipe,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3352

struct pipe_ctx *last_dpp_pipe =

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3354

struct pipe_ctx *opp_head = resource_get_opp_head(dpp_pipe);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3355

struct pipe_ctx *new_dpp_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3410

struct pipe_ctx *dpp_pipe,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3414

struct pipe_ctx *last_dpp_pipe =

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3442

struct pipe_ctx *otg_master = resource_get_otg_master_for_stream(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3479

struct pipe_ctx *dpp_pipes[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3763

if (!res_ctx->pipe_ctx[tg_inst].stream) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3764

struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3766

pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3769

if (pipe_ctx->stream_res.tg->funcs->get_optc_source)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3770

pipe_ctx->stream_res.tg->funcs->get_optc_source(pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3783

pipe_ctx = &res_ctx->pipe_ctx[id_src[i]];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3785

pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3786

pipe_ctx->plane_res.mi = pool->mis[id_src[i]];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3787

pipe_ctx->plane_res.hubp = pool->hubps[id_src[i]];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3788

pipe_ctx->plane_res.ipp = pool->ipps[id_src[i]];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3789

pipe_ctx->plane_res.xfm = pool->transforms[id_src[i]];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3790

pipe_ctx->plane_res.dpp = pool->dpps[id_src[i]];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3791

pipe_ctx->stream_res.opp = pool->opps[id_src[i]];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3794

pipe_ctx->plane_res.mpcc_inst = pool->dpps[id_src[i]]->inst;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3799

pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3802

pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id =

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3806

pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot =

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3810

pipe_ctx->stream_res.opp->mpc_tree_params.opp_id = s.opp_id;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3813

pipe_ctx->pipe_idx = id_src[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3818

pipe_ctx->stream_res.tg = pool->timing_generators[id_src[i]];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3819

pipe_ctx->stream_res.opp = pool->opps[id_src[i]];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3822

pipe_ctx->stream = stream;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3827

res_ctx->pipe_ctx[id_src[0]].next_odm_pipe = &res_ctx->pipe_ctx[id_src[1]];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3828

res_ctx->pipe_ctx[id_src[0]].prev_odm_pipe = NULL;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3829

res_ctx->pipe_ctx[id_src[1]].next_odm_pipe = NULL;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3830

res_ctx->pipe_ctx[id_src[1]].prev_odm_pipe = &res_ctx->pipe_ctx[id_src[0]];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3888

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3927

pipe_ctx = &new_ctx->res_ctx.pipe_ctx[pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3928

memset(pipe_ctx, 0, sizeof(*pipe_ctx));

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3929

pipe_ctx->pipe_idx = pipe_idx;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3930

pipe_ctx->stream_res.tg = pool->timing_generators[pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3931

pipe_ctx->plane_res.mi = pool->mis[pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3932

pipe_ctx->plane_res.hubp = pool->hubps[pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3933

pipe_ctx->plane_res.ipp = pool->ipps[pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3934

pipe_ctx->plane_res.xfm = pool->transforms[pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3935

pipe_ctx->plane_res.dpp = pool->dpps[pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3936

pipe_ctx->stream_res.opp = pool->opps[pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3938

pipe_ctx->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3943

pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3944

pipe_ctx->stream_res.opp = pool->opps[tg_inst];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3947

pipe_ctx->stream = stream;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3963

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3989

pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3991

if (!pipe_ctx || pipe_ctx->stream_res.tg == NULL)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3994

pipe_ctx->stream_res.stream_enc =

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3998

if (!pipe_ctx->stream_res.stream_enc)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4003

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4012

&pipe_ctx->link_config.dp_link_settings))

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4016

&pipe_ctx->link_config.dp_tunnel_settings);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4019

&pipe_ctx->link_config.dp_link_settings) == DP_128b_132b_ENCODING) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4020

pipe_ctx->stream_res.hpo_dp_stream_enc =

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4024

if (!pipe_ctx->stream_res.hpo_dp_stream_enc)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4029

pipe_ctx->stream_res.hpo_dp_stream_enc,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4031

if (!add_hpo_dp_link_enc_to_ctx(&context->res_ctx, pool, pipe_ctx, stream))

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4037

if (!add_dio_link_enc_to_ctx(dc, context, pool, pipe_ctx, stream))

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4042

dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4046

pipe_ctx->stream_res.audio = find_first_free_audio(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4047

&context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id, dc_ctx->dce_version);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4054

if (pipe_ctx->stream_res.audio)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4056

pipe_ctx->stream_res.audio, true);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4060

if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4062

pipe_ctx->stream_res.abm = pool->abm;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4064

pipe_ctx->stream_res.abm = pool->multiple_abms[pipe_ctx->stream_res.tg->inst];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4069

context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4070

context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->stream_enc_inst;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4072

pipe_ctx->stream_res.audio ? pipe_ctx->stream_res.audio->inst : -1;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4377

static void calculate_timing_params_for_dsc_with_padding(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4381

if (!pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4384

stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4385

pipe_ctx->dsc_padding_params.dsc_hactive_padding = 0;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4386

pipe_ctx->dsc_padding_params.dsc_htotal_padding = 0;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4389

pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz = stream->timing.pix_clk_100hz;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4426

struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4428

if (pipe_ctx->stream != stream)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4433

calculate_timing_params_for_dsc_with_padding(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4436

pipe_ctx->plane_state &&

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4437

pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4438

result = dc->res_pool->funcs->patch_unknown_plane_state(pipe_ctx->plane_state);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4447

if (dc_is_dp_signal(pipe_ctx->stream->signal) &&

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4453

pipe_ctx->clock_source);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4455

pipe_ctx->clock_source = dc->res_pool->dp_clock_source;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4459

pipe_ctx->clock_source);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4493

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4495

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4503

unsigned int vic = pipe_ctx->stream->timing.vic;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4504

unsigned int rid = pipe_ctx->stream->timing.rid;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4505

unsigned int fr_ind = pipe_ctx->stream->timing.fr_index;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4516

color_space = pipe_ctx->stream->output_color_space;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4658

if (pipe_ctx->stream->timing.hdmi_vic != 0)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4664

switch (pipe_ctx->stream->timing.hdmi_vic) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4880

void resource_build_info_frame(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4883

struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4896

signal = pipe_ctx->stream->signal;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4898

if (pipe_ctx->stream->ctx->dc->res_pool->funcs->get_vstartup_for_pipe)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4899

vstartup_start = pipe_ctx->stream->ctx->dc->res_pool->funcs->get_vstartup_for_pipe(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4903

set_avi_info_frame(&info->avi, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4905

set_vendor_info_packet(&info->vendor, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4906

set_hfvs_info_packet(&info->hfvsif, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4907

set_vtem_info_packet(&info->vtem, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4909

set_spd_info_packet(&info->spd, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4911

set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4914

set_vsc_info_packet(&info->vsc, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4916

set_spd_info_packet(&info->spd, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4918

set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4920

pipe_ctx->stream,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4935

struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4938

if (!pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4941

if (dc_is_dp_signal(pipe_ctx->stream->signal)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4942

|| pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4943

pipe_ctx->clock_source = pool->dp_clock_source;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4945

pipe_ctx->clock_source = NULL;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4948

pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4950

pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4952

if (pipe_ctx->clock_source == NULL)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4953

pipe_ctx->clock_source =

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4959

if (pipe_ctx->clock_source == NULL)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4964

pipe_ctx->clock_source);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4975

struct pipe_ctx *pipe_ctx_old,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4976

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4981

if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4984

if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4987

if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4990

if (pipe_ctx_old->clock_source != pipe_ctx->clock_source

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4991

&& pipe_ctx_old->stream != pipe_ctx->stream)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4994

if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4997

if (dc_is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5000

if (pipe_ctx_old->stream->dpms_off != pipe_ctx->stream->dpms_off)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5007

if (pipe_ctx_old->stream_res.dsc != pipe_ctx->stream_res.dsc)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5010

if (pipe_ctx_old->stream_res.hpo_dp_stream_enc != pipe_ctx->stream_res.hpo_dp_stream_enc)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5012

if (pipe_ctx_old->link_res.hpo_dp_link_enc != pipe_ctx->link_res.hpo_dp_link_enc)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5017

if (pipe_ctx_old->link_res.dio_link_enc != pipe_ctx->link_res.dio_link_enc)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5025

if (link_enc_prev != pipe_ctx->stream->link_enc)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5354

struct pipe_ctx *pipe_ctx_old, *pipe_ctx, *pipe_ctx_syncd;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5358

pipe_ctx_old = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5359

pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5364

if (!pipe_ctx->stream ||

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5365

pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5369

pipe_ctx_syncd = &context->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5383

struct pipe_ctx *pipe_ctx, *pipe_ctx_check;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5385

pipe_ctx = &context->res_ctx.pipe_ctx[disabled_master_pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5386

if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx) != disabled_master_pipe_idx) ||

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5387

!IS_PIPE_SYNCD_VALID(pipe_ctx))

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5388

SET_PIPE_SYNCD_TO_PIPE(pipe_ctx, disabled_master_pipe_idx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5392

pipe_ctx_check = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5396

struct pipe_ctx *first_pipe = pipe_ctx_check;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5417

struct pipe_ctx *pipe_ctx_reset;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5421

pipe_ctx_reset = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5531

struct pipe_ctx *pri_pipe,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5532

struct pipe_ctx *sec_pipe,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5536

struct pipe_ctx *sec_top, *sec_bottom, *sec_next, *sec_prev;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5585

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5587

if (dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings) == DP_128b_132b_ENCODING) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5588

if (pipe_ctx->stream_res.hpo_dp_stream_enc == NULL) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5589

pipe_ctx->stream_res.hpo_dp_stream_enc =

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5591

&context->res_ctx, dc->res_pool, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5593

if (!pipe_ctx->stream_res.hpo_dp_stream_enc)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5598

pipe_ctx->stream_res.hpo_dp_stream_enc,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5602

if (pipe_ctx->link_res.hpo_dp_link_enc == NULL) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5603

if (!add_hpo_dp_link_enc_to_ctx(&context->res_ctx, dc->res_pool, pipe_ctx, pipe_ctx->stream))

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5607

if (pipe_ctx->stream_res.hpo_dp_stream_enc) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5610

pipe_ctx->stream_res.hpo_dp_stream_enc,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5612

pipe_ctx->stream_res.hpo_dp_stream_enc = NULL;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5614

if (pipe_ctx->link_res.hpo_dp_link_enc)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5615

remove_hpo_dp_link_enc_from_ctx(&context->res_ctx, pipe_ctx, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5618

if (pipe_ctx->link_res.dio_link_enc == NULL && dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5619

if (!add_dio_link_enc_to_ctx(dc, context, dc->res_pool, pipe_ctx, pipe_ctx->stream))

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5625

struct dscl_prog_data *resource_get_dscl_prog_data(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5627

return &pipe_ctx->plane_res.scl_data.dscl_prog_data;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5677

int resource_calculate_det_for_stream(struct dc_state *state, struct pipe_ctx *otg_master)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5679

struct pipe_ctx *opp_heads[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5680

struct pipe_ctx *dpp_pipes[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

701

const struct pipe_ctx *pipe_with_clk_src,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

702

const struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

733

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

738

if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

739

return res_ctx->pipe_ctx[i].clock_source;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

852

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

916

const struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

942

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

945

const struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

946

int mpc_slice_count = resource_get_mpc_slice_count(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

947

int mpc_slice_idx = resource_get_mpc_slice_index(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

977

static void calculate_adjust_recout_for_visual_confirm(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

980

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

984

if (dc->debug.visual_confirm == VISUAL_CONFIRM_DISABLE || !pipe_ctx->plane_res.dpp)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

987

*dpp_offset = pipe_ctx->stream->timing.v_addressable / VISUAL_CONFIRM_DPP_OFFSET_DENO;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

988

*dpp_offset *= pipe_ctx->plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

998

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

152

struct pipe_ctx *cur_pipe = &dst_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_state.c

155

cur_pipe->top_pipe = &dst_state->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_state.c

158

cur_pipe->bottom_pipe = &dst_state->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_state.c

161

cur_pipe->prev_odm_pipe = &dst_state->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_state.c

164

cur_pipe->next_odm_pipe = &dst_state->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_state.c

407

struct pipe_ctx *del_pipe = resource_get_otg_master_for_stream(

drivers/gpu/drm/amd/display/dc/core/dc_state.c

469

struct pipe_ctx *otg_master_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_state.c

670

const struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_state.c

672

return dc_state_get_stream_subvp_type(state, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

924

struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

258

struct pipe_ctx *pipe_to_program = NULL;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

267

struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

269

if (pipe_ctx->stream != stream)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

273

pipe_to_program = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

276

dc->hwss.begin_cursor_offload_update(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

284

dc->hwss.set_cursor_attribute(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

286

dc_send_update_cursor_info_to_dmu(pipe_ctx, i);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

288

dc->hwss.set_cursor_sdr_white_level(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

290

dc->hwss.update_cursor_offload_pipe(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

405

struct pipe_ctx *pipe_to_program = NULL;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

414

struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

416

if (pipe_ctx->stream != stream ||

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

417

(!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) ||

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

418

!pipe_ctx->plane_state ||

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

419

(!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) ||

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

420

(!pipe_ctx->plane_res.ipp && !pipe_ctx->plane_res.dpp))

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

424

pipe_to_program = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

427

dc->hwss.begin_cursor_offload_update(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

432

dc->hwss.set_cursor_position(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

434

dc->hwss.update_cursor_offload_pipe(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

437

dc_send_update_cursor_info_to_dmu(pipe_ctx, i);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

504

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

507

if (stream == pipe_ctx->stream) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

508

get_cursor_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

511

if (pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

512

dc->hwss.update_visual_confirm_color(dc, pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

513

pipe_ctx->plane_res.hubp->mpcc_id);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

523

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

526

if (stream == pipe_ctx->stream) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

527

pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

716

struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

718

if (res_ctx->pipe_ctx[i].stream != stream || !tg)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

746

struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

748

if (pipe_ctx->stream != stream)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

752

dc->hwss.send_immediate_sdp_message(pipe_ctx,

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

784

struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

786

if (res_ctx->pipe_ctx[i].stream != stream || !tg)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

804

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

811

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

828

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

841

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

842

if (pipe_ctx->stream == stream)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

849

hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

853

pipe_ctx->stream->dmdata_address = attr->address;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

857

dc->hwss.program_dmdata_engine(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

860

pipe_ctx->stream->dmdata_address.quad_part != 0) {

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

878

struct pipe_ctx *dc_stream_get_pipe_ctx(struct dc_stream_state *stream)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

883

struct pipe_ctx *pipe = &stream->ctx->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

134

struct pipe_ctx *pipe_ctx =

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

135

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

137

if (pipe_ctx->plane_state != plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

140

if (pipe_ctx->plane_state && flags.bits.address)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

141

pipe_ctx->plane_state->status.is_flip_pending = false;

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

149

struct pipe_ctx *pipe_ctx =

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

150

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

152

if (pipe_ctx->plane_state != plane_state)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

156

dc->hwss.update_pending_status(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

290

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

292

if (!pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

296

dc->hwss.clear_surface_dcc_and_tiling(pipe_ctx, plane_state, clear_tiling);

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

74

struct pipe_ctx *pipe_ctx = &dc_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

76

if (pipe_ctx->plane_state == plane_state && pipe_ctx->plane_res.hubp)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

77

pipe_mask |= 1 << pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/dc.h

2282

bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1014

static bool dc_dmub_should_update_cursor_data(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1016

if (pipe_ctx->plane_state != NULL) {

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1017

if (pipe_ctx->plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE ||

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1018

resource_can_pipe_disable_cursor(pipe_ctx))

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1022

if ((pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1 ||

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1023

pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_1) &&

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1024

pipe_ctx->stream->ctx->dce_version >= DCN_VERSION_3_1)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1027

if (pipe_ctx->stream->link->replay_settings.config.replay_supported)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1034

struct pipe_ctx *pipe_ctx, uint8_t p_idx,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1037

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1038

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1046

pipe_ctx->stream->link, &panel_inst))

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1063

payload->otg_inst = pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1106

struct pipe_ctx *pCtx, uint8_t pipe_idx)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1229

struct pipe_ctx const *pipe_ctx;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1239

pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1240

if (!pipe_ctx || !pipe_ctx->stream_res.tg || pipe_ctx->stream != stream)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1251

cntl->data.otg_inst = pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1263

void dc_dmub_srv_program_cursor_now(struct dc *dc, const struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

421

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

430

struct pipe_ctx *head_pipe,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

438

struct pipe_ctx *split_pipe = &context->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

469

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

487

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

494

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

538

void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

543

if (!dc_get_edp_link_panel_inst(dc, pipe_ctx->stream->link, &panel_inst) &&

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

584

struct pipe_ctx *subvp_pipe,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

585

struct pipe_ctx *vblank_pipe,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

664

struct pipe_ctx *vblank_pipe,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

668

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

674

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

720

struct pipe_ctx *subvp_pipes[])

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

785

struct pipe_ctx *subvp_pipe,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

850

struct pipe_ctx *phantom_pipe = &context->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

885

struct pipe_ctx *subvp_pipes[2];

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

897

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

910

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

103

void dc_send_update_cursor_info_to_dmu(struct pipe_ctx *pCtx, uint8_t pipe_idx);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

34

struct pipe_ctx;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

353

void dc_dmub_srv_program_cursor_now(struct dc *dc, const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

93

void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

119

resource_get_mpc_slice_count(pipe_ctx);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

124

spl_in->basic_in.mpc_h_slice_index = resource_get_mpc_slice_index(pipe_ctx);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

128

spl_in->odm_slice_index = resource_get_odm_slice_index(pipe_ctx);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

131

stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right + pipe_ctx->dsc_padding_params.dsc_hactive_padding;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

136

pipe_ctx->stream->ctx->dc->debug.max_downscale_src_width;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

137

spl_in->basic_out.always_scale = pipe_ctx->stream->ctx->dc->debug.always_scale;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

139

spl_in->basic_out.alpha_en = pipe_ctx->plane_res.scl_data.lb_params.alpha_en;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

140

spl_in->basic_out.use_two_pixels_per_container = pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

144

spl_in->prefer_easf = pipe_ctx->stream->ctx->dc->config.prefer_easf;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

146

if (pipe_ctx->stream->ctx->dc->debug.force_easf == 1)

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

148

else if (pipe_ctx->stream->ctx->dc->debug.force_easf == 2)

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

150

else if (pipe_ctx->stream->ctx->dc->debug.force_easf == 3)

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

153

unsigned int sharpness_setting = pipe_ctx->stream->ctx->dc->debug.force_sharpness;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

154

unsigned int force_sharpness_level = pipe_ctx->stream->ctx->dc->debug.force_sharpness_level;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

186

if (pipe_ctx->stream->ctx->dc->debug.force_lls > 0)

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

187

spl_in->lls_pref = pipe_ctx->stream->ctx->dc->debug.force_lls;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

191

if (pipe_ctx->stream->ctx->dc->debug.force_cositing)

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

192

spl_in->basic_in.cositing = pipe_ctx->stream->ctx->dc->debug.force_cositing - 1;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

199

spl_in->h_active = pipe_ctx->plane_res.scl_data.h_active;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

200

spl_in->v_active = pipe_ctx->plane_res.scl_data.v_active;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

204

(enum scale_to_sharpness_policy)pipe_ctx->stream->ctx->dc->debug.scale_to_sharpness_policy;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

209

spl_in->is_fullscreen = pipe_ctx->stream->sharpening_required;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

210

spl_in->is_hdr_on = dm_helpers_is_hdr_on(pipe_ctx->stream->ctx, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

217

void translate_SPL_out_params_to_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl_out *spl_out)

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

220

populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.recout, &spl_out->dscl_prog_data->recout);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

222

populate_ratios_from_splratios(&pipe_ctx->plane_res.scl_data.ratios, &spl_out->dscl_prog_data->ratios);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

224

populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.viewport, &spl_out->dscl_prog_data->viewport);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

226

populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.viewport_c, &spl_out->dscl_prog_data->viewport_c);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

228

populate_taps_from_spltaps(&pipe_ctx->plane_res.scl_data.taps, &spl_out->dscl_prog_data->taps);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

230

populate_inits_from_splinits(&pipe_ctx->plane_res.scl_data.inits, &spl_out->dscl_prog_data->init);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

76

void translate_SPL_in_params_from_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl_in *spl_in)

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

78

const struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

79

const struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

80

struct rect odm_slice_src = resource_get_odm_slice_src_rect(pipe_ctx);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

98

populate_splformat_from_format(&spl_in->basic_in.format, pipe_ctx->plane_res.scl_data.format);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.h

15

void translate_SPL_in_params_from_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl_in *spl_in);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.h

21

void translate_SPL_out_params_to_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl_out *spl_out);

drivers/gpu/drm/amd/display/dc/dc_state_priv.h

38

const struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/dc_stream.h

634

struct pipe_ctx *dc_stream_get_pipe_ctx(struct dc_stream_state *stream);

drivers/gpu/drm/amd/display/dc/dc_trace.h

26

#define TRACE_DC_PIPE_STATE(pipe_ctx, index, max_pipes) \

drivers/gpu/drm/amd/display/dc/dc_trace.h

28

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[index]; \

drivers/gpu/drm/amd/display/dc/dc_trace.h

29

if (pipe_ctx->plane_state) \

drivers/gpu/drm/amd/display/dc/dc_trace.h

30

trace_amdgpu_dm_dc_pipe_state(pipe_ctx->pipe_idx, pipe_ctx->plane_state, \

drivers/gpu/drm/amd/display/dc/dc_trace.h

31

pipe_ctx->stream, &pipe_ctx->plane_res, \

drivers/gpu/drm/amd/display/dc/dc_trace.h

32

pipe_ctx->update_flags.raw); \

drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c

190

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c

192

if (pipe_ctx->stream == NULL)

drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c

196

if (pipe_ctx->top_pipe)

drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c

199

if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 > max_pix_clk)

drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c

200

max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10;

drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c

205

if (dc_is_dp_signal(pipe_ctx->stream->signal) &&

drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c

206

pipe_ctx->stream_res.pix_clk_params.requested_sym_clk > max_pix_clk)

drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c

207

max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk;

drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c

508

const struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c

511

if (stream == context->res_ctx.pipe_ctx[k].stream) {

drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c

512

pipe_ctx = &context->res_ctx.pipe_ctx[k];

drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c

516

ASSERT(pipe_ctx != NULL);

drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c

523

cfg->signal = pipe_ctx->stream->signal;

drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c

524

cfg->pipe_idx = pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

301

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

306

if (res_ctx->pipe_ctx[i].stream &&

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

307

res_ctx->pipe_ctx[i].stream->link == link &&

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

308

res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) {

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

309

pipe_ctx = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

315

if (!pipe_ctx)

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

319

if (!dmub_psr_set_version(dmub, pipe_ctx->stream, panel_inst))

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

341

copy_settings_data->mpcc_inst = pipe_ctx->plane_res.mpcc_inst;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

343

if (pipe_ctx->plane_res.dpp)

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

344

copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

347

if (pipe_ctx->stream_res.opp)

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

348

copy_settings_data->opp_inst = pipe_ctx->stream_res.opp->inst;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

351

if (pipe_ctx->stream_res.tg)

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

352

copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

382

copy_settings_data->dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1);

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

124

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

130

res_ctx->pipe_ctx[i].stream &&

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

131

res_ctx->pipe_ctx[i].stream->link &&

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

132

res_ctx->pipe_ctx[i].stream->link == link &&

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

133

res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) {

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

134

pipe_ctx = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

140

if (!pipe_ctx)

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

153

if (pipe_ctx->plane_res.dpp)

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

154

copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

157

if (pipe_ctx->stream_res.tg)

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

158

copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

178

copy_settings_data->flags.bitfields.dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

435

pix_clk = dc->current_state->res_ctx.pipe_ctx[i].stream_res.pix_clk_params.requested_pix_clk_100hz / 10;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1200

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1235

struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

302

const struct pipe_ctx *pipe,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

455

struct pipe_ctx *pipe,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

525

struct pipe_ctx *primary_pipe,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

526

struct pipe_ctx *secondary_pipe)

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

710

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

894

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1000

if (!res_ctx->pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1042

wb_arb_params->time_per_pixel = 16.0 * 1000 / (context->res_ctx.pipe_ctx[i].stream->phy_pix_clk / 1000); /* 4 bit fraction, ms */

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1049

if (!context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1051

if (dc->link_srv->dp_is_128b_132b_signal(&context->res_ctx.pipe_ctx[i]))

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1064

if (context->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1180

if (!context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1182

if (context->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1189

if (dc_state_get_pipe_subvp_type(context, &context->res_ctx.pipe_ctx[i]) == SUBVP_PHANTOM) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1191

context->res_ctx.pipe_ctx[i].det_buffer_size_kb = 0;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1192

context->res_ctx.pipe_ctx[i].unbounded_req = false;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1194

context->res_ctx.pipe_ctx[i].det_buffer_size_kb = context->bw_ctx.dml.ip.det_buffer_size_kbytes;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1195

context->res_ctx.pipe_ctx[i].unbounded_req = pipes[pipe_idx].pipe.src.unbounded_req_mode;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1200

context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1202

context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1204

context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1206

&context->res_ctx.pipe_ctx[i].stream->timing,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1207

&context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start);

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1227

if (!context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1235

&context->res_ctx.pipe_ctx[i].dlg_regs,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1236

&context->res_ctx.pipe_ctx[i].ttu_regs,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1245

&context->res_ctx.pipe_ctx[i].rq_regs,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1326

if (!res_ctx->pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1334

if (res_ctx->pipe_ctx[pipe_cnt].stream == res_ctx->pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1339

res_ctx->pipe_ctx[pipe_cnt].stream,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1340

res_ctx->pipe_ctx[i].stream) &&

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1342

res_ctx->pipe_ctx[pipe_cnt].stream,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1343

res_ctx->pipe_ctx[i].stream))) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1350

struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1356

if (!res_ctx->pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1371

pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1373

pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1374

if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1382

dc_is_dp_signal(res_ctx->pipe_ctx[i].stream->signal) ? 36 : 32;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1408

pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1412

pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1413

pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1414

switch (resource_get_odm_slice_count(&res_ctx->pipe_ctx[i])) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1424

pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1425

if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1426

== res_ctx->pipe_ctx[i].plane_state) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1427

struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].top_pipe;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1431

== res_ctx->pipe_ctx[i].plane_state) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1439

pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1441

pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1442

} else if (res_ctx->pipe_ctx[i].prev_odm_pipe) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1443

struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1450

switch (res_ctx->pipe_ctx[i].stream->signal) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1454

if (dc->link_srv->dp_is_128b_132b_signal(&res_ctx->pipe_ctx[i]))

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1472

switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1502

switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1513

if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC &&

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1514

!res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.ycbcr422_simple)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1525

if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1526

pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.0;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1531

get_audio_check(&res_ctx->pipe_ctx[i].stream->audio_info, &aud_check);

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1537

if (res_ctx->pipe_ctx[i].plane_state &&

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1538

(res_ctx->pipe_ctx[i].plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE ||

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1539

dc_state_get_pipe_subvp_type(context, &res_ctx->pipe_ctx[i]) == SUBVP_PHANTOM))

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1547

if (!res_ctx->pipe_ctx[i].plane_state) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1588

struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1589

struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1592

pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1593

|| (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1600

pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1656

struct pipe_ctx *split_pipe = res_ctx->pipe_ctx[i].bottom_pipe;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1662

split_pipe = res_ctx->pipe_ctx[i].top_pipe;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1742

if (!context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2252

if (!context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2486

struct dc_stream_state *stream = res_ctx->pipe_ctx[i].stream;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2499

(wb_info->writeback_source_plane == res_ctx->pipe_ctx[i].plane_state)) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

998

struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0];

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

192

struct dc_stream_state *stream = res_ctx->pipe_ctx[i].stream;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

205

(wb_info->writeback_source_plane == res_ctx->pipe_ctx[i].plane_state)) {

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

479

if (!context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

468

if (!context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

538

if (!context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

541

if (context->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

573

if (context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

574

context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = 0;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

577

if (!context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

580

context->res_ctx.pipe_ctx[i].det_buffer_size_kb =

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

582

if (context->res_ctx.pipe_ctx[i].det_buffer_size_kb > 384)

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

583

context->res_ctx.pipe_ctx[i].det_buffer_size_kb /= 2;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

584

total_det += context->res_ctx.pipe_ctx[i].det_buffer_size_kb;

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

313

struct pipe_ctx *pipe = 0;

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

326

if (!res_ctx->pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

328

pipe = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

416

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1049

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1099

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1101

if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) &&

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1102

dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_MAIN) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1103

pipe_ctx->subvp_index = index++;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1105

pipe_ctx->subvp_index = 0;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1118

struct pipe_ctx *pri_pipe;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1146

struct pipe_ctx *dpp_pipe, struct dc_plane_state *plane, int diff)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1149

struct pipe_ctx *pri_dpp_pipe = resource_get_primary_dpp_pipe(dpp_pipe);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1172

struct pipe_ctx *otg_master;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1173

struct pipe_ctx *dpp_pipes[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1225

struct pipe_ctx *pipe;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1232

pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1605

if (!context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1607

if (dc->link_srv->dp_is_128b_132b_signal(&context->res_ctx.pipe_ctx[i]))

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1701

if (!context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1703

if (context->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1714

if (dc_state_get_pipe_subvp_type(context, &context->res_ctx.pipe_ctx[i]) == SUBVP_PHANTOM) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1716

context->res_ctx.pipe_ctx[i].det_buffer_size_kb = 0;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1717

context->res_ctx.pipe_ctx[i].unbounded_req = false;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1719

context->res_ctx.pipe_ctx[i].det_buffer_size_kb = get_det_buffer_size_kbytes(&context->bw_ctx.dml, pipes, pipe_cnt,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1721

context->res_ctx.pipe_ctx[i].unbounded_req = unbounded_req_enabled;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1726

if (context->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1727

context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1729

context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = 0;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1730

context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1732

context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes = get_surface_size_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1735

context->res_ctx.pipe_ctx[i].has_vactive_margin = true;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1737

context->res_ctx.pipe_ctx[i].has_vactive_margin = false;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1741

if (context->res_ctx.pipe_ctx[i].stream && context->res_ctx.pipe_ctx[i].plane_state &&

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1742

(context->res_ctx.pipe_ctx[i].top_pipe == NULL ||

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1743

context->res_ctx.pipe_ctx[i].plane_state != context->res_ctx.pipe_ctx[i].top_pipe->plane_state) &&

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1744

context->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1746

if (dc_state_get_pipe_subvp_type(context, &context->res_ctx.pipe_ctx[i]) != SUBVP_PHANTOM) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1747

context->bw_ctx.bw.dcn.mall_ss_size_bytes += context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1749

if (context->res_ctx.pipe_ctx[i].stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1751

context->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes += context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1755

context->bw_ctx.bw.dcn.mall_subvp_size_bytes += context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1759

if (context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1761

&context->res_ctx.pipe_ctx[i].stream->timing,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1762

&context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1790

if (context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1791

context->bw_ctx.bw.dcn.compbuf_size_kb -= context->res_ctx.pipe_ctx[i].det_buffer_size_kb;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1796

if (!context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1800

&context->res_ctx.pipe_ctx[i].dlg_regs, &context->res_ctx.pipe_ctx[i].ttu_regs, pipes,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1803

context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg_v2(&context->res_ctx.pipe_ctx[i].rq_regs,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1809

static struct pipe_ctx *dcn32_find_split_pipe(

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1814

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1817

if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1818

pipe = &context->res_ctx.pipe_ctx[old_index];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1824

if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1825

&& dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1826

if (context->res_ctx.pipe_ctx[i].stream == NULL) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1827

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1841

if (context->res_ctx.pipe_ctx[i].stream == NULL) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1842

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1854

struct pipe_ctx *pri_pipe,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1855

struct pipe_ctx *sec_pipe,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1959

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2012

struct pipe_ctx *top_pipe = pipe->top_pipe;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2013

struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2033

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2034

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2035

struct pipe_ctx *hsplit_pipe = NULL;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2076

struct pipe_ctx *pipe_4to1;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2119

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2128

struct pipe_ctx *otg_master = resource_get_otg_master_for_stream(&context->res_ctx,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2220

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2221

struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2596

if (!context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3391

bool dcn32_allow_subvp_with_active_margin(struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

343

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3433

bool dcn32_allow_subvp_high_refresh_rate(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3447

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3449

if (!pipe_ctx->stream)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3451

refresh_rate = (pipe_ctx->stream->timing.pix_clk_100hz * 100 +

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3452

pipe_ctx->stream->timing.v_total * pipe_ctx->stream->timing.h_total - 1)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3453

/ (double)(pipe_ctx->stream->timing.v_total * pipe_ctx->stream->timing.h_total);

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3529

const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3568

const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

468

struct pipe_ctx *ref_pipe,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

475

struct pipe_ctx *pipe;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

488

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

565

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

610

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

644

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

687

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

728

struct pipe_ctx *subvp_pipes[2] = {0};

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

737

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

801

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

802

struct pipe_ctx *drr_pipe = NULL;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

819

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

836

drr_pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

900

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

901

struct pipe_ctx *subvp_pipe = NULL;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

925

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

947

vblank_timing = &context->res_ctx.pipe_ctx[vblank_index].stream->timing;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

995

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

41

struct pipe_ctx *ref_pipe,

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

444

struct pipe_ctx *pipe = 0;

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

458

if (!res_ctx->pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

461

pipe = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

557

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

587

if (context->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

477

struct pipe_ctx *pipe = 0;

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

491

if (!res_ctx->pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

494

pipe = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

590

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

617

if (context->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

102

timing->h_total = stream->timing.h_total + pipe_ctx->dsc_padding_params.dsc_htotal_padding;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

109

timing->h_blank_end = hblank_start - stream->timing.h_addressable - pipe_ctx->dsc_padding_params.dsc_hactive_padding

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

128

if (pipe_ctx->dsc_padding_params.dsc_hactive_padding != 0) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

129

pix_clk_100hz = pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

186

struct dc_stream_state *stream, const struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

472

struct pipe_ctx *temp_pipe = &dml_ctx->v21.scratch.temp_pipe;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

474

memset(temp_pipe, 0, sizeof(struct pipe_ctx));

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

477

const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

754

populate_dml21_timing_config_from_stream_state(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].timing, context->streams[stream_index], &context->res_ctx.pipe_ctx[stream_index], dml_ctx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

755

populate_dml21_output_config_from_stream_state(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].output, context->streams[stream_index], &context->res_ctx.pipe_ctx[stream_index]);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

87

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

883

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

887

mcache_pipe_config->plane0.viewport_x_start = pipe_ctx->plane_res.scl_data.viewport.x;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

888

mcache_pipe_config->plane0.viewport_width = pipe_ctx->plane_res.scl_data.viewport.width;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

890

mcache_pipe_config->plane1.viewport_x_start = pipe_ctx->plane_res.scl_data.viewport_c.x;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

891

mcache_pipe_config->plane1.viewport_width = pipe_ctx->plane_res.scl_data.viewport_c.width;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

898

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

905

pipe_ctx->p_state_type = P_STATE_V_ACTIVE;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

910

pipe_ctx->p_state_type = P_STATE_V_BLANK_SUB_VP;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

912

pipe_ctx->p_state_type = P_STATE_V_BLANK;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

916

pipe_ctx->p_state_type = P_STATE_SUB_VP;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

920

pipe_ctx->p_state_type = P_STATE_DRR_SUB_VP;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

922

pipe_ctx->p_state_type = P_STATE_FPO;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

925

pipe_ctx->p_state_type = P_STATE_UNKNOWN;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

93

timing->h_active = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right + pipe_ctx->dsc_padding_params.dsc_hactive_padding;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

98

if (pipe_ctx->dsc_padding_params.dsc_hactive_padding != 0)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

99

timing->pixel_clock_khz = pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz / 10;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.h

13

struct pipe_ctx;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.h

25

void dml21_get_pipe_mcache_config(struct dc_state *context, struct pipe_ctx *pipe_ctx, struct dml2_per_plane_programming *pln_prog, struct dml2_pipe_configuration_descriptor *mcache_pipe_config);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.h

26

void dml21_set_dc_p_state_type(struct pipe_ctx *pipe_ctx, struct dml2_per_stream_programming *stream_programming, bool sub_vp_enabled);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

102

memset(dc_main_pipes, 0, sizeof(struct pipe_ctx *) * __DML2_WRAPPER_MAX_STREAMS_PLANES__);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

103

memset(dc_phantom_pipes, 0, sizeof(struct pipe_ctx *) * __DML2_WRAPPER_MAX_STREAMS_PLANES__);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

121

struct pipe_ctx *otg_master_pipe = dml_ctx->config.callbacks.get_otg_master_for_stream(&context->res_ctx, dc_main_stream);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

147

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

152

if (dml_ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

157

memcpy(&pipe_ctx->global_sync,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

165

struct pipe_ctx *dc_pipe)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

186

bool check_dp2p0_output_encoder(const struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

189

ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

190

return (pipe_ctx->stream_res.hpo_dp_stream_enc &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

191

pipe_ctx->link_res.hpo_dp_link_enc &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

192

dc_is_dp_signal(pipe_ctx->stream->signal));

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

201

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

203

if (pipe_ctx->stream && dc_state_get_paired_subvp_stream(context, pipe_ctx->stream) &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

204

dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_MAIN) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

212

void dml21_program_dc_pipe(struct dml2_context *dml_ctx, struct dc_state *context, struct pipe_ctx *pipe_ctx, struct dml2_per_plane_programming *pln_prog,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

217

dml21_pipe_populate_global_sync(dml_ctx, context, pipe_ctx, stream_prog);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

218

find_pipe_regs_idx(dml_ctx, pipe_ctx, &pipe_reg_index);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

220

if (dml_ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

221

memcpy(&pipe_ctx->hubp_regs, pln_prog->phantom_plane.pipe_regs[pipe_reg_index], sizeof(struct dml2_dchub_per_pipe_register_set));

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

222

pipe_ctx->unbounded_req = false;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

223

pipe_ctx->det_buffer_size_kb = 0;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

225

memcpy(&pipe_ctx->hubp_regs, pln_prog->pipe_regs[pipe_reg_index], sizeof(struct dml2_dchub_per_pipe_register_set));

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

226

pipe_ctx->unbounded_req = pln_prog->pipe_regs[pipe_reg_index]->rq_regs.unbounded_request_enabled;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

227

pipe_ctx->det_buffer_size_kb = pln_prog->pipe_regs[pipe_reg_index]->det_size * 64;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

230

pipe_ctx->plane_res.bw.dppclk_khz = pln_prog->min_clocks.dcn4x.dppclk_khz;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

231

if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipe_ctx->plane_res.bw.dppclk_khz)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

232

context->bw_ctx.bw.dcn.clk.dppclk_khz = pipe_ctx->plane_res.bw.dppclk_khz;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

234

dml21_populate_mall_allocation_size(context, dml_ctx, pln_prog, pipe_ctx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

236

bool sub_vp_enabled = is_sub_vp_enabled(pipe_ctx->stream->ctx->dc, context);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

238

dml21_set_dc_p_state_type(pipe_ctx, stream_prog, sub_vp_enabled);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

442

if (context->res_ctx.pipe_ctx[k].stream &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

443

context->res_ctx.pipe_ctx[k].stream->stream_id == stream->stream_id &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

444

context->res_ctx.pipe_ctx[k].plane_state == context->stream_status[i].plane_states[j]) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

479

if (context->res_ctx.pipe_ctx[k].stream &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

480

context->res_ctx.pipe_ctx[k].stream->stream_id == phantom_stream->stream_id &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

481

context->res_ctx.pipe_ctx[k].plane_state == phantom_status->plane_states[j]) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

73

struct pipe_ctx *pipe, unsigned int *pipe_regs_idx)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

75

struct pipe_ctx *opp_head = dml_ctx->config.callbacks.get_opp_head(pipe);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

87

struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__],

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

88

struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__],

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h

11

struct pipe_ctx;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h

23

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h

28

struct pipe_ctx *dc_pipe);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h

29

bool check_dp2p0_output_encoder(const struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h

32

struct pipe_ctx *pipe, unsigned int *pipe_regs_idx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h

36

struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__],

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h

37

struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__],

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h

41

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c

311

struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c

312

struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__] = {0};

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c

93

struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c

94

struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__] = {0};

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

109

static struct pipe_ctx *find_master_pipe_of_stream(struct dml2_context *ctx, struct dc_state *state, unsigned int stream_id)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

114

if (state->res_ctx.pipe_ctx[i].stream && state->res_ctx.pipe_ctx[i].stream->stream_id == stream_id) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

115

if (!state->res_ctx.pipe_ctx[i].prev_odm_pipe && !state->res_ctx.pipe_ctx[i].top_pipe)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1158

struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

116

return &state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

123

static struct pipe_ctx *find_master_pipe_of_plane(struct dml2_context *ctx,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

130

if (state->res_ctx.pipe_ctx[i].plane_state && get_plane_id(ctx, state, state->res_ctx.pipe_ctx[i].plane_state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

131

state->res_ctx.pipe_ctx[i].stream->stream_id,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

132

ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[state->res_ctx.pipe_ctx[i].pipe_idx], &plane_id_assigned_to_pipe)) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

134

return &state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

149

struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

160

struct pipe_ctx *mpc_pipe = pipe;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

227

static bool is_plane_using_pipe(const struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

235

static bool is_pipe_free(const struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

267

if (existing_state->res_ctx.pipe_ctx[i].stream && existing_state->res_ctx.pipe_ctx[i].stream->stream_id == stream_id) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

268

struct pipe_ctx *head_pipe =

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

269

resource_is_pipe_type(&existing_state->res_ctx.pipe_ctx[i], DPP_PIPE) ?

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

270

resource_get_primary_dpp_pipe(&existing_state->res_ctx.pipe_ctx[i]) :

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

276

if (existing_state->res_ctx.pipe_ctx[i].plane_res.hubp &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

277

existing_state->res_ctx.pipe_ctx[i].plane_res.hubp->opp_id != i &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

278

(existing_state->res_ctx.pipe_ctx[i].prev_odm_pipe ||

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

279

existing_state->res_ctx.pipe_ctx[i].next_odm_pipe))

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

308

struct pipe_ctx *head_pipe =

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

309

resource_is_pipe_type(&existing_state->res_ctx.pipe_ctx[i], DPP_PIPE) ?

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

310

resource_get_primary_dpp_pipe(&existing_state->res_ctx.pipe_ctx[i]) :

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

316

if ((existing_state->res_ctx.pipe_ctx[i].plane_res.hubp &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

317

existing_state->res_ctx.pipe_ctx[i].plane_res.hubp->opp_id != i) ||

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

318

existing_state->res_ctx.pipe_ctx[i].stream_res.tg)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

348

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

365

pipe = &state->res_ctx.pipe_ctx[preferred_pipe_candidates[i]];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

381

pipe = &state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

392

pipe = &state->res_ctx.pipe_ctx[last_resort_pipe_candidates[i]];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

414

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

431

pipe = &state->res_ctx.pipe_ctx[preferred_pipe_candidates[i]];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

447

pipe = &state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

458

pipe = &state->res_ctx.pipe_ctx[last_resort_pipe_candidates[i]];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

48

struct pipe_ctx *next_higher_pipe_for_odm_slice[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

52

struct pipe_ctx *prev_odm_pipe;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

538

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

546

pipe = &state->res_ctx.pipe_ctx[scratch->pipe_pool.pipes_assigned_to_plane[odm_slice_index][i]];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

557

static struct pipe_ctx *add_plane_to_blend_tree(struct dml2_context *ctx,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

562

struct pipe_ctx *top_pipe)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

568

top_pipe->bottom_pipe = &state->res_ctx.pipe_ctx[pipe_pool->pipes_assigned_to_plane[odm_slice][i]];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

572

state->res_ctx.pipe_ctx[pipe_pool->pipes_assigned_to_plane[odm_slice][i]].top_pipe = top_pipe;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

573

state->res_ctx.pipe_ctx[pipe_pool->pipes_assigned_to_plane[odm_slice][i]].bottom_pipe = NULL;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

575

top_pipe = &state->res_ctx.pipe_ctx[pipe_pool->pipes_assigned_to_plane[odm_slice][i]];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

589

struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

603

static struct pipe_ctx *assign_pipes_to_stream(struct dml2_context *ctx, struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

609

struct pipe_ctx *master_pipe;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

637

static struct pipe_ctx *assign_pipes_to_plane(struct dml2_context *ctx, struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

646

struct pipe_ctx *master_pipe = NULL;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

695

static void free_pipe(struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

697

memset(pipe, 0, sizeof(struct pipe_ctx));

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

707

if (state->res_ctx.pipe_ctx[i].plane_state == plane &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

708

state->res_ctx.pipe_ctx[i].stream->stream_id == stream_id &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

710

ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[state->res_ctx.pipe_ctx[i].pipe_idx] == plane_index) &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

711

!is_pipe_used(pool, state->res_ctx.pipe_ctx[i].pipe_idx)) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

712

free_pipe(&state->res_ctx.pipe_ctx[i]);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

719

struct pipe_ctx *pipe;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

723

pipe = &state->res_ctx.pipe_ctx[pipe_pool->pipes_assigned_to_plane[odm_slice][0]];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

738

struct pipe_ctx *master_pipe = NULL;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

750

master_pipe, &state->res_ctx.pipe_ctx[scratch->pipe_pool.pipes_assigned_to_plane[odm_slice_index][0]], true);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

759

struct pipe_ctx *master_pipe = NULL;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

784

master_pipe, &state->res_ctx.pipe_ctx[scratch->pipe_pool.pipes_assigned_to_plane[odm_slice_index][i]], true);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

899

struct pipe_ctx *otg_master = ctx->config.callbacks.get_otg_master_for_stream(&state->res_ctx, stream);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

911

struct pipe_ctx *dpp_pipes[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_internal_types.h

122

struct pipe_ctx temp_pipe;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

108

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

130

struct pipe_ctx *top_pipe = pipe->top_pipe;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

131

struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

152

const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

193

struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

239

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

264

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

317

struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

360

struct pipe_ctx *subvp_pipes[2];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

369

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

436

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

450

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

51

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

510

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

511

struct pipe_ctx *subvp_pipe = NULL;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

535

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

553

if (found && context->res_ctx.pipe_ctx[vblank_index].stream->ignore_msa_timing_param) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

555

schedulable = dml2_svp_drr_schedulable(ctx, context, &context->res_ctx.pipe_ctx[vblank_index].stream->timing);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

560

vblank_timing = &context->res_ctx.pipe_ctx[vblank_index].stream->timing;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

611

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

652

struct pipe_ctx *ref_pipe,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

660

struct pipe_ctx *pipe;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

666

pipe = &state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

716

struct pipe_ctx *ref_pipe = &state->res_ctx.pipe_ctx[dc_pipe_idx];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

742

struct pipe_ctx *curr_pipe = &state->res_ctx.pipe_ctx[dc_pipe_idx];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

795

struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

848

struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

892

struct pipe_ctx *pipe_ctx = &state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

894

if (!pipe_ctx->plane_state || !pipe_ctx->stream)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

897

ctx->config.svp_pstate.callbacks.build_scaling_params(pipe_ctx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

901

dml_pipe_idx = dml2_helper_find_dml_pipe_idx_by_stream_id(ctx, state->res_ctx.pipe_ctx[dc_pipe_idx].stream->stream_id);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1208

struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1273

struct pipe_ctx *current_pipe_context;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1282

current_pipe_context = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1298

struct pipe_ctx *current_pipe_context;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1323

if (context->streams[i] == context->res_ctx.pipe_ctx[k].stream) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1324

current_pipe_context = &context->res_ctx.pipe_ctx[k];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1432

struct pipe_ctx *out)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

783

const struct dc_stream_state *in, const struct pipe_ctx *pipe, struct dml2_context *dml2)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

985

struct pipe_ctx *temp_pipe = &context->res_ctx.temp_pipe;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

987

memset(temp_pipe, 0, sizeof(struct pipe_ctx));

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

990

const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.h

38

void dml2_update_pipe_ctx_dchub_regs(struct _vcs_dpi_dml_display_rq_regs_st *rq_regs, struct _vcs_dpi_dml_display_dlg_regs_st *disp_dlg_regs, struct _vcs_dpi_dml_display_ttu_regs_st *disp_ttu_regs, struct pipe_ctx *out);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.h

39

bool is_dp2p0_output_encoder(const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

156

bool is_dp2p0_output_encoder(const struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

158

if (pipe_ctx == NULL || pipe_ctx->stream == NULL)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

162

ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

164

return (pipe_ctx->stream_res.hpo_dp_stream_enc &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

165

pipe_ctx->link_res.hpo_dp_link_enc &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

166

dc_is_dp_signal(pipe_ctx->stream->signal));

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

174

if (!context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

176

if (is_dp2p0_output_encoder(&context->res_ctx.pipe_ctx[i]))

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

240

static void populate_pipe_ctx_dlg_params_from_dml(struct pipe_ctx *pipe_ctx, struct display_mode_lib_st *mode_lib, dml_uint_t pipe_idx)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

243

struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

247

hblank_start = pipe_ctx->stream->timing.h_total - pipe_ctx->stream->timing.h_front_porch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

248

vblank_start = pipe_ctx->stream->timing.v_total - pipe_ctx->stream->timing.v_front_porch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

253

pipe_ctx->pipe_dlg_param.vstartup_start = dml_get_vstartup_calculated(mode_lib, pipe_idx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

254

pipe_ctx->pipe_dlg_param.vupdate_offset = dml_get_vupdate_offset(mode_lib, pipe_idx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

255

pipe_ctx->pipe_dlg_param.vupdate_width = dml_get_vupdate_width(mode_lib, pipe_idx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

256

pipe_ctx->pipe_dlg_param.vready_offset = dml_get_vready_offset(mode_lib, pipe_idx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

258

pipe_ctx->pipe_dlg_param.otg_inst = pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

260

pipe_ctx->pipe_dlg_param.hactive = hactive;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

261

pipe_ctx->pipe_dlg_param.vactive = vactive;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

262

pipe_ctx->pipe_dlg_param.htotal = pipe_ctx->stream->timing.h_total;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

263

pipe_ctx->pipe_dlg_param.vtotal = pipe_ctx->stream->timing.v_total;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

264

pipe_ctx->pipe_dlg_param.hblank_end = hblank_end;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

265

pipe_ctx->pipe_dlg_param.vblank_end = vblank_end;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

266

pipe_ctx->pipe_dlg_param.hblank_start = hblank_start;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

267

pipe_ctx->pipe_dlg_param.vblank_start = vblank_start;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

268

pipe_ctx->pipe_dlg_param.vfront_porch = pipe_ctx->stream->timing.v_front_porch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

269

pipe_ctx->pipe_dlg_param.pixel_rate_mhz = pipe_ctx->stream->timing.pix_clk_100hz / 10000.00;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

270

pipe_ctx->pipe_dlg_param.refresh_rate = ((timing->pix_clk_100hz * 100) / timing->h_total) / timing->v_total;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

271

pipe_ctx->pipe_dlg_param.vtotal_max = pipe_ctx->stream->adjust.v_total_max;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

272

pipe_ctx->pipe_dlg_param.vtotal_min = pipe_ctx->stream->adjust.v_total_min;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

273

pipe_ctx->pipe_dlg_param.recout_height = pipe_ctx->plane_res.scl_data.recout.height;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

274

pipe_ctx->pipe_dlg_param.recout_width = pipe_ctx->plane_res.scl_data.recout.width;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

275

pipe_ctx->pipe_dlg_param.full_recout_height = pipe_ctx->plane_res.scl_data.recout.height;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

276

pipe_ctx->pipe_dlg_param.full_recout_width = pipe_ctx->plane_res.scl_data.recout.width;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

299

if (!context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

305

if (get_plane_id(in_ctx, context, context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

306

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream->stream_id,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

307

in_ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[context->res_ctx.pipe_ctx[dc_pipe_ctx_index].pipe_idx], &plane_id)) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

310

dml_pipe_idx = dml2_helper_find_dml_pipe_idx_by_stream_id(in_ctx, context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream->stream_id);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

316

ASSERT(in_ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[dml_pipe_idx] == context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream->stream_id);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

321

populate_pipe_ctx_dlg_params_from_dml(&context->res_ctx.pipe_ctx[dc_pipe_ctx_index], &context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

323

pipe_mall_type = dc_state_get_pipe_subvp_type(context, &context->res_ctx.pipe_ctx[dc_pipe_ctx_index]);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

326

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].det_buffer_size_kb = 0;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

327

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].unbounded_req = false;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

329

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].det_buffer_size_kb = dml_get_det_buffer_size_kbytes(&context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

331

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].unbounded_req = in_ctx->v20.dml_core_ctx.ms.UnboundedRequestEnabledThisState;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

334

context->bw_ctx.bw.dcn.compbuf_size_kb -= context->res_ctx.pipe_ctx[dc_pipe_ctx_index].det_buffer_size_kb;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

335

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz = dml_get_dppclk_calculated(&context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx) * 1000;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

336

if (context->bw_ctx.bw.dcn.clk.dppclk_khz < context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

337

context->bw_ctx.bw.dcn.clk.dppclk_khz = context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

341

dml2_update_pipe_ctx_dchub_regs(&s->rq_regs, &s->disp_dlg_regs, &s->disp_ttu_regs, &out_new_hw_state->pipe_ctx[dc_pipe_ctx_index]);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

343

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].surface_size_in_mall_bytes = dml_get_surface_size_for_mall(&context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

347

if (context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream && context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_state &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

348

(context->res_ctx.pipe_ctx[dc_pipe_ctx_index].top_pipe == NULL ||

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

349

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_state != context->res_ctx.pipe_ctx[dc_pipe_ctx_index].top_pipe->plane_state) &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

350

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].prev_odm_pipe == NULL) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

353

context->bw_ctx.bw.dcn.mall_ss_size_bytes += context->res_ctx.pipe_ctx[dc_pipe_ctx_index].surface_size_in_mall_bytes;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

356

context->bw_ctx.bw.dcn.mall_subvp_size_bytes += context->res_ctx.pipe_ctx[dc_pipe_ctx_index].surface_size_in_mall_bytes;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

440

if (context->res_ctx.pipe_ctx[i].stream->phy_pix_clk != 0) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

443

(1000000 << 6) / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

520

if (!display_state->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

522

if (get_plane_id(in_ctx, display_state, display_state->res_ctx.pipe_ctx[i].plane_state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

523

display_state->res_ctx.pipe_ctx[i].stream->stream_id,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

524

in_ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[display_state->res_ctx.pipe_ctx[i].pipe_idx], &plane_id))

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

527

dml_pipe_idx = dml2_helper_find_dml_pipe_idx_by_stream_id(in_ctx, display_state->res_ctx.pipe_ctx[i].stream->stream_id);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

100

struct pipe_ctx *opp_heads[MAX_PIPES]);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

103

struct pipe_ctx *dpp_pipes[MAX_PIPES]);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

116

bool (*build_scaling_params)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

142

enum mall_stream_type (*get_pipe_subvp_type)(const struct dc_state *state, const struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

37

struct pipe_ctx;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

74

bool (*build_scaling_params)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

75

void (*build_test_pattern_params)(struct resource_context *res_ctx, struct pipe_ctx *otg_master);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

77

bool (*acquire_secondary_pipe_for_mpc_odm)(const struct dc *dc, struct dc_state *state, struct pipe_ctx *pri_pipe, struct pipe_ctx *sec_pipe, bool odm);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

90

int (*get_odm_slice_index)(const struct pipe_ctx *opp_head);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

91

int (*get_odm_slice_count)(const struct pipe_ctx *opp_head);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

92

int (*get_mpc_slice_index)(const struct pipe_ctx *dpp_pipe);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

93

int (*get_mpc_slice_count)(const struct pipe_ctx *dpp_pipe);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

94

struct pipe_ctx *(*get_opp_head)(const struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

95

struct pipe_ctx *(*get_otg_master_for_stream)(

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h

98

int (*get_opp_heads_for_otg_master)(const struct pipe_ctx *otg_master,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

180

struct pipe_ctx *pipe = &display_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

288

struct pipe_ctx *pipe = &display_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c

48

struct pipe_ctx *pipe,

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c

90

struct pipe_ctx *pipe,

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1276

struct pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1283

struct pipe_ctx *pipe,

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1291

struct pipe_ctx *pipe,

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

154

void dce100_reset_surface_dcc_and_tiling(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

158

struct mem_input *mi = pipe_ctx->plane_res.mi;

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.h

49

void dce100_reset_surface_dcc_and_tiling(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1059

void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1067

if (!pipe_ctx->stream)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1070

if (dc_is_rgb_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1073

dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1075

link_hwss = get_link_hwss(pipe_ctx->stream->link, &pipe_ctx->link_res);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1077

if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1080

if (pipe_ctx->stream_res.audio) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1083

if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1091

pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1093

link_hwss->enable_audio_packet(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1095

if (pipe_ctx->stream_res.audio)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1096

pipe_ctx->stream_res.audio->enabled = true;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1100

void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1106

if (!pipe_ctx || !pipe_ctx->stream)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1109

if (dc_is_rgb_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1112

dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1114

link_hwss = get_link_hwss(pipe_ctx->stream->link, &pipe_ctx->link_res);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1116

if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1119

link_hwss->disable_audio_packet(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1121

if (pipe_ctx->stream_res.audio) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1122

pipe_ctx->stream_res.audio->enabled = false;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1136

void dce110_disable_stream(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1138

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1140

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1141

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1143

struct timing_generator *tg = pipe_ctx->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1146

struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1147

struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1152

if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1153

pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1154

pipe_ctx->stream_res.stream_enc);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1155

pipe_ctx->stream_res.stream_enc->funcs->hdmi_reset_stream_attribute(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1156

pipe_ctx->stream_res.stream_enc);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1159

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1160

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->stop_dp_info_packets(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1161

pipe_ctx->stream_res.hpo_dp_stream_enc);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1162

} else if (dc_is_dp_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1163

pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1164

pipe_ctx->stream_res.stream_enc);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1166

dc->hwss.disable_audio_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1168

link_hwss->reset_stream_encoder(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1170

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) && dccg) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1172

dto_params.timing = &pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1173

dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1188

void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1192

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1197

params.timing = pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1200

if (dc_is_dp_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1201

pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1208

void dce110_blank_stream(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1210

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1220

link->dc->hwss.set_abm_immediate_disable(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1223

if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1225

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_blank(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1226

pipe_ctx->stream_res.hpo_dp_stream_enc);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1227

} else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1228

pipe_ctx->stream_res.stream_enc->funcs->dp_blank(link, pipe_ctx->stream_res.stream_enc);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1230

if (!dc_is_embedded_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1239

if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1254

void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1256

if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1257

pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1281

const struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1284

const struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1289

&pipe_ctx->link_config.dp_link_settings);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1291

dp_link_info->lane_count = pipe_ctx->link_config.dp_link_settings.lane_count;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1292

dp_link_info->link_rate = pipe_ctx->link_config.dp_link_settings.link_rate;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1295

&pipe_ctx->link_config.dp_link_settings));

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1316

struct dc_crtc_timing *crtc_timing = &pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1374

const struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1377

const struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1378

audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1380

audio_output->signal = pipe_ctx->stream->signal;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1414

pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1417

pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1429

if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) &&

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1432

if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1436

pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/2;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1442

(pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1443

pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1451

pipe_ctx->stream_res.tg->inst + 1);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1457

pipe_ctx->pll_settings.ss_percentage;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1459

if (dc_is_dp_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1460

populate_audio_dp_link_info(pipe_ctx, &audio_output->dp_link_info);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1465

const struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1470

if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1474

get_surface_visual_confirm_color(pipe_ctx, &color);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1477

pipe_ctx->stream->output_color_space,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1480

pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1481

pipe_ctx->plane_res.xfm,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1482

pipe_ctx->plane_res.scl_data.lb_params.depth,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1483

&pipe_ctx->stream->bit_depth_params);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1485

if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1491

if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1494

pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1495

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1499

pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1500

&pipe_ctx->plane_res.scl_data);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1504

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1508

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1509

struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1510

pipe_ctx[pipe_ctx->pipe_idx];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1518

pipe_ctx->stream_res.tg->funcs->set_blank_color(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1519

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1526

pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1528

if (false == pipe_ctx->clock_source->funcs->program_pix_clk(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1529

pipe_ctx->clock_source,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1530

&pipe_ctx->stream_res.pix_clk_params,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1531

dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings),

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1532

&pipe_ctx->pll_settings)) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1545

pipe_ctx->stream_res.tg->funcs->program_timing(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1546

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1553

pipe_ctx->stream->signal,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1558

if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1559

pipe_ctx->stream_res.tg)) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1569

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1573

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1577

struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1580

link, &pipe_ctx->link_res);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1584

hws->funcs.disable_stream_gating(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1587

if (pipe_ctx->stream_res.audio != NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1590

build_audio_output(context, pipe_ctx, &audio_output);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1592

link_hwss->setup_audio_output(pipe_ctx, &audio_output,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1593

pipe_ctx->stream_res.audio->inst);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1595

pipe_ctx->stream_res.audio->funcs->az_configure(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1596

pipe_ctx->stream_res.audio,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1597

pipe_ctx->stream->signal,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1599

&pipe_ctx->stream->audio_info,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1603

if (pipe_ctx->stream_res.audio->funcs->az_disable_hbr_audio &&

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1604

dc->link_srv->dp_is_128b_132b_signal(pipe_ctx))

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1605

pipe_ctx->stream_res.audio->funcs->az_disable_hbr_audio(pipe_ctx->stream_res.audio);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1609

if (!pipe_ctx->stream->apply_seamless_boot_optimization && dc->config.use_pipe_ctx_sync_logic)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1610

check_syncd_pipes_for_disabled_master_pipe(dc, context, pipe_ctx->pipe_idx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1612

pipe_ctx->stream_res.opp->funcs->opp_program_fmt(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1613

pipe_ctx->stream_res.opp,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1617

pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1618

pipe_ctx->stream_res.opp,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1642

if (!(hws->wa.dp_hpo_and_otg_sequence && dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)))

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1645

if (!pipe_ctx->stream->apply_seamless_boot_optimization)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1646

hws->funcs.enable_stream_timing(pipe_ctx, context, dc);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1649

hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1653

set_drr_and_clear_adjust_pending(pipe_ctx, stream, &params);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1662

if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1663

pipe_ctx->stream_res.tg->funcs->set_static_screen_control(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1664

pipe_ctx->stream_res.tg, event_triggers, 2);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1666

if (!dc_is_virtual_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1667

pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1668

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1669

pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1671

if (dc_is_dp_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1678

if (pipe_ctx->stream->timing.flags.DSC) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1679

if ((pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1682

(dc_is_dp_signal(pipe_ctx->stream->signal) ||

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1683

dc_is_virtual_signal(pipe_ctx->stream->signal)))

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1684

dc->link_srv->set_dsc_enable(pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1688

dc->link_srv->set_dpms_on(context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1695

if (hws->wa.dp_hpo_and_otg_sequence && dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1696

if (!pipe_ctx->stream->apply_seamless_boot_optimization)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1697

hws->funcs.enable_stream_timing(pipe_ctx, context, dc);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1700

pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1706

if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1707

pipe_ctx->stream->link->psr_settings.psr_feature_enabled = false;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1708

pipe_ctx->stream->link->replay_settings.replay_feature_enabled = false;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1801

dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1803

&dc->current_state->res_ctx.pipe_ctx[i]);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1902

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1950

pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, edp_stream);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1951

if (pipe_ctx &&

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1953

hws->funcs.is_dp_dig_pixel_rate_div_policy(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1957

pipe_ctx->stream_res.tg->inst,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1958

&pipe_ctx->pixel_rate_divider.div_factor1,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1959

&pipe_ctx->pixel_rate_divider.div_factor2);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1963

pipe_ctx->stream_res.pix_clk_params.dio_se_pix_per_cycle = 1;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2049

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2052

if (pipe_ctx->stream == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2056

dc->bw_vbios->blackout_duration, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2057

pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2058

pipe_ctx->plane_res.mi,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2066

pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2067

pipe_ctx->plane_res.mi,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2090

if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2093

res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2094

res_ctx->pipe_ctx[i].plane_res.mi,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2102

res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2103

res_ctx->pipe_ctx[i].plane_res.mi,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2116

static void set_drr(struct pipe_ctx **pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2138

struct timing_generator *tg = pipe_ctx[i]->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2141

set_drr_and_clear_adjust_pending(pipe_ctx[i], pipe_ctx[i]->stream, &params);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2150

static void get_position(struct pipe_ctx **pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2159

pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2162

static void set_static_screen_control(struct pipe_ctx **pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2178

struct dc *dc = pipe_ctx[0]->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2185

pipe_ctx[i]->stream_res.tg->funcs->

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2186

set_static_screen_control(pipe_ctx[i]->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2198

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2214

if (res_ctx->pipe_ctx[i].stream) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2216

pipe_ctx = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2219

if (pipe_ctx->pipe_idx != underlay_idx) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2229

if (!pipe_ctx->stream->link)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2233

if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2237

if (pipe_ctx->stream->link->psr_settings.psr_feature_enabled)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2241

if (pipe_ctx->stream->link->replay_settings.replay_feature_enabled)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2245

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2249

if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2268

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2270

params.source_view_width = pipe_ctx->stream->timing.h_addressable;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2271

params.source_view_height = pipe_ctx->stream->timing.v_addressable;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2272

params.inst = pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2291

struct pipe_ctx *pipe_ctx_old =

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2292

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2293

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2304

if (!pipe_ctx->stream ||

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2305

pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2311

if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2380

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2382

if (pipe_ctx->stream == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2385

if (pipe_ctx->top_pipe)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2387

if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2389

if (pipe_ctx->stream_res.audio != NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2392

build_audio_output(context, pipe_ctx, &audio_output);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2400

pipe_ctx->stream_res.audio->funcs->wall_dto_setup(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2401

pipe_ctx->stream_res.audio,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2402

pipe_ctx->stream->signal,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2406

pipe_ctx->stream_res.audio->funcs->wall_dto_setup(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2407

pipe_ctx->stream_res.audio,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2408

pipe_ctx->stream->signal,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2418

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2420

if (pipe_ctx->stream == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2423

if (pipe_ctx->top_pipe)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2426

if (!dc_is_dp_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2429

if (pipe_ctx->stream_res.audio != NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2432

build_audio_output(context, pipe_ctx, &audio_output);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2434

pipe_ctx->stream_res.audio->funcs->wall_dto_setup(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2435

pipe_ctx->stream_res.audio,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2436

pipe_ctx->stream->signal,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2473

struct pipe_ctx *pipe_ctx_old =

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2474

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2475

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2477

if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2480

if (pipe_ctx->stream == pipe_ctx_old->stream) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2481

if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2483

pipe_ctx->clock_source, i);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2502

struct pipe_ctx *pipe_ctx_old =

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2503

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2504

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2506

if (pipe_ctx->stream == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2509

if (pipe_ctx->stream == pipe_ctx_old->stream &&

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2510

pipe_ctx->stream->link->link_state_valid) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2514

if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2517

if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2521

pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2545

static void set_default_colors(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2550

default_adjust.in_color_space = pipe_ctx->plane_state->color_space;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2551

default_adjust.out_color_space = pipe_ctx->stream->output_color_space;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2553

default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2557

pipe_ctx->stream->timing.display_color_depth;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2560

default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2562

pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2563

pipe_ctx->plane_res.xfm, &default_adjust);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2587

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2592

if (pipe_ctx->bottom_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2595

ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2597

if (pipe_ctx->bottom_pipe->plane_state->visible) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2598

if (pipe_ctx->plane_state->visible)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2603

} else if (!pipe_ctx->plane_state->visible)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2606

} else if (!pipe_ctx->plane_state->visible)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2609

dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2610

pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2614

static void program_gamut_remap(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2622

if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2627

pipe_ctx->stream->gamut_remap_matrix.matrix[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2630

pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2633

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2635

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2640

pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2641

pipe_ctx->plane_res.mi,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2648

static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2650

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2656

pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2657

pipe_ctx->plane_res.mi);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2660

pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2662

plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2663

if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2664

pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2666

!pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2720

struct pipe_ctx *grouped_pipes[])

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2766

struct pipe_ctx *grouped_pipes[])

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

284

dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

287

struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2911

struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2913

struct mem_input *mi = pipe_ctx->plane_res.mi;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2914

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2927

set_default_colors(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2928

if (pipe_ctx->stream->csc_color_matrix.enable_adjustment

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2931

pipe_ctx->stream->output_color_space;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2935

pipe_ctx->stream->csc_color_matrix.matrix[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2937

pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2938

(pipe_ctx->plane_res.xfm, &tbl_entry);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2941

if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2946

pipe_ctx->stream->gamut_remap_matrix.matrix[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2949

pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2951

pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2953

program_scaler(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2964

mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2968

pipe_ctx->plane_res.mi,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2974

if (pipe_ctx->plane_state->update_flags.bits.full_update ||

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2975

pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2976

pipe_ctx->plane_state->update_flags.bits.gamma_change)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2977

hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2979

if (pipe_ctx->plane_state->update_flags.bits.full_update)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2980

hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2988

pipe_ctx->pipe_idx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2989

(void *) pipe_ctx->plane_state,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2990

pipe_ctx->plane_state->address.grph.addr.high_part,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2991

pipe_ctx->plane_state->address.grph.addr.low_part,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2992

pipe_ctx->plane_state->src_rect.x,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2993

pipe_ctx->plane_state->src_rect.y,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2994

pipe_ctx->plane_state->src_rect.width,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2995

pipe_ctx->plane_state->src_rect.height,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2996

pipe_ctx->plane_state->dst_rect.x,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2997

pipe_ctx->plane_state->dst_rect.y,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2998

pipe_ctx->plane_state->dst_rect.width,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2999

pipe_ctx->plane_state->dst_rect.height,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3000

pipe_ctx->plane_state->clip_rect.x,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3001

pipe_ctx->plane_state->clip_rect.y,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3002

pipe_ctx->plane_state->clip_rect.width,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3003

pipe_ctx->plane_state->clip_rect.height);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3009

pipe_ctx->pipe_idx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3010

pipe_ctx->plane_res.scl_data.viewport.width,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3011

pipe_ctx->plane_res.scl_data.viewport.height,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3012

pipe_ctx->plane_res.scl_data.viewport.x,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3013

pipe_ctx->plane_res.scl_data.viewport.y,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3014

pipe_ctx->plane_res.scl_data.recout.width,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3015

pipe_ctx->plane_res.scl_data.recout.height,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3016

pipe_ctx->plane_res.scl_data.recout.x,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3017

pipe_ctx->plane_res.scl_data.recout.y);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3035

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3037

if (pipe_ctx->stream != stream)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3041

pipe_ctx->plane_res.mi->funcs->allocate_mem_input(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3042

pipe_ctx->plane_res.mi,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3043

pipe_ctx->stream->timing.h_total,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3044

pipe_ctx->stream->timing.v_total,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3045

pipe_ctx->stream->timing.pix_clk_100hz / 10,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3048

dce110_program_front_end_for_pipe(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3050

dc->hwss.update_plane_addr(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3052

program_surface_visibility(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3066

static void dce110_power_down_fe(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3069

int fe_idx = pipe_ctx->plane_res.mi ?

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3070

pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3073

if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3086

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3092

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3100

if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3101

enum dc_color_space color_space = pipe_ctx->stream->output_color_space;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3104

tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i];

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3108

pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3109

pipe_ctx->plane_res.xfm, &tbl_entry);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3113

static void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3115

struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3116

struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3117

struct mem_input *mi = pipe_ctx->plane_res.mi;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3119

.pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3120

.ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.xtalin_clock_inKhz,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3121

.viewport = pipe_ctx->plane_res.scl_data.viewport,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3122

.h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3123

.v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3124

.rotation = pipe_ctx->plane_state->rotation,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3125

.mirror = pipe_ctx->plane_state->horizontal_mirror

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3141

pos_cpy.x += pipe_ctx->plane_state->src_rect.x;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3142

pos_cpy.y += pipe_ctx->plane_state->src_rect.y;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3145

if (pipe_ctx->plane_state->address.type

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3149

if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3158

static void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3160

struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3162

if (pipe_ctx->plane_res.ipp &&

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3163

pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3164

pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3165

pipe_ctx->plane_res.ipp, attributes);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3167

if (pipe_ctx->plane_res.mi &&

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3168

pipe_ctx->plane_res.mi->funcs->set_cursor_attributes)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3169

pipe_ctx->plane_res.mi->funcs->set_cursor_attributes(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3170

pipe_ctx->plane_res.mi, attributes);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3172

if (pipe_ctx->plane_res.xfm &&

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3173

pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3174

pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3175

pipe_ctx->plane_res.xfm, attributes);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3178

bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3183

struct dc_link *link = pipe_ctx->stream->link;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3185

struct abm *abm = pipe_ctx->stream_res.abm;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3192

uint32_t controller_id = pipe_ctx->stream_res.tg->inst + 1;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3213

void dce110_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3215

struct abm *abm = pipe_ctx->stream_res.abm;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3216

struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3220

pipe_ctx->stream->link->panel_cntl->inst);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3226

void dce110_set_pipe(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3228

struct abm *abm = pipe_ctx->stream_res.abm;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3229

struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3230

uint32_t otg_inst = pipe_ctx->stream_res.tg->inst + 1;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3282

struct pipe_ctx *pipes =

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3283

link->dc->current_state->res_ctx.pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

607

dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

610

struct transform *xfm = pipe_ctx->plane_res.xfm;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

631

void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

636

ASSERT(pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

638

if (pipe_ctx->stream_res.stream_enc == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

641

is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

642

is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

648

pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

649

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

650

&pipe_ctx->stream_res.encoder_info_frame);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

652

if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

653

pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

654

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

655

&pipe_ctx->stream_res.encoder_info_frame);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

657

pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

658

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

659

&pipe_ctx->stream_res.encoder_info_frame);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

663

void dce110_enable_stream(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

666

pipe_ctx->stream->link->cur_link_settings.lane_count;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

667

struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

668

struct dc_link *link = pipe_ctx->stream->link;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

670

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

673

struct timing_generator *tg = pipe_ctx->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

675

link_hwss->setup_stream_encoder(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

677

dc->hwss.update_info_frame(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

115

const struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

119

const struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

43

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

47

void dce110_enable_stream(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

49

void dce110_disable_stream(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

51

void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

54

void dce110_blank_stream(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

56

void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

57

void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

59

void dce110_update_info_frame(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

61

void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

90

bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

92

void dce110_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h

93

void dce110_set_pipe(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

101

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

105

if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

124

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

126

params.source_view_width = pipe_ctx->stream->timing.h_addressable;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

127

params.source_view_height = pipe_ctx->stream->timing.v_addressable;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

128

params.inst = pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

143

static void dce60_set_default_colors(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

148

default_adjust.in_color_space = pipe_ctx->plane_state->color_space;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

149

default_adjust.out_color_space = pipe_ctx->stream->output_color_space;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

151

default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

155

pipe_ctx->stream->timing.display_color_depth;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

158

default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

160

pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

161

pipe_ctx->plane_res.xfm, &default_adjust);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

182

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

188

if (!pipe_ctx->plane_state->visible)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

192

pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

197

static void dce60_get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

200

uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

202

switch (pipe_ctx->plane_res.scl_data.format) {

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

233

const struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

240

dce60_get_surface_visual_confirm_color(pipe_ctx, &color);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

243

pipe_ctx->stream->output_color_space,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

246

pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

247

pipe_ctx->plane_res.xfm,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

248

pipe_ctx->plane_res.scl_data.lb_params.depth,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

249

&pipe_ctx->stream->bit_depth_params);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

251

if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) {

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

257

if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

260

pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

261

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

265

pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

266

&pipe_ctx->plane_res.scl_data);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

271

struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

273

struct mem_input *mi = pipe_ctx->plane_res.mi;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

274

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

288

dce60_set_default_colors(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

289

if (pipe_ctx->stream->csc_color_matrix.enable_adjustment

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

292

pipe_ctx->stream->output_color_space;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

296

pipe_ctx->stream->csc_color_matrix.matrix[i];

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

298

pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

299

(pipe_ctx->plane_res.xfm, &tbl_entry);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

302

if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

307

pipe_ctx->stream->gamut_remap_matrix.matrix[i];

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

310

pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

312

pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

314

dce60_program_scaler(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

325

mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

329

pipe_ctx->plane_res.mi,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

335

if (pipe_ctx->plane_state->update_flags.bits.full_update ||

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

336

pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

337

pipe_ctx->plane_state->update_flags.bits.gamma_change)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

338

hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

340

if (pipe_ctx->plane_state->update_flags.bits.full_update)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

341

hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

349

pipe_ctx->pipe_idx,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

350

(void *) pipe_ctx->plane_state,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

351

pipe_ctx->plane_state->address.grph.addr.high_part,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

352

pipe_ctx->plane_state->address.grph.addr.low_part,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

353

pipe_ctx->plane_state->src_rect.x,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

354

pipe_ctx->plane_state->src_rect.y,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

355

pipe_ctx->plane_state->src_rect.width,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

356

pipe_ctx->plane_state->src_rect.height,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

357

pipe_ctx->plane_state->dst_rect.x,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

358

pipe_ctx->plane_state->dst_rect.y,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

359

pipe_ctx->plane_state->dst_rect.width,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

360

pipe_ctx->plane_state->dst_rect.height,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

361

pipe_ctx->plane_state->clip_rect.x,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

362

pipe_ctx->plane_state->clip_rect.y,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

363

pipe_ctx->plane_state->clip_rect.width,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

364

pipe_ctx->plane_state->clip_rect.height);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

370

pipe_ctx->pipe_idx,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

371

pipe_ctx->plane_res.scl_data.viewport.width,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

372

pipe_ctx->plane_res.scl_data.viewport.height,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

373

pipe_ctx->plane_res.scl_data.viewport.x,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

374

pipe_ctx->plane_res.scl_data.viewport.y,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

375

pipe_ctx->plane_res.scl_data.recout.width,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

376

pipe_ctx->plane_res.scl_data.recout.height,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

377

pipe_ctx->plane_res.scl_data.recout.x,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

378

pipe_ctx->plane_res.scl_data.recout.y);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

396

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

398

if (pipe_ctx->stream != stream)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

402

pipe_ctx->plane_res.mi->funcs->allocate_mem_input(

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

403

pipe_ctx->plane_res.mi,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

404

pipe_ctx->stream->timing.h_total,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

405

pipe_ctx->stream->timing.v_total,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

406

pipe_ctx->stream->timing.pix_clk_100hz / 10,

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

409

dce60_program_front_end_for_pipe(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

411

dc->hwss.update_plane_addr(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

413

dce60_program_surface_visibility(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

55

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

71

if (res_ctx->pipe_ctx[i].stream) {

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

73

pipe_ctx = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

75

if (!pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

79

if (pipe_ctx->pipe_idx != underlay_idx) {

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

89

if (!pipe_ctx->stream->link)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

93

if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP)

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

97

if (pipe_ctx->stream->link->psr_settings.psr_feature_enabled)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

102

void dcn10_wait_for_pipe_update_if_needed(struct dc *dc, struct pipe_ctx *pipe_ctx, bool is_surface_update_only)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

105

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

111

if (!pipe_ctx->stream ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

112

!pipe_ctx->stream_res.tg ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

113

!pipe_ctx->stream_res.stream_enc)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1138

struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1153

static int calculate_vready_offset_for_group(struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1155

struct pipe_ctx *other_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

116

if (pipe_ctx->prev_odm_pipe &&

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

117

pipe_ctx->stream)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1180

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1184

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1192

if (pipe_ctx->top_pipe != NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

120

if (!pipe_ctx->wait_is_required)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1200

pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1202

if (false == pipe_ctx->clock_source->funcs->program_pix_clk(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1203

pipe_ctx->clock_source,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1204

&pipe_ctx->stream_res.pix_clk_params,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1205

dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings),

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1206

&pipe_ctx->pll_settings)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1219

pipe_ctx->stream_res.tg->funcs->program_timing(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1220

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1222

calculate_vready_offset_for_group(pipe_ctx),

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1223

pipe_ctx->pipe_dlg_param.vstartup_start,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1224

pipe_ctx->pipe_dlg_param.vupdate_offset,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1225

pipe_ctx->pipe_dlg_param.vupdate_width,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1226

pipe_ctx->pipe_dlg_param.pstate_keepout,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1227

pipe_ctx->stream->signal,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

123

struct timing_generator *tg = pipe_ctx->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1234

inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1236

pipe_ctx->stream_res.opp->funcs->opp_program_fmt(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1237

pipe_ctx->stream_res.opp,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1253

if (pipe_ctx->stream_res.tg->funcs->set_blank_color)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1254

pipe_ctx->stream_res.tg->funcs->set_blank_color(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1255

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1258

if (pipe_ctx->stream_res.tg->funcs->is_blanked &&

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1259

!pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1260

pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1261

hwss_wait_for_blank_complete(pipe_ctx->stream_res.tg);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1262

false_optc_underflow_wa(dc, pipe_ctx->stream, pipe_ctx->stream_res.tg);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1266

if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

128

dc->hwss.calc_vupdate_position(dc, pipe_ctx, &vupdate_start,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1284

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1290

if (pipe_ctx->stream_res.stream_enc == NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1291

pipe_ctx->stream = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1295

link = pipe_ctx->stream->link;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1302

if (!pipe_ctx->stream->dpms_off || link->link_status.link_active)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1303

dc->link_srv->set_dpms_off(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1304

else if (pipe_ctx->stream_res.audio)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1305

dc->hwss.disable_audio_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1307

if (pipe_ctx->stream_res.audio) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1309

pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

131

dc->hwss.get_position(&pipe_ctx, 1, &position);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1316

pipe_ctx->stream_res.audio, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1317

pipe_ctx->stream_res.audio = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1325

if (pipe_ctx->top_pipe == NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1327

if (pipe_ctx->stream_res.abm)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1328

dc->hwss.set_abm_immediate_disable(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1330

pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1332

pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1333

set_drr_and_clear_adjust_pending(pipe_ctx, pipe_ctx->stream, NULL);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1334

if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1335

pipe_ctx->stream->link->phy_state.symclk_ref_cnts.otg = 0;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1339

if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1345

pipe_ctx->stream = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1347

pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

136

if (frame_count - pipe_ctx->wait_frame_count > 2)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1368

struct pipe_ctx *pipe_ctx =

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1369

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1370

if (pipe_ctx != NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1371

hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1381

struct pipe_ctx *pipe_ctx =

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1382

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1383

if (pipe_ctx != NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1384

hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

139

vblank_start = pipe_ctx->pipe_dlg_param.vblank_start;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1391

struct pipe_ctx *pipe_ctx =

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1392

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1393

if (pipe_ctx != NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1394

hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1403

struct pipe_ctx *pipe_ctx =

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1404

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1405

if (pipe_ctx != NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1406

hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1430

TRACE_DC_PIPE_STATE(pipe_ctx, i, MAX_PIPES);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1443

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1446

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1447

int dpp_id = pipe_ctx->plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1451

struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1463

if (dc_state_get_pipe_subvp_type(state, pipe_ctx) != SUBVP_PHANTOM)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1464

opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1521

void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1524

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1525

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1528

dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1534

if (opp_id != 0xf && pipe_ctx->stream_res.opp->mpc_tree_params.opp_list == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1535

pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1536

pipe_ctx->stream_res.opp,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1543

pipe_ctx->plane_res.dpp,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1544

pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1546

pipe_ctx->stream = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1547

memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1548

memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1549

pipe_ctx->top_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1550

pipe_ctx->bottom_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1551

pipe_ctx->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1554

void dcn10_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1559

if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1562

hws->funcs.plane_atomic_disable(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1567

pipe_ctx->pipe_idx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1587

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1593

if (pipe_ctx->stream != NULL && can_apply_seamless_boot)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

160

pipe_ctx->wait_is_required = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1613

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1617

if (pipe_ctx->stream != NULL && can_apply_seamless_boot)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1630

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1633

if (pipe_ctx->stream != NULL && can_apply_seamless_boot)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1644

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1651

pipe_ctx->stream != NULL &&

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1652

pipe_ctx->stream_res.tg->funcs->is_tg_enabled(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1653

pipe_ctx->stream_res.tg)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1665

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

167

pipe_ctx->next_vupdate = 0;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1670

pipe_ctx->stream_res.tg = tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1671

pipe_ctx->pipe_idx = i;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1673

pipe_ctx->plane_res.hubp = hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1674

pipe_ctx->plane_res.dpp = dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1675

pipe_ctx->plane_res.mpcc_inst = dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

168

pipe_ctx->wait_frame_count = 0;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1682

dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1683

pipe_ctx->stream_res.opp = dc->res_pool->opps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1685

hws->funcs.plane_atomic_disconnect(dc, context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

169

pipe_ctx->wait_is_required = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1690

dc->hwss.disable_plane(dc, context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1692

pipe_ctx->stream_res.tg = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1693

pipe_ctx->plane_res.hubp = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

178

void dcn10_set_wait_for_update_needed_for_pipe(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

184

if (!pipe_ctx->stream ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

185

!pipe_ctx->stream_res.tg ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

186

!pipe_ctx->stream_res.stream_enc)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

189

dc->hwss.get_position(&pipe_ctx, 1, &position);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

192

dc->hwss.calc_vupdate_position(dc, pipe_ctx, &vupdate_start,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

195

struct timing_generator *tg = pipe_ctx->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1956

struct pipe_ctx *pipe_ctx_old =

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1957

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1958

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1966

if (!pipe_ctx->stream ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1967

pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1980

struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1982

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1983

bool sec_split = pipe_ctx->top_pipe &&

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1984

pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1986

(pipe_ctx->stream->timing.timing_3d_format ==

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1988

pipe_ctx->stream->timing.timing_3d_format ==

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1995

if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2007

void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2011

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2016

addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2018

pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2019

pipe_ctx->plane_res.hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2029

pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2032

bool dcn10_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2035

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

204

pipe_ctx->next_vupdate = vupdate_start;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

209

pipe_ctx->wait_frame_count = cur_frame;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2110

bool dcn10_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2113

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

212

pipe_ctx->wait_frame_count = cur_frame + 1 - optc1->max_frame_count;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

214

pipe_ctx->wait_frame_count = cur_frame + 1;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2150

struct pipe_ctx *pipe,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

217

pipe_ctx->wait_is_required = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2191

static void delay_cursor_until_vupdate(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2193

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2202

if (!pipe_ctx->stream_res.stream_enc || !pipe_ctx->stream_res.tg)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2205

dc->hwss.calc_vupdate_position(dc, pipe_ctx, &vupdate_start,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2208

dc->hwss.get_position(&pipe_ctx, 1, &position);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2239

void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

224

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

225

struct pipe_ctx *old_pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

230

old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

231

pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

232

tg = pipe_ctx->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2354

static bool is_low_refresh_rate(struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2363

static uint8_t get_clock_divider(struct pipe_ctx *pipe,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

238

if (pipe_ctx->top_pipe ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2385

struct pipe_ctx *grouped_pipes[])

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

239

!pipe_ctx->stream ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

240

(!pipe_ctx->plane_state && !old_pipe_ctx->plane_state) ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

242

dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

246

dc->hwss.pipe_control_lock(dc, pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2478

struct pipe_ctx *grouped_pipes[])

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

248

dc->hwss.pipe_control_lock(dc, pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2544

struct pipe_ctx *grouped_pipes[])

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2625

struct pipe_ctx *grouped_pipes[])

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2732

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2744

pipe_ctx->plane_res.hubp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2747

pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2750

pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2751

pipe_ctx->stream_res.opp,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2755

dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2761

if (!pipe_ctx->top_pipe

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2762

&& pipe_ctx->plane_state

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2763

&& pipe_ctx->plane_state->flip_int_enabled

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2764

&& pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2765

pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2769

void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2777

if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2781

pipe_ctx->stream->gamut_remap_matrix.matrix[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2782

} else if (pipe_ctx->plane_state &&

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2783

pipe_ctx->plane_state->gamut_remap_matrix.enable_remap == true) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2787

pipe_ctx->plane_state->gamut_remap_matrix.matrix[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2790

pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2794

static bool dcn10_is_rear_mpo_fix_required(struct pipe_ctx *pipe_ctx, enum dc_color_space colorspace)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2796

if (pipe_ctx->plane_state && pipe_ctx->plane_state->layer_index > 0 && is_rgb_cspace(colorspace)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2797

if (pipe_ctx->top_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2798

struct pipe_ctx *top = pipe_ctx->top_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2812

static void dcn10_set_csc_adjustment_rgb_mpo_fix(struct pipe_ctx *pipe_ctx, uint16_t *matrix)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2820

pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2827

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2832

if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2833

if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2846

if (rgb_bias > 0 && dcn10_is_rear_mpo_fix_required(pipe_ctx, colorspace)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2847

dcn10_set_csc_adjustment_rgb_mpo_fix(pipe_ctx, matrix);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2849

pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2853

if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default != NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2854

pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2877

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2883

mpc->funcs->set_bg_color(mpc, &(pipe_ctx->visual_confirm_color), mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2887

void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2889

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2891

bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2895

struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2905

pipe_ctx->stream->output_color_space)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2906

&& pipe_ctx->plane_state->pre_multiplied_alpha);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2907

if (pipe_ctx->plane_state->global_alpha) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2909

blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2918

if (pipe_ctx->plane_state->global_alpha)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2919

blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2934

if (!pipe_ctx->plane_state->update_flags.bits.full_update) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2936

dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2958

dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2961

hubp->opp_id = pipe_ctx->stream_res.opp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2965

static void update_scaler(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2968

pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2970

pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2971

pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2973

pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2974

pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2979

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2983

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2984

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2985

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3038

pipe_ctx->plane_res.bw.dppclk_khz);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3050

hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3054

&pipe_ctx->dlg_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3055

&pipe_ctx->ttu_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3056

&pipe_ctx->rq_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3057

&pipe_ctx->pipe_dlg_param);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3060

&pipe_ctx->dlg_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3061

&pipe_ctx->ttu_regs);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3064

size.surface_size = pipe_ctx->plane_res.scl_data.viewport;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3073

hws->funcs.update_mpcc(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3080

update_scaler(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3088

&pipe_ctx->plane_res.scl_data.viewport,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3089

&pipe_ctx->plane_res.scl_data.viewport_c);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3092

if (pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3094

dc->hwss.abort_cursor_offload_update(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3096

dc->hwss.set_cursor_attribute(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3097

dc->hwss.set_cursor_position(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3100

dc->hwss.set_cursor_sdr_white_level(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3105

dc->hwss.program_gamut_remap(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3108

pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3109

pipe_ctx->stream->output_color_space,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3110

pipe_ctx->stream->csc_color_matrix.matrix,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3111

pipe_ctx->stream_res.opp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3136

dc->hwss.update_plane_addr(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3138

if (is_pipe_tree_visible(pipe_ctx))

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3144

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3149

struct stream_resource *stream_res = &pipe_ctx->stream_res;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3150

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3174

dc->hwss.set_pipe(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3178

dc->hwss.set_abm_immediate_disable(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3186

void dcn10_set_hdr_multiplier(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3188

struct fixed31_32 multiplier = pipe_ctx->plane_state->hdr_mult;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3200

pipe_ctx->plane_res.dpp->funcs->dpp_set_hdr_multiplier(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3201

pipe_ctx->plane_res.dpp, hw_mult);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3206

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3211

if (pipe_ctx->top_pipe == NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3212

bool blank = !is_pipe_tree_visible(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3214

pipe_ctx->stream_res.tg->funcs->program_global_sync(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3215

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3216

calculate_vready_offset_for_group(pipe_ctx),

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3217

pipe_ctx->pipe_dlg_param.vstartup_start,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3218

pipe_ctx->pipe_dlg_param.vupdate_offset,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3219

pipe_ctx->pipe_dlg_param.vupdate_width,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3220

pipe_ctx->pipe_dlg_param.pstate_keepout);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3222

pipe_ctx->stream_res.tg->funcs->set_vtg_params(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3223

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3226

hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3228

hws->funcs.blank_pixel_data(dc, pipe_ctx, blank);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3231

if (pipe_ctx->plane_state->update_flags.bits.full_update)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3232

dcn10_enable_plane(dc, pipe_ctx, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3234

dcn10_update_dchubp_dpp(dc, pipe_ctx, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3236

hws->funcs.set_hdr_multiplier(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3238

if (pipe_ctx->plane_state->update_flags.bits.full_update ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3239

pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3240

pipe_ctx->plane_state->update_flags.bits.gamma_change)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3241

hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3249

if (pipe_ctx->plane_state->update_flags.bits.full_update)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3250

hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3256

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3261

pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3262

tg = pipe_ctx->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3268

if (pipe_ctx->top_pipe ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3269

!pipe_ctx->stream || !pipe_ctx->plane_state ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3280

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3281

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3292

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3294

if (!pipe_ctx->top_pipe &&

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3295

!pipe_ctx->prev_odm_pipe &&

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3296

pipe_ctx->stream) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3297

struct timing_generator *tg = pipe_ctx->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3300

false_optc_underflow_wa(dc, pipe_ctx->stream, tg);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3305

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3306

dc->hwss.disable_plane(dc, dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i]);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3309

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3411

void dcn10_set_drr(struct pipe_ctx **pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3434

struct timing_generator *tg = pipe_ctx[i]->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3437

set_drr_and_clear_adjust_pending(pipe_ctx[i], pipe_ctx[i]->stream, &params);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3446

void dcn10_get_position(struct pipe_ctx **pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3455

pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3458

void dcn10_set_static_screen_control(struct pipe_ctx **pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3472

pipe_ctx[i]->stream_res.tg->funcs->

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3473

set_static_screen_control(pipe_ctx[i]->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3519

void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3522

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3533

pipe_ctx->stream_res.opp->funcs->opp_program_stereo(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3534

pipe_ctx->stream_res.opp,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3538

pipe_ctx->stream_res.tg->funcs->program_stereo(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3539

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3561

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3570

if (!pipe_ctx->stream_res.opp)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3574

if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3577

if (pipe_ctx->stream_res.tg &&

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3578

pipe_ctx->stream_res.tg->funcs->is_tg_enabled(pipe_ctx->stream_res.tg))

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3580

pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3600

void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3602

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3603

struct timing_generator *tg = pipe_ctx->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3605

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3610

flip_pending = pipe_ctx->plane_res.hubp->funcs->hubp_is_flip_pending(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3611

pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3621

!tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3646

void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3648

struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3649

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3650

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3652

.pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3653

.ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3654

.viewport = pipe_ctx->plane_res.scl_data.viewport,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3655

.h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3656

.v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3657

.rotation = pipe_ctx->plane_state->rotation,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3658

.mirror = pipe_ctx->plane_state->horizontal_mirror,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3659

.stream = pipe_ctx->stream,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3662

bool odm_combine_on = (pipe_ctx->next_odm_pipe != NULL) ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3663

(pipe_ctx->prev_odm_pipe != NULL);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3665

int x_plane = pipe_ctx->plane_state->dst_rect.x;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3666

int y_plane = pipe_ctx->plane_state->dst_rect.y;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3669

bool is_primary_plane = (pipe_ctx->plane_state->layer_index == 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3673

? param.viewport.x : pipe_ctx->plane_state->clip_rect.x;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3674

int clip_width = pipe_ctx->plane_state->clip_rect.width;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3676

if ((pipe_ctx->top_pipe != NULL) || (pipe_ctx->bottom_pipe != NULL)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3677

if ((pipe_ctx->plane_state->src_rect.width != pipe_ctx->plane_res.scl_data.viewport.width) ||

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3678

(pipe_ctx->plane_state->src_rect.height != pipe_ctx->plane_res.scl_data.viewport.height)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3701

x_pos = (x_pos - x_plane) * pipe_ctx->plane_state->src_rect.height /

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3702

pipe_ctx->plane_state->dst_rect.width;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3703

y_pos = (y_pos - y_plane) * pipe_ctx->plane_state->src_rect.width /

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3704

pipe_ctx->plane_state->dst_rect.height;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3706

x_pos = (x_pos - x_plane) * pipe_ctx->plane_state->src_rect.width /

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3707

pipe_ctx->plane_state->dst_rect.width;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3708

y_pos = (y_pos - y_plane) * pipe_ctx->plane_state->src_rect.height /

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3709

pipe_ctx->plane_state->dst_rect.height;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3710

clip_x = (clip_x - x_plane) * pipe_ctx->plane_state->src_rect.width /

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3711

pipe_ctx->plane_state->dst_rect.width;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3712

clip_width = clip_width * pipe_ctx->plane_state->src_rect.width /

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3713

pipe_ctx->plane_state->dst_rect.width;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3729

x_pos += pipe_ctx->plane_state->src_rect.x;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3730

y_pos += pipe_ctx->plane_state->src_rect.y;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3751

if (pipe_ctx->plane_state->address.type

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3755

if (pos_cpy.enable && resource_can_pipe_disable_cursor(pipe_ctx))

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3778

pos_cpy.x = pipe_ctx->plane_res.scl_data.viewport.width -

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3779

(pos_cpy.y - pipe_ctx->plane_res.scl_data.viewport.x) + pipe_ctx->plane_res.scl_data.viewport.x;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3786

pipe_ctx->plane_res.scl_data.viewport.height;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3788

pipe_ctx->plane_res.scl_data.viewport.y;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3808

if (pipe_ctx->bottom_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3810

pipe_ctx->bottom_pipe->plane_res.scl_data.viewport.y;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3813

pipe_ctx->top_pipe->plane_res.scl_data.viewport.y;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3816

if (pipe_ctx->next_odm_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3818

pipe_ctx->next_odm_pipe->plane_res.scl_data.viewport.y;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3821

pipe_ctx->prev_odm_pipe->plane_res.scl_data.viewport.y;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3862

pos_cpy.y = (2 * pipe_ctx->plane_res.scl_data.viewport.y) +

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3863

pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.y;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3870

void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3872

struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3874

pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3875

pipe_ctx->plane_res.hubp, attributes);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3876

pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3877

pipe_ctx->plane_res.dpp, attributes);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3880

void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3882

uint32_t sdr_white_level = pipe_ctx->stream->cursor_attributes.sdr_white_level;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3888

if (!pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3903

pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3904

pipe_ctx->plane_res.dpp, &opt_attr);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3925

int dcn10_get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3927

const struct dc_crtc_timing *dc_crtc_timing = &pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3948

pipe_ctx->pipe_dlg_param.vstartup_start + 1;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3953

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3957

const struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3958

int vupdate_pos = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3969

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3973

const struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3974

int vline_pos = pipe_ctx->stream->periodic_interrupt.lines_offset;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3976

if (pipe_ctx->stream->periodic_interrupt.ref_point == START_V_UPDATE) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3982

vline_pos += dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3988

} else if (pipe_ctx->stream->periodic_interrupt.ref_point == START_V_SYNC) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3998

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4000

struct timing_generator *tg = pipe_ctx->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4004

dcn10_cal_vline_position(dc, pipe_ctx, &start_line, &end_line);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4009

void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4011

struct timing_generator *tg = pipe_ctx->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4012

int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4023

void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4027

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4032

params.timing = pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4036

if (dc_is_dp_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4039

pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4047

void dcn10_send_immediate_sdp_message(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4051

if (dc_is_dp_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4052

pipe_ctx->stream_res.stream_enc->funcs->send_immediate_sdp_message(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4053

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4134

void dcn10_reset_surface_dcc_and_tiling(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4138

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

814

bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

816

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

817

struct timing_generator *tg = pipe_ctx->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

104

void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

109

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

111

void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

120

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

122

void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

130

struct pipe_ctx *grouped_pipes[]);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

135

struct pipe_ctx *grouped_pipes[]);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

139

struct pipe_ctx *grouped_pipes[]);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

140

void dce110_update_info_frame(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

141

void dcn10_send_immediate_sdp_message(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

144

void dce110_blank_stream(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

145

void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

146

void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

152

void dcn10_set_drr(struct pipe_ctx **pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

154

void dcn10_get_position(struct pipe_ctx **pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

157

void dcn10_set_static_screen_control(struct pipe_ctx **pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

159

void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

160

void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

171

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

183

void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

184

void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

185

void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

188

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

196

bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

207

void dcn10_set_hdr_multiplier(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

214

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

217

void dcn10_reset_surface_dcc_and_tiling(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

36

int dcn10_get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

39

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

42

void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

44

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

55

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

59

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

62

struct pipe_ctx *pipe,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

64

void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

67

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

69

void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

72

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

76

bool dcn10_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

78

bool dcn10_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

80

void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

81

void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

85

void dcn10_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1014

bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1017

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1018

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1029

if (pipe_ctx->top_pipe == NULL

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1033

else if (pipe_ctx->stream->out_transfer_func.type ==

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1055

struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1057

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1075

struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1077

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1101

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1105

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1113

hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1114

hws->funcs.set_blend_lut(pipe_ctx, plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1176

void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1178

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1180

int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1181

int odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1182

int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1184

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1190

pipe_ctx->stream_res.tg->funcs->set_odm_combine(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1191

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1195

pipe_ctx->stream_res.tg->funcs->set_odm_bypass(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1196

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1201

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1205

struct stream_resource *stream_res = &pipe_ctx->stream_res;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1206

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1210

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1220

dc->hwss.set_abm_immediate_disable(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1230

odm_pipe = pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1259

dc->hwss.set_pipe(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1267

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1274

hws->funcs.dpp_root_clock_control(hws, pipe_ctx->plane_res.dpp->inst, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1283

hws->funcs.dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1286

hws->funcs.hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1293

"Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1297

void dcn20_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1303

dcn20_power_on_plane_resources(dc->hwseq, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1306

pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1309

pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1312

pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1313

pipe_ctx->stream_res.opp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1362

pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1365

if (!pipe_ctx->top_pipe

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1366

&& pipe_ctx->plane_state

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1367

&& pipe_ctx->plane_state->flip_int_enabled

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1368

&& pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1369

pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1378

struct pipe_ctx *pipe,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1381

struct pipe_ctx *temp_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1478

struct pipe_ctx *old_pipe,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1479

struct pipe_ctx *new_pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1666

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1670

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1671

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1672

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1675

enum mall_stream_type pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1677

if (pipe_ctx->update_flags.bits.dppclk)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1680

if (pipe_ctx->update_flags.bits.enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1681

dccg->funcs->update_dpp_dto(dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1688

if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1689

hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1694

&pipe_ctx->hubp_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1695

&pipe_ctx->global_sync,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1696

&pipe_ctx->stream->timing);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1700

&pipe_ctx->dlg_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1701

&pipe_ctx->ttu_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1702

&pipe_ctx->rq_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1703

&pipe_ctx->pipe_dlg_param);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1707

if (pipe_ctx->update_flags.bits.unbounded_req && hubp->funcs->set_unbounded_requesting)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1708

hubp->funcs->set_unbounded_requesting(hubp, pipe_ctx->unbounded_req);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1710

if (pipe_ctx->update_flags.bits.hubp_interdependent) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1714

&pipe_ctx->hubp_regs);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1718

&pipe_ctx->dlg_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1719

&pipe_ctx->ttu_regs);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1723

if (pipe_ctx->update_flags.bits.enable ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1724

pipe_ctx->update_flags.bits.plane_changed ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1750

if (pipe_ctx->update_flags.bits.mpcc

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1751

|| pipe_ctx->update_flags.bits.plane_changed

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1755

hws->funcs.update_mpcc(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1758

if (pipe_ctx->update_flags.bits.scaler ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1762

pipe_ctx->stream->update_flags.bits.scaling) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1763

pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1764

ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_36BPP);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1766

pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1767

pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1770

if (pipe_ctx->update_flags.bits.viewport ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1773

(context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1777

&pipe_ctx->plane_res.scl_data.viewport,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1778

&pipe_ctx->plane_res.scl_data.viewport_c);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1783

hubp->funcs->hubp_program_mcache_id_and_split_coordinate(hubp, &pipe_ctx->mcache_regs);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1786

if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1787

pipe_ctx->update_flags.bits.scaler || viewport_changed == true) &&

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1788

pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1790

dc->hwss.abort_cursor_offload_update(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1792

dc->hwss.set_cursor_attribute(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1793

dc->hwss.set_cursor_position(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1796

dc->hwss.set_cursor_sdr_white_level(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1801

if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1802

|| pipe_ctx->update_flags.bits.plane_changed

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1803

|| pipe_ctx->stream->update_flags.bits.gamut_remap

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1805

|| pipe_ctx->stream->update_flags.bits.out_csc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1807

dc->hwss.program_gamut_remap(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1811

pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1812

pipe_ctx->stream->output_color_space,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1813

pipe_ctx->stream->csc_color_matrix.matrix,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1817

if (pipe_ctx->update_flags.bits.enable ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1818

pipe_ctx->update_flags.bits.plane_changed ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1819

pipe_ctx->update_flags.bits.opp_changed ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1830

size.surface_size = pipe_ctx->plane_res.scl_data.viewport;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1843

if (pipe_ctx->update_flags.bits.enable ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1844

pipe_ctx->update_flags.bits.plane_changed ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1846

if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) &&

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1851

params.subvp_save_surf_addr.addr = &pipe_ctx->plane_state->address;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1852

params.subvp_save_surf_addr.subvp_index = pipe_ctx->subvp_index;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1855

dc->hwss.update_plane_addr(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1858

if (pipe_ctx->update_flags.bits.enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1865

static int dcn20_calculate_vready_offset_for_group(struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1867

struct pipe_ctx *other_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1893

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1897

pipe_ctx->stream_res.tg->funcs->program_global_sync(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1898

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1899

dcn20_calculate_vready_offset_for_group(pipe_ctx),

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1900

pipe_ctx->pipe_dlg_param.vstartup_start,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1901

pipe_ctx->pipe_dlg_param.vupdate_offset,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1902

pipe_ctx->pipe_dlg_param.vupdate_width,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1903

pipe_ctx->pipe_dlg_param.pstate_keepout);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1905

if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1906

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1908

pipe_ctx->stream_res.tg->funcs->set_vtg_params(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1909

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1912

hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1917

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1923

if (resource_is_pipe_type(pipe_ctx, OTG_MASTER)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1924

if (pipe_ctx->update_flags.bits.enable ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1925

pipe_ctx->update_flags.bits.odm ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1926

pipe_ctx->stream->update_flags.bits.abm_level)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1927

hws->funcs.blank_pixel_data(dc, pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1928

!pipe_ctx->plane_state ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1929

!pipe_ctx->plane_state->visible);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1933

if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1934

&& !pipe_ctx->prev_odm_pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1935

dcn20_program_tg(dc, pipe_ctx, context, hws);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1937

if (pipe_ctx->update_flags.bits.odm)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1938

hws->funcs.update_odm(dc, context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1940

if (pipe_ctx->update_flags.bits.enable) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1942

hws->funcs.enable_plane(dc, pipe_ctx, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1944

dcn20_enable_plane(dc, pipe_ctx, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1950

if (pipe_ctx->update_flags.bits.det_size) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1953

dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1957

dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->hubp_regs.det_size);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1960

if (pipe_ctx->plane_state && (pipe_ctx->update_flags.raw ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1961

pipe_ctx->plane_state->update_flags.raw ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1962

pipe_ctx->stream->update_flags.raw))

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1963

dcn20_update_dchubp_dpp(dc, pipe_ctx, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1965

if (pipe_ctx->plane_state && (pipe_ctx->update_flags.bits.enable ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1966

pipe_ctx->plane_state->update_flags.bits.hdr_mult))

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1967

hws->funcs.set_hdr_multiplier(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1969

if (pipe_ctx->plane_state &&

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1970

(pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1971

pipe_ctx->plane_state->update_flags.bits.gamma_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1972

pipe_ctx->plane_state->update_flags.bits.lut_3d ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1973

pipe_ctx->update_flags.bits.enable))

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1974

hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1980

if (pipe_ctx->update_flags.bits.enable ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1981

pipe_ctx->update_flags.bits.plane_changed ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1982

pipe_ctx->stream->update_flags.bits.out_tf)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1983

hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1990

if (pipe_ctx->update_flags.bits.enable

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1991

|| pipe_ctx->update_flags.bits.opp_changed) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1993

pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1994

pipe_ctx->stream_res.opp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1996

pipe_ctx->stream->timing.display_color_depth,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1997

pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1999

pipe_ctx->stream_res.opp->funcs->opp_program_fmt(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2000

pipe_ctx->stream_res.opp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2001

&pipe_ctx->stream->bit_depth_params,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2002

&pipe_ctx->stream->clamping);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2006

if ((pipe_ctx->plane_state && pipe_ctx->plane_state->visible)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2007

if (pipe_ctx->stream_res.abm) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2008

dc->hwss.set_pipe(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2009

pipe_ctx->stream_res.abm->funcs->set_abm_level(pipe_ctx->stream_res.abm,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2010

pipe_ctx->stream->abm_level);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2014

if (pipe_ctx->update_flags.bits.test_pattern_changed) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2015

struct output_pixel_processor *odm_opp = pipe_ctx->stream_res.opp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2021

pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2022

pipe_ctx->stream_res.test_pattern_params.test_pattern,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2023

pipe_ctx->stream_res.test_pattern_params.color_space,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2024

pipe_ctx->stream_res.test_pattern_params.color_depth,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2026

pipe_ctx->stream_res.test_pattern_params.width,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2027

pipe_ctx->stream_res.test_pattern_params.height,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2028

pipe_ctx->stream_res.test_pattern_params.offset);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2040

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2049

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2061

if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2063

if (context->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2076

dcn20_detect_pipe_changes(dc->current_state, context, &dc->current_state->res_ctx.pipe_ctx[i],

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2077

&context->res_ctx.pipe_ctx[i]);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2083

struct dc_stream_state *stream = dc->current_state->res_ctx.pipe_ctx[i].stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2085

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2087

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable && stream &&

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2089

struct timing_generator *tg = dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2101

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2102

&& !context->res_ctx.pipe_ctx[i].top_pipe

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2103

&& !context->res_ctx.pipe_ctx[i].prev_odm_pipe

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2104

&& context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2105

hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2109

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2110

|| context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2119

if ((context->res_ctx.pipe_ctx[i].update_flags.bits.disable ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2120

(context->res_ctx.pipe_ctx[i].plane_state &&

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2121

dc_state_get_pipe_subvp_type(context, &context->res_ctx.pipe_ctx[i])

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2125

dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2128

hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2131

&dc->current_state->res_ctx.pipe_ctx[i]);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2132

DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2137

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2150

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2175

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

220

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2200

struct pipe_ctx *opp_head)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2243

if (resource_is_pipe_type(&dc->current_state->res_ctx.pipe_ctx[i], OPP_HEAD) &&

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2244

!resource_is_pipe_type(&context->res_ctx.pipe_ctx[i], OPP_HEAD))

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2246

&dc->current_state->res_ctx.pipe_ctx[i]);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2249

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2250

dc->hwss.disable_plane(dc, dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i]);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2259

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2273

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2274

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2299

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

232

if (pipe_ctx->stream_res.gsl_group > 0)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

237

pipe_ctx->stream_res.gsl_group = group_idx;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2377

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2421

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2461

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2463

if (pipe_ctx->stream && pipe_ctx->plane_res.hubp->funcs->program_extended_blank

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2464

&& pipe_ctx->stream->adjust.v_total_min == pipe_ctx->stream->adjust.v_total_max

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2465

&& pipe_ctx->stream->adjust.v_total_max > pipe_ctx->stream->timing.v_total)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2466

pipe_ctx->plane_res.hubp->funcs->program_extended_blank(pipe_ctx->plane_res.hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2467

pipe_ctx->dlg_regs.min_dst_y_next_start);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2488

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2490

if (pipe_ctx->plane_state == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2493

if (pipe_ctx->top_pipe == NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2494

bool blank = !is_pipe_tree_visible(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2496

pipe_ctx->stream_res.tg->funcs->program_global_sync(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2497

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2498

dcn20_calculate_vready_offset_for_group(pipe_ctx),

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2499

pipe_ctx->pipe_dlg_param.vstartup_start,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2500

pipe_ctx->pipe_dlg_param.vupdate_offset,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2501

pipe_ctx->pipe_dlg_param.vupdate_width,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2502

pipe_ctx->pipe_dlg_param.pstate_keepout);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2504

pipe_ctx->stream_res.tg->funcs->set_vtg_params(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2505

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2507

if (pipe_ctx->prev_odm_pipe == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2508

hws->funcs.blank_pixel_data(dc, pipe_ctx, blank);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2511

hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2514

pipe_ctx->plane_res.hubp->funcs->hubp_setup(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2515

pipe_ctx->plane_res.hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2516

&pipe_ctx->dlg_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2517

&pipe_ctx->ttu_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2518

&pipe_ctx->rq_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2519

&pipe_ctx->pipe_dlg_param);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

259

group_idx = pipe_ctx->stream_res.gsl_group;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2590

bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2592

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2599

void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2603

if (pipe_ctx->stream_res.dsc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2604

struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2606

hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2614

void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2618

if (pipe_ctx->stream_res.dsc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2619

struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2621

hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2629

void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

263

pipe_ctx->stream_res.gsl_group = 0;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2632

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2636

dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2638

pipe_ctx->stream->dmdata_address.quad_part;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2690

struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2692

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2693

bool sec_split = pipe_ctx->top_pipe &&

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2694

pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2696

(pipe_ctx->stream->timing.timing_3d_format ==

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2698

pipe_ctx->stream->timing.timing_3d_format ==

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2706

if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2717

void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2721

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2726

addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2729

vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2731

pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2732

pipe_ctx->plane_res.hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2742

pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2745

void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2749

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2752

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2754

pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2758

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2762

params.timing = pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2766

if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2768

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2769

pipe_ctx->stream_res.hpo_dp_stream_enc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2770

pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2771

} else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2774

if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2775

pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2776

pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2777

pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2785

void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2787

struct timing_generator *tg = pipe_ctx->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2788

int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2799

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2802

struct dc_link *link = pipe_ctx->stream->link;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2803

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2808

if (pipe_ctx->stream_res.stream_enc == NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2809

pipe_ctx->stream = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2819

if (!pipe_ctx->stream->dpms_off || link->link_status.link_active)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2820

dc->link_srv->set_dpms_off(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2821

else if (pipe_ctx->stream_res.audio)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2822

dc->hwss.disable_audio_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2825

if (pipe_ctx->stream_res.audio) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2827

pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2834

pipe_ctx->stream_res.audio, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2835

pipe_ctx->stream_res.audio = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2843

if (pipe_ctx->top_pipe == NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2845

dc->hwss.set_abm_immediate_disable(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2847

pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2849

pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2850

if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2851

pipe_ctx->stream_res.tg->funcs->set_odm_bypass(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2852

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2854

set_drr_and_clear_adjust_pending(pipe_ctx, pipe_ctx->stream, NULL);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2859

if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2863

&pipe_ctx->link_res, pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2866

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) && dccg

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2868

dto_params.otg_inst = pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2869

dto_params.timing = &pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

287

if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

288

pipe_ctx->stream_res.tg->funcs->set_gsl(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2880

pipe_ctx->stream = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2881

pipe_ctx->top_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2882

pipe_ctx->bottom_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2883

pipe_ctx->next_odm_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2884

pipe_ctx->prev_odm_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2886

pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

289

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2898

struct pipe_ctx *pipe_ctx_old =

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2899

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2900

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2908

if (!pipe_ctx->stream ||

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2909

pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

291

if (pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

292

pipe_ctx->stream_res.tg->funcs->set_gsl_source_select(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2921

void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2923

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2925

bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2929

struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

293

pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2935

blnd_cfg.pre_multiplied_alpha = pipe_ctx->plane_state->pre_multiplied_alpha;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2936

if (pipe_ctx->plane_state->global_alpha) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2938

blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2947

if (pipe_ctx->plane_state->global_alpha)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2948

blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2958

if (pipe_ctx->plane_state->format

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2973

if (!pipe_ctx->plane_state->update_flags.bits.full_update &&

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2974

!pipe_ctx->update_flags.bits.mpcc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2976

dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

299

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2998

dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3001

hubp->opp_id = pipe_ctx->stream_res.opp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3005

void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3008

pipe_ctx->stream->link->cur_link_settings.lane_count;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3010

struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3011

struct dc_link *link = pipe_ctx->stream->link;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3015

struct timing_generator *tg = pipe_ctx->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3016

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3017

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

302

if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3023

struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3024

struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3029

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

303

pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3031

dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3032

dto_params.num_odm_segments = get_odm_segment_count(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3033

dto_params.timing = &pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3036

dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

304

pipe_ctx->plane_res.hubp, flip_immediate);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3062

pipe_ctx->stream_res.tg->inst,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3063

pipe_ctx->pixel_rate_divider.div_factor1,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3064

pipe_ctx->pixel_rate_divider.div_factor2);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3066

link_hwss->setup_stream_encoder(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3068

if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3070

dc->hwss.program_dmdata_engine(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3073

dc->hwss.update_info_frame(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3075

if (dc_is_dp_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3093

void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3095

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3096

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3098

struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3104

if (pipe_ctx->stream->dmdata_address.quad_part != 0) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3105

pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3185

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3189

pipe_ctx->stream_res.tg = tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3190

pipe_ctx->pipe_idx = i;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3192

pipe_ctx->plane_res.hubp = hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3193

pipe_ctx->plane_res.dpp = dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3194

pipe_ctx->plane_res.mpcc_inst = dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3198

pipe_ctx->stream_res.opp = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3204

dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3205

pipe_ctx->stream_res.opp = dc->res_pool->opps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3207

hws->funcs.plane_atomic_disconnect(dc, context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3222

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3224

dc->hwss.disable_plane(dc, context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3226

pipe_ctx->stream_res.tg = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3227

pipe_ctx->plane_res.hubp = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3241

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3248

pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

379

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

382

if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

383

pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

384

pipe_ctx->plane_res.hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

695

void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

698

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

699

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

701

dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

706

if (pipe_ctx->stream_res.gsl_group != 0)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

707

dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

712

dc->hwss.set_flip_control_gsl(pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

721

pipe_ctx->plane_res.dpp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

722

pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

724

pipe_ctx->stream = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

725

memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

726

memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

727

pipe_ctx->top_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

728

pipe_ctx->bottom_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

729

pipe_ctx->prev_odm_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

730

pipe_ctx->next_odm_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

731

pipe_ctx->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

735

void dcn20_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

737

bool is_phantom = dc_state_get_pipe_subvp_type(state, pipe_ctx) == SUBVP_PHANTOM;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

738

struct timing_generator *tg = is_phantom ? pipe_ctx->stream_res.tg : NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

742

if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

745

dcn20_plane_atomic_disable(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

754

pipe_ctx->pipe_idx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

757

void dcn20_disable_pixel_data(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

759

dcn20_blank_pixel_data(dc, pipe_ctx, blank);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

803

static int get_odm_segment_count(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

805

struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

817

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

822

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

832

pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

836

struct pipe_ctx *opp_heads[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

841

pipe_ctx->stream_res.tg->inst,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

842

pipe_ctx->pixel_rate_divider.div_factor1,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

843

pipe_ctx->pixel_rate_divider.div_factor2);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

849

if (pipe_ctx->top_pipe != NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

854

opp_cnt = resource_get_opp_heads_for_otg_master(pipe_ctx, &context->res_ctx, opp_heads);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

858

odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

859

last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

861

pipe_ctx->stream_res.tg->funcs->set_odm_combine(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

862

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

869

pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

871

if (false == pipe_ctx->clock_source->funcs->program_pix_clk(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

872

pipe_ctx->clock_source,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

873

&pipe_ctx->stream_res.pix_clk_params,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

874

dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings),

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

875

&pipe_ctx->pll_settings)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

880

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

882

struct timing_generator *tg = pipe_ctx->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

889

dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

890

dto_params.num_odm_segments = get_odm_segment_count(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

891

dto_params.timing = &pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

905

dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

907

pipe_ctx->stream_res.tg->funcs->program_timing(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

908

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

910

pipe_ctx->pipe_dlg_param.vready_offset,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

911

pipe_ctx->pipe_dlg_param.vstartup_start,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

912

pipe_ctx->pipe_dlg_param.vupdate_offset,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

913

pipe_ctx->pipe_dlg_param.vupdate_width,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

914

pipe_ctx->pipe_dlg_param.pstate_keepout,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

915

pipe_ctx->stream->signal,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

943

hws->funcs.blank_pixel_data(dc, pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

946

if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

957

set_drr_and_clear_adjust_pending(pipe_ctx, stream, &params);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

966

if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

967

pipe_ctx->stream_res.tg->funcs->set_static_screen_control(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

968

pipe_ctx->stream_res.tg, event_triggers, 2);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

978

if (dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

979

if (pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

980

pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable(pipe_ctx->stream_res.tg);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

987

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

994

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

999

if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

112

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

121

void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

122

bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

123

void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

124

void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

131

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

146

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

155

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

160

struct pipe_ctx *old_pipe,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

161

struct pipe_ctx *new_pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

164

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

168

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

172

struct pipe_ctx *opp_head);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

34

struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

36

struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

43

void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

44

void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

45

bool dcn20_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

47

bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

50

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

54

void dcn20_enable_stream(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

55

void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

57

void dcn20_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

60

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

64

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

68

struct pipe_ctx *pipe,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

83

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

86

void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

87

void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

88

void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

91

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

98

void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

136

void dcn201_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

140

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

148

addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

152

pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

153

pipe_ctx->plane_res.hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

163

pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

309

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

313

pipe_ctx->stream_res.tg = tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

314

pipe_ctx->pipe_idx = i;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

316

pipe_ctx->plane_res.hubp = hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

317

pipe_ctx->plane_res.dpp = dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

318

pipe_ctx->plane_res.mpcc_inst = dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

322

pipe_ctx->stream_res.opp = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

326

res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

327

pipe_ctx->stream_res.opp = res_pool->opps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

329

hws->funcs.plane_atomic_disconnect(dc, context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

344

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

346

dc->hwss.disable_plane(dc, context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

348

pipe_ctx->stream_res.tg = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

349

pipe_ctx->plane_res.hubp = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

380

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

383

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

384

int dpp_id = pipe_ctx->plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

388

struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

414

opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

425

void dcn201_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

427

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

429

bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

434

struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

438

pipe_ctx, &blnd_cfg.black_color);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

441

pipe_ctx, &blnd_cfg.black_color);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

444

dc, pipe_ctx->stream->output_color_space,

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

455

if (pipe_ctx->plane_state->global_alpha_value)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

456

blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

488

if (!pipe_ctx->plane_state->update_flags.bits.full_update) {

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

489

dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

514

dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

524

hubp->opp_id = pipe_ctx->stream_res.opp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

530

struct pipe_ctx *pipe,

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

559

void dcn201_set_cursor_attribute(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

561

struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

563

gpu_addr_to_uma(pipe_ctx->stream->ctx->dc->hwseq, &attributes->address);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

565

pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

566

pipe_ctx->plane_res.hubp, attributes);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

567

pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

568

pipe_ctx->plane_res.dpp, attributes);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

571

void dcn201_set_dmdata_attributes(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

574

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

576

gpu_addr_to_uma(pipe_ctx->stream->ctx->dc->hwseq,

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

577

&pipe_ctx->stream->dmdata_address);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

581

dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

583

pipe_ctx->stream->dmdata_address.quad_part;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

594

void dcn201_unblank_stream(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

598

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

60

struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

603

params.timing = pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

607

if (dc_is_dp_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

609

if (pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing))

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

612

pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

62

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

63

bool sec_split = pipe_ctx->top_pipe &&

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

64

pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

67

(pipe_ctx->stream->timing.timing_3d_format ==

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

69

pipe_ctx->stream->timing.timing_3d_format ==

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

76

if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h

31

void dcn201_set_dmdata_attributes(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h

33

void dcn201_unblank_stream(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h

35

void dcn201_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h

36

void dcn201_plane_atomic_disconnect(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h

37

void dcn201_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h

38

void dcn201_set_cursor_attribute(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h

41

struct pipe_ctx *pipe,

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

128

void dcn21_PLAT_58856_wa(struct dc_state *context, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

130

if (!pipe_ctx->stream->dpms_off)

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

133

pipe_ctx->stream->dpms_off = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

134

pipe_ctx->stream->ctx->dc->link_srv->set_dpms_on(context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

135

pipe_ctx->stream->ctx->dc->link_srv->set_dpms_off(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

136

pipe_ctx->stream->dpms_off = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

178

void dcn21_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

180

struct abm *abm = pipe_ctx->stream_res.abm;

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

181

uint32_t otg_inst = pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

182

struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

183

struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

187

if (pipe_ctx->stream->abm_level == 0 || pipe_ctx->stream->abm_level == ABM_LEVEL_IMMEDIATE_DISABLE) {

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

192

dce110_set_abm_immediate_disable(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

211

void dcn21_set_pipe(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

213

struct abm *abm = pipe_ctx->stream_res.abm;

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

214

struct timing_generator *tg = pipe_ctx->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

215

struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

216

struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

225

dce110_set_pipe(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

243

bool dcn21_set_backlight_level(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

246

struct dc_context *dc = pipe_ctx->stream->ctx;

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

247

struct abm *abm = pipe_ctx->stream_res.abm;

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

248

struct timing_generator *tg = pipe_ctx->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

249

struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

260

dce110_set_backlight_level(pipe_ctx, backlight_level_params);

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

293

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

295

if (pipe_ctx->stream == stream &&

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

296

(pipe_ctx->prev_odm_pipe == NULL && pipe_ctx->next_odm_pipe == NULL))

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h

48

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h

52

void dcn21_set_pipe(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h

53

void dcn21_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h

54

bool dcn21_set_backlight_level(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1157

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1179

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1186

pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1209

void dcn30_wait_for_all_pending_updates(const struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1211

struct timing_generator *tg = pipe_ctx->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1225

if (tg->funcs->get_pipe_update_pending && pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

235

struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

237

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

256

static bool dcn30_set_mpc_shaper_3dlut(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

259

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

260

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

261

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

262

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

317

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

321

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

346

if (pipe_ctx->stream_res.opp && pipe_ctx->stream_res.opp->ctx) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

348

hws->funcs.set_blend_lut(pipe_ctx, plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

351

hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

357

void dcn30_program_gamut_remap(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

362

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

363

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

368

if (pipe_ctx->plane_state &&

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

369

pipe_ctx->plane_state->gamut_remap_matrix.enable_remap == true) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

373

pipe_ctx->plane_state->gamut_remap_matrix.matrix[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

376

pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

382

if (pipe_ctx->top_pipe == NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

383

if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

387

pipe_ctx->stream->gamut_remap_matrix.matrix[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

395

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

398

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

399

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

404

if (pipe_ctx->top_pipe == NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

406

ret = dcn30_set_mpc_shaper_3dlut(pipe_ctx, stream);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

410

else if (pipe_ctx->stream->out_transfer_func.type ==

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

606

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i_pipe];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

608

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

611

if (pipe_ctx->plane_state == wb_info.writeback_source_plane) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

612

wb_info.mpcc_inst = pipe_ctx->plane_res.mpcc_inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

833

void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

835

if (pipe_ctx == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

838

if (dc_is_hdmi_signal(pipe_ctx->stream->signal) && pipe_ctx->stream_res.stream_enc != NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

839

pipe_ctx->stream_res.stream_enc->funcs->set_avmute(

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

840

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

844

if (enable && pipe_ctx->stream_res.tg->funcs->is_tg_enabled(pipe_ctx->stream_res.tg)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

845

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

846

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

847

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

848

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

849

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

854

void dcn30_update_info_frame(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

859

ASSERT(pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

861

if (pipe_ctx->stream_res.stream_enc == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

864

is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

865

is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

871

pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

872

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

873

&pipe_ctx->stream_res.encoder_info_frame);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

875

if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

876

pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num(

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

877

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

878

&pipe_ctx->stream_res.encoder_info_frame);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

880

pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

881

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

882

&pipe_ctx->stream_res.encoder_info_frame);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

886

void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

888

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

889

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

891

struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

897

if (pipe_ctx->stream->dmdata_address.quad_part != 0) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

898

pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

100

void dcn30_wait_for_all_pending_updates(const struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

59

bool dcn30_set_blend_lut(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

63

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

66

void dcn30_program_gamut_remap(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

69

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

71

void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

72

void dcn30_update_info_frame(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

73

void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

86

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h

94

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

376

void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

381

ASSERT(pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

383

if (pipe_ctx->stream_res.stream_enc == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

386

is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

387

is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

393

pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

394

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

395

&pipe_ctx->stream_res.encoder_info_frame);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

396

else if (pipe_ctx->stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

397

if (pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets_sdp_line_num)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

398

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets_sdp_line_num(

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

399

pipe_ctx->stream_res.hpo_dp_stream_enc,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

400

&pipe_ctx->stream_res.encoder_info_frame);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

402

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets(

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

403

pipe_ctx->stream_res.hpo_dp_stream_enc,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

404

&pipe_ctx->stream_res.encoder_info_frame);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

407

if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

408

pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num(

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

409

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

410

&pipe_ctx->stream_res.encoder_info_frame);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

412

pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

413

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

414

&pipe_ctx->stream_res.encoder_info_frame);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

511

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

517

if (pipe_ctx->stream_res.stream_enc == NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

518

pipe_ctx->stream = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

521

ASSERT(!pipe_ctx->top_pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

523

dc->hwss.set_abm_immediate_disable(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

525

link = pipe_ctx->stream->link;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

530

if ((!pipe_ctx->stream->dpms_off || link->link_status.link_active) &&

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

532

dc->hwss.blank_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

537

pipe_ctx->stream_res.tg->funcs->set_dsc_config(

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

538

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

541

pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

543

pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

544

if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

545

pipe_ctx->stream_res.tg->funcs->set_odm_bypass(

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

546

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

552

if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

555

if (pipe_ctx->top_pipe == NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

557

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

559

link_hwss->disable_link_output(link, &pipe_ctx->link_res, pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

564

set_drr_and_clear_adjust_pending(pipe_ctx, pipe_ctx->stream, NULL);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

572

if (!pipe_ctx->stream->dpms_off || link->link_status.link_active)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

573

dc->link_srv->set_dpms_off(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

574

else if (pipe_ctx->stream_res.audio)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

575

dc->hwss.disable_audio_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

581

if (pipe_ctx->stream->timing.flags.DSC) {

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

582

if ((pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

585

(dc_is_dp_signal(pipe_ctx->stream->signal) ||

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

586

dc_is_virtual_signal(pipe_ctx->stream->signal)))

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

587

dc->link_srv->set_dsc_enable(pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

591

if (pipe_ctx->stream_res.audio) {

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

593

pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

600

pipe_ctx->stream_res.audio, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

601

pipe_ctx->stream_res.audio = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

606

pipe_ctx->stream = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

608

pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

620

struct pipe_ctx *pipe_ctx_old =

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

621

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

622

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

630

if (!pipe_ctx->stream ||

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

631

pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

664

void dcn31_set_static_screen_control(struct pipe_ctx **pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

678

pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(pipe_ctx[i]->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

705

bool dcn31_set_backlight_level(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

708

struct dc_context *dc = pipe_ctx->stream->ctx;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

709

struct abm *abm = pipe_ctx->stream_res.abm;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

710

struct timing_generator *tg = pipe_ctx->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

711

struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

44

void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

54

bool dcn31_set_backlight_level(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

61

void dcn31_set_static_screen_control(struct pipe_ctx **pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

107

dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

114

dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

115

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

128

DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

129

pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

135

pipe_ctx->stream_res.tg->funcs->set_dsc_config(

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

136

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

140

dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

141

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

150

static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

153

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

156

for (odm_pipe = pipe_ctx; odm_pipe->prev_odm_pipe; odm_pipe = odm_pipe->prev_odm_pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

173

void dcn314_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

175

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

178

int odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

179

int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

183

opp_cnt = get_odm_config(pipe_ctx, opp_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

186

pipe_ctx->stream_res.tg->funcs->set_odm_combine(

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

187

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

191

pipe_ctx->stream_res.tg->funcs->set_odm_bypass(

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

192

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

204

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

210

if (pipe_ctx->stream_res.dsc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

211

struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

213

update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

216

if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe &&

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

328

unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

330

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

334

two_pix_per_container = pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

335

odm_combine_factor = get_odm_config(pipe_ctx, NULL);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

337

if (stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

340

} else if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) || dc_is_dvi_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

346

} else if (dc_is_dp_signal(pipe_ctx->stream->signal) || dc_is_virtual_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

370

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

374

pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

376

if (pipe_ctx) {

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

378

hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

380

pipe_ctx->pixel_rate_divider.div_factor1 = k1_div;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

381

pipe_ctx->pixel_rate_divider.div_factor2 = k2_div;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

385

static bool dcn314_is_pipe_dig_fifo_on(struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

402

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

407

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

409

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

430

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

432

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

439

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

484

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

489

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

490

if (pipe_ctx->stream && pipe_ctx->stream->link == link && pipe_ctx->top_pipe == NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

491

pipe_ctx->clock_source->funcs->program_pix_clk(

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

492

pipe_ctx->clock_source,

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

493

&pipe_ctx->stream_res.pix_clk_params,

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

495

&pipe_ctx->link_config.dp_link_settings),

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

496

&pipe_ctx->pll_settings);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

72

static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

74

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

75

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

76

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

80

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

90

DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

97

DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h

34

void dcn314_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h

40

unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1020

void dcn32_update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1022

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1023

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1024

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1025

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1041

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1051

DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1058

DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1064

dsc_cfg.pic_width = (stream->timing.h_addressable + pipe_ctx->dsc_padding_params.dsc_hactive_padding +

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1069

dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1078

dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1079

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1092

DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1093

pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1099

pipe_ctx->stream_res.tg->funcs->set_dsc_config(

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1100

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1104

dsc->funcs->dsc_disconnect(pipe_ctx->stream_res.dsc);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1105

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1116

static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1119

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1122

for (odm_pipe = pipe_ctx; odm_pipe->prev_odm_pipe; odm_pipe = odm_pipe->prev_odm_pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1139

void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1141

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1144

int odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1145

int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1147

opp_cnt = get_odm_config(pipe_ctx, opp_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1150

pipe_ctx->stream_res.tg->funcs->set_odm_combine(

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1151

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1155

pipe_ctx->stream_res.tg->funcs->set_odm_bypass(

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1156

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1158

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1164

pipe_ctx->stream->timing.pixel_encoding,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1168

if (pipe_ctx->stream_res.dsc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1169

struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1171

dcn32_update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1174

if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe &&

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1183

if (!resource_is_pipe_type(pipe_ctx, DPP_PIPE))

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1188

dc->hwseq->funcs.blank_pixel_data(dc, pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1191

unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1193

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1198

two_pix_per_container = pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1199

odm_combine_factor = get_odm_config(pipe_ctx, NULL);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1201

if (stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1218

hws->funcs.is_dp_dig_pixel_rate_div_policy(pipe_ctx)))

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1235

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1239

pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1241

if (pipe_ctx) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1244

hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1246

pipe_ctx->pixel_rate_divider.div_factor1 = k1_div;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1247

pipe_ctx->pixel_rate_divider.div_factor2 = k2_div;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1254

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1260

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1263

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1282

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1284

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1291

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1310

void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1314

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1317

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1320

params.pix_per_cycle = pipe_ctx->stream_res.pix_clk_params.dio_se_pix_per_cycle;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1322

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1326

params.timing = pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1330

if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1332

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank(

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1333

pipe_ctx->stream_res.hpo_dp_stream_enc,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1334

pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1335

} else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1336

if (pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing) ||

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1341

if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1342

pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1343

pipe_ctx->stream_res.stream_enc, params.pix_per_cycle > 1);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1344

pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1351

bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1353

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1355

if (!is_h_timing_divisible_by_2(pipe_ctx->stream))

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1358

if (dc_is_dp_signal(pipe_ctx->stream->signal) && !dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) &&

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1382

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1387

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1388

if (resource_is_pipe_type(pipe_ctx, OPP_HEAD) && pipe_ctx->stream->link == link) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1389

pipe_ctx->clock_source->funcs->program_pix_clk(

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1390

pipe_ctx->clock_source,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1391

&pipe_ctx->stream_res.pix_clk_params,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1393

&pipe_ctx->link_config.dp_link_settings),

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1394

&pipe_ctx->pll_settings);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1438

struct pipe_ctx *phantom_pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1444

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1469

void dcn32_apply_update_flags_for_phantom(struct pipe_ctx *phantom_pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1550

struct pipe_ctx *pipe_ctx_old =

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1551

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1552

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1563

if (!pipe_ctx->stream || pipe_need_reprogram(pipe_ctx_old, pipe_ctx) ||

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1564

(pipe_ctx->stream && dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1584

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1585

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1602

struct pipe_ctx *pipe_ctx_old =

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1603

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1604

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1606

if (pipe_ctx->stream == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1609

if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1612

if (pipe_ctx->stream == pipe_ctx_old->stream &&

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1613

pipe_ctx->stream->link->link_state_valid) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1617

if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1620

if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1625

pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1728

const struct pipe_ctx *cur_pipe,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1729

const struct pipe_ctx *new_pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1748

const struct pipe_ctx *cur_pipe, *new_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1752

cur_pipe = &cur_ctx->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1753

new_pipe = &new_ctx->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1830

struct pipe_ctx *pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1834

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

239

struct pipe_ctx *pipe = &ctx->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

361

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

363

if (pipe_ctx->stream && dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_MAIN) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

382

struct pipe_ctx *top_pipe_to_program,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

388

struct pipe_ctx *pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

392

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

413

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

447

struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

449

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

450

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

451

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

452

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

484

struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

486

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

487

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

488

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

530

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

535

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

561

if (pipe_ctx->stream_res.opp &&

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

562

pipe_ctx->stream_res.opp->ctx &&

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

564

result = hws->funcs.set_mcm_luts(pipe_ctx, plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

570

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

573

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

574

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

579

if (resource_is_pipe_type(pipe_ctx, OPP_HEAD)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

581

ret = dcn32_set_mpc_shaper_3dlut(pipe_ctx, stream);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

585

else if (pipe_ctx->stream->out_transfer_func.type ==

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

616

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

635

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

636

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

681

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

741

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

102

struct pipe_ctx *phantom_pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

104

void dcn32_apply_update_flags_for_phantom(struct pipe_ctx *phantom_pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

50

bool dcn32_set_mcm_luts(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

54

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

58

struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

61

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

72

void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

74

void dcn32_update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

76

unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

84

struct pipe_ctx *top_pipe_to_program,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

89

void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

92

bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1032

struct pipe_ctx *cur_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1033

struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1121

struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1398

void dcn35_set_drr(struct pipe_ctx **pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1418

struct timing_generator *tg = pipe_ctx[i]->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1421

if (pipe_ctx[i]->stream && pipe_ctx[i]->stream->ctx->dc->debug.static_screen_wait_frames) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1422

struct dc_crtc_timing *timing = &pipe_ctx[i]->stream->timing;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1423

struct dc *dc = pipe_ctx[i]->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1432

set_drr_and_clear_adjust_pending(pipe_ctx[i], pipe_ctx[i]->stream, &params);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1440

void dcn35_set_static_screen_control(struct pipe_ctx **pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1453

pipe_ctx[i]->stream_res.tg->funcs->

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1454

set_static_screen_control(pipe_ctx[i]->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1458

void dcn35_set_long_vblank(struct pipe_ctx **pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1468

if (!pipe_ctx[i])

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1471

if (pipe_ctx[i]->stream) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1472

struct dc_crtc_timing *timing = &pipe_ctx[i]->stream->timing;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1479

if ((pipe_ctx[i]->stream_res.tg != NULL) && pipe_ctx[i]->stream_res.tg->funcs &&

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1480

pipe_ctx[i]->stream_res.tg->funcs->set_long_vtotal)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1481

pipe_ctx[i]->stream_res.tg->funcs->set_long_vtotal(pipe_ctx[i]->stream_res.tg, &params);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1486

static bool should_avoid_empty_tu(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1498

struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1499

struct dc_link_settings *link_settings = &pipe_ctx->link_config.dp_link_settings;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1500

const struct dc *dc = pipe_ctx->stream->link->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1502

if (pipe_ctx->link_config.dp_tunnel_settings.should_enable_dp_tunneling == false)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1506

if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1541

bool dcn35_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1543

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1545

if (!is_h_timing_divisible_by_2(pipe_ctx->stream))

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1548

if (should_avoid_empty_tu(pipe_ctx))

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1551

if (dc_is_dp_signal(pipe_ctx->stream->signal) && !dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) &&

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1592

void dcn35_abort_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1620

void dcn35_begin_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1623

const struct pipe_ctx *top_pipe = resource_get_otg_master(pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1643

void dcn35_commit_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1647

const struct pipe_ctx *top_pipe = resource_get_otg_master(pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1672

void dcn35_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1675

const struct pipe_ctx *top_pipe = resource_get_otg_master(pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1726

void dcn35_program_cursor_offload_now(struct dc *dc, const struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1734

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1738

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1739

if (pipe_ctx->stream && pipe_ctx->stream->link == link && pipe_ctx->top_pipe == NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1740

pipe_ctx->clock_source->funcs->program_pix_clk(

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1741

pipe_ctx->clock_source,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1742

&pipe_ctx->stream_res.pix_clk_params,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1744

&pipe_ctx->pll_settings);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

327

static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

329

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

330

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

331

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

337

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

347

DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

354

DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

363

dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

370

dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

371

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

384

DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

385

pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

391

pipe_ctx->stream_res.tg->funcs->set_dsc_config(

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

392

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

396

dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

397

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

406

static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

409

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

412

for (odm_pipe = pipe_ctx; odm_pipe->prev_odm_pipe; odm_pipe = odm_pipe->prev_odm_pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

429

void dcn35_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

431

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

434

int odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

435

int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

439

opp_cnt = get_odm_config(pipe_ctx, opp_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

442

pipe_ctx->stream_res.tg->funcs->set_odm_combine(

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

443

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

447

pipe_ctx->stream_res.tg->funcs->set_odm_bypass(

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

448

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

460

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

466

if (pipe_ctx->stream_res.dsc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

467

struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

469

update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

472

if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe &&

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

639

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

645

if (pipe_ctx->stream != NULL && can_apply_seamless_boot)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

665

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

669

if (pipe_ctx->stream != NULL && can_apply_seamless_boot)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

682

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

685

if (pipe_ctx->stream != NULL && can_apply_seamless_boot)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

696

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

703

pipe_ctx->stream != NULL &&

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

704

pipe_ctx->stream_res.tg->funcs->is_tg_enabled(

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

705

pipe_ctx->stream_res.tg)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

717

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

722

pipe_ctx->stream_res.tg = tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

723

pipe_ctx->pipe_idx = i;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

725

pipe_ctx->plane_res.hubp = hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

726

pipe_ctx->plane_res.dpp = dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

727

pipe_ctx->plane_res.mpcc_inst = dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

734

dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

735

pipe_ctx->stream_res.opp = dc->res_pool->opps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

737

hws->funcs.plane_atomic_disconnect(dc, context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

742

dc->hwss.disable_plane(dc, context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

744

pipe_ctx->stream_res.tg = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

745

pipe_ctx->plane_res.hubp = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

816

void dcn35_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

819

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

822

pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

825

pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

829

pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

830

pipe_ctx->stream_res.opp,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

842

pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

846

if (!pipe_ctx->top_pipe

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

847

&& pipe_ctx->plane_state

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

848

&& pipe_ctx->plane_state->flip_int_enabled

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

849

&& pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

850

pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

856

void dcn35_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

858

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

859

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

862

dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

867

if (pipe_ctx->stream_res.gsl_group != 0)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

868

dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

873

dc->hwss.set_flip_control_gsl(pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

884

pipe_ctx->stream = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

885

memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

886

memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

887

pipe_ctx->top_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

888

pipe_ctx->bottom_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

889

pipe_ctx->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

894

void dcn35_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

897

bool is_phantom = dc_state_get_pipe_subvp_type(state, pipe_ctx) == SUBVP_PHANTOM;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

898

struct timing_generator *tg = is_phantom ? pipe_ctx->stream_res.tg : NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

902

if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

906

hws->funcs.plane_atomic_disable(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

915

pipe_ctx->pipe_idx);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

943

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

948

if (!pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

951

if (pipe_ctx->plane_res.hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

952

update_state->pg_pipe_res_update[PG_HUBP][pipe_ctx->plane_res.hubp->inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

954

if (pipe_ctx->plane_res.dpp && pipe_ctx->plane_res.hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

955

update_state->pg_pipe_res_update[PG_DPP][pipe_ctx->plane_res.hubp->inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

957

if (pipe_ctx->plane_res.dpp || pipe_ctx->stream_res.opp)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

958

update_state->pg_pipe_res_update[PG_MPCC][pipe_ctx->plane_res.mpcc_inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

960

if (pipe_ctx->stream_res.dsc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

961

update_state->pg_pipe_res_update[PG_DSC][pipe_ctx->stream_res.dsc->inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

963

update_state->pg_pipe_res_update[PG_HUBP][pipe_ctx->stream_res.dsc->inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

964

update_state->pg_pipe_res_update[PG_DPP][pipe_ctx->stream_res.dsc->inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

967

if (!pipe_ctx->top_pipe && pipe_ctx->plane_res.hubp &&

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

968

pipe_ctx->plane_res.hubp->inst != pipe_ctx->stream_res.dsc->inst) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

977

if (pipe_ctx->stream_res.opp)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

978

update_state->pg_pipe_res_update[PG_OPP][pipe_ctx->stream_res.opp->inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

980

if (pipe_ctx->stream_res.hpo_dp_stream_enc)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

981

update_state->pg_pipe_res_update[PG_DPSTREAM][pipe_ctx->stream_res.hpo_dp_stream_enc->inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

100

bool dcn35_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

104

void dcn35_abort_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

105

void dcn35_begin_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

106

void dcn35_commit_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

107

void dcn35_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

110

void dcn35_program_cursor_offload_now(struct dc *dc, const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

34

void dcn35_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

61

void dcn35_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

62

void dcn35_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

64

void dcn35_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

91

void dcn35_set_drr(struct pipe_ctx **pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

94

void dcn35_set_static_screen_control(struct pipe_ctx **pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

97

void dcn35_set_long_vblank(struct pipe_ctx **pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

100

ASSERT(pipe_ctx->plane_state->mcm_location == MPCC_MOVABLE_CM_LOCATION_BEFORE);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1000

if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1002

dc->hwss.program_dmdata_engine(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1005

dc->hwss.update_info_frame(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1007

if (dc_is_dp_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1032

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1036

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1037

if (pipe_ctx->stream && pipe_ctx->stream->link == link && pipe_ctx->top_pipe == NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1038

pipe_ctx->clock_source->funcs->program_pix_clk(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1039

pipe_ctx->clock_source,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1040

&pipe_ctx->stream_res.pix_clk_params,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1042

&pipe_ctx->pll_settings);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

107

if (pipe_ctx->plane_state &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

108

pipe_ctx->plane_state->gamut_remap_matrix.enable_remap == true) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1081

void dcn401_set_cursor_position(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1083

struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1084

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1085

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1087

.pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1088

.ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1089

.viewport = pipe_ctx->plane_res.scl_data.viewport,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1090

.recout = pipe_ctx->plane_res.scl_data.recout,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1091

.h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1092

.v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1093

.rotation = pipe_ctx->plane_state->rotation,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1094

.mirror = pipe_ctx->plane_state->horizontal_mirror,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1095

.stream = pipe_ctx->stream

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1098

bool odm_combine_on = (pipe_ctx->next_odm_pipe != NULL) ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1099

(pipe_ctx->prev_odm_pipe != NULL);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1101

struct pipe_ctx *prev_odm_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1110

if ((pipe_ctx->top_pipe != NULL) || (pipe_ctx->bottom_pipe != NULL)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1111

if ((pipe_ctx->plane_state->src_rect.width != pipe_ctx->plane_res.scl_data.viewport.width) ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1112

(pipe_ctx->plane_state->src_rect.height != pipe_ctx->plane_res.scl_data.viewport.height)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

112

pipe_ctx->plane_state->gamut_remap_matrix.matrix[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1137

x_pos = pipe_ctx->stream->dst.x + x_pos * pipe_ctx->stream->dst.width /

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1138

pipe_ctx->stream->src.width;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1139

y_pos = pipe_ctx->stream->dst.y + y_pos * pipe_ctx->stream->dst.height /

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1140

pipe_ctx->stream->src.height;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1154

x_pos += pipe_ctx->plane_state->src_rect.x;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1155

y_pos += pipe_ctx->plane_state->src_rect.y;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1162

prev_odm_pipe = pipe_ctx->prev_odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1193

pipe_ctx->top_pipe &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1194

(pipe_ctx == pipe_ctx->top_pipe->bottom_pipe)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1196

bottom_pipe_x_pos = x_pos - pipe_ctx->plane_res.scl_data.recout.x;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1198

x_pos = pipe_ctx->plane_res.scl_data.recout.x;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1208

if (pos_cpy.enable && resource_can_pipe_disable_cursor(pipe_ctx))

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1263

struct pipe_ctx *pipe = &ctx->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

128

if (pipe_ctx->top_pipe == NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

129

if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

133

pipe_ctx->stream->gamut_remap_matrix.matrix[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1357

const struct pipe_ctx *top_pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1360

const struct pipe_ctx *pipe_ctx = top_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1363

while (pipe_ctx != NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1364

if (pipe_ctx->plane_state &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1365

pipe_ctx->plane_state->dcc.enable &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1366

pipe_ctx->plane_state->flip_immediate &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1367

pipe_ctx->plane_state->update_flags.bits.addr_update) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1373

pipe_ctx = pipe_ctx->bottom_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1478

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1480

if (pipe_ctx->stream && pipe_ctx->plane_res.hubp->funcs->program_extended_blank

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1481

&& pipe_ctx->stream->adjust.v_total_min == pipe_ctx->stream->adjust.v_total_max

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1482

&& pipe_ctx->stream->adjust.v_total_max > pipe_ctx->stream->timing.v_total)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1483

pipe_ctx->plane_res.hubp->funcs->program_extended_blank(pipe_ctx->plane_res.hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1484

pipe_ctx->dlg_regs.min_dst_y_next_start);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1539

struct pipe_ctx *otg_master)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1542

struct pipe_ctx *old_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1543

struct pipe_ctx *new_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1544

struct pipe_ctx *old_opp_heads[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1545

struct pipe_ctx *old_otg_master;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1548

old_otg_master = &dc->current_state->res_ctx.pipe_ctx[otg_master->pipe_idx];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1569

new_pipe = &context->res_ctx.pipe_ctx[old_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1578

struct pipe_ctx *otg_master)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1580

struct pipe_ctx *opp_heads[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1623

struct pipe_ctx *otg_master, struct block_sequence_state *seq_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1625

struct pipe_ctx *old_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1626

struct pipe_ctx *new_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1627

struct pipe_ctx *old_opp_heads[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1628

struct pipe_ctx *old_otg_master;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1632

old_otg_master = &dc->current_state->res_ctx.pipe_ctx[otg_master->pipe_idx];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1645

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1703

new_pipe = &context->res_ctx.pipe_ctx[old_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1715

struct pipe_ctx *otg_master, struct block_sequence_state *seq_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1717

struct pipe_ctx *opp_heads[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1759

void dcn401_unblank_stream(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1763

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1768

params.opp_cnt = resource_get_odm_slice_count(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1770

params.timing = pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1772

params.pix_per_cycle = pipe_ctx->stream_res.pix_clk_params.dio_se_pix_per_cycle;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1774

if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1775

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1776

pipe_ctx->stream_res.hpo_dp_stream_enc,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1777

pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1778

} else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1779

pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1816

void dcn401_wait_for_det_buffer_update_under_otg_master(struct dc *dc, struct dc_state *context, struct pipe_ctx *otg_master)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1818

struct pipe_ctx *opp_heads[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1819

struct pipe_ctx *dpp_pipes[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1836

struct pipe_ctx *dpp_pipe = dpp_pipes[dpp_idx];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1853

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1858

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1870

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1880

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1892

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1905

void dcn401_perform_3dlut_wa_unlock(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1913

struct pipe_ctx *wa_pipes[MAX_PIPES] = { NULL };

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1914

struct pipe_ctx *odm_pipe, *mpc_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1917

for (odm_pipe = pipe_ctx; odm_pipe != NULL; odm_pipe = odm_pipe->next_odm_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1929

if (pipe_ctx->stream_res.tg->funcs->set_vupdate_keepout)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1930

pipe_ctx->stream_res.tg->funcs->set_vupdate_keepout(pipe_ctx->stream_res.tg, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1937

pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1938

if (pipe_ctx->stream_res.tg->funcs->wait_update_lock_status)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1939

pipe_ctx->stream_res.tg->funcs->wait_update_lock_status(pipe_ctx->stream_res.tg, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1946

if (pipe_ctx->stream_res.tg->funcs->set_vupdate_keepout)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1947

pipe_ctx->stream_res.tg->funcs->set_vupdate_keepout(pipe_ctx->stream_res.tg, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1949

pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1965

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1968

struct dc_link *link = pipe_ctx->stream->link;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1969

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1972

if (pipe_ctx->stream_res.stream_enc == NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1973

pipe_ctx->stream = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1983

if (!pipe_ctx->stream->dpms_off || link->link_status.link_active)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1984

dc->link_srv->set_dpms_off(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1985

else if (pipe_ctx->stream_res.audio)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1986

dc->hwss.disable_audio_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1989

if (pipe_ctx->stream_res.audio) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1991

pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1998

pipe_ctx->stream_res.audio, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1999

pipe_ctx->stream_res.audio = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2007

if (pipe_ctx->top_pipe == NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2009

dc->hwss.set_abm_immediate_disable(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2011

pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2013

pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2014

if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2015

pipe_ctx->stream_res.tg->funcs->set_odm_bypass(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2016

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2018

set_drr_and_clear_adjust_pending(pipe_ctx, pipe_ctx->stream, NULL);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2024

if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2028

&pipe_ctx->link_res, pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2034

dc->res_pool->dccg->funcs->set_dtbclk_p_src(dc->res_pool->dccg, REFCLK, pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2042

pipe_ctx->stream = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2043

pipe_ctx->top_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2044

pipe_ctx->bottom_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2045

pipe_ctx->next_odm_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2046

pipe_ctx->prev_odm_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2048

pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2060

struct pipe_ctx *pipe_ctx_old =

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2061

&dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2062

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2070

if (!pipe_ctx->stream ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2071

pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2084

static unsigned int dcn401_calculate_vready_offset_for_group(struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2086

struct pipe_ctx *other_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2112

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2116

pipe_ctx->stream_res.tg->funcs->program_global_sync(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2117

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2118

dcn401_calculate_vready_offset_for_group(pipe_ctx),

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2119

(unsigned int)pipe_ctx->global_sync.dcn4x.vstartup_lines,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2120

(unsigned int)pipe_ctx->global_sync.dcn4x.vupdate_offset_pixels,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2121

(unsigned int)pipe_ctx->global_sync.dcn4x.vupdate_vupdate_width_pixels,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2122

(unsigned int)pipe_ctx->global_sync.dcn4x.pstate_keepout_start_lines);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2124

if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2125

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2127

pipe_ctx->stream_res.tg->funcs->set_vtg_params(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2128

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2131

hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2136

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2142

if (resource_is_pipe_type(pipe_ctx, OTG_MASTER)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2143

if (pipe_ctx->update_flags.bits.enable ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2144

pipe_ctx->update_flags.bits.odm ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2145

pipe_ctx->stream->update_flags.bits.abm_level)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2146

hws->funcs.blank_pixel_data(dc, pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2147

!pipe_ctx->plane_state ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2148

!pipe_ctx->plane_state->visible);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2152

if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2153

&& !pipe_ctx->prev_odm_pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2154

dcn401_program_tg(dc, pipe_ctx, context, hws);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2156

if (pipe_ctx->update_flags.bits.odm)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2157

hws->funcs.update_odm(dc, context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2159

if (pipe_ctx->update_flags.bits.enable) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2161

hws->funcs.enable_plane(dc, pipe_ctx, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2163

dc->hwss.enable_plane(dc, pipe_ctx, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2169

if (pipe_ctx->update_flags.bits.det_size) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2172

dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2175

dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->hubp_regs.det_size);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2178

if (pipe_ctx->plane_state && (pipe_ctx->update_flags.raw ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2179

pipe_ctx->plane_state->update_flags.raw ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2180

pipe_ctx->stream->update_flags.raw))

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2181

dc->hwss.update_dchubp_dpp(dc, pipe_ctx, context);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2183

if (pipe_ctx->plane_state && (pipe_ctx->update_flags.bits.enable ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2184

pipe_ctx->plane_state->update_flags.bits.hdr_mult))

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2185

hws->funcs.set_hdr_multiplier(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2187

if (pipe_ctx->plane_state &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2188

(pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2189

pipe_ctx->plane_state->update_flags.bits.gamma_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2190

pipe_ctx->plane_state->update_flags.bits.lut_3d ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2191

pipe_ctx->update_flags.bits.enable))

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2192

hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2198

if (pipe_ctx->update_flags.bits.enable ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2199

pipe_ctx->update_flags.bits.plane_changed ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2200

pipe_ctx->stream->update_flags.bits.out_tf)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2201

hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2208

if (pipe_ctx->update_flags.bits.enable

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2209

|| pipe_ctx->update_flags.bits.opp_changed) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2211

pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2212

pipe_ctx->stream_res.opp,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2214

pipe_ctx->stream->timing.display_color_depth,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2215

pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2217

pipe_ctx->stream_res.opp->funcs->opp_program_fmt(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2218

pipe_ctx->stream_res.opp,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2219

&pipe_ctx->stream->bit_depth_params,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2220

&pipe_ctx->stream->clamping);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2224

if ((pipe_ctx->plane_state && pipe_ctx->plane_state->visible)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2225

if (pipe_ctx->stream_res.abm) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2226

dc->hwss.set_pipe(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2227

pipe_ctx->stream_res.abm->funcs->set_abm_level(pipe_ctx->stream_res.abm,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2228

pipe_ctx->stream->abm_level);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2232

if (pipe_ctx->update_flags.bits.test_pattern_changed) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2233

struct output_pixel_processor *odm_opp = pipe_ctx->stream_res.opp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2239

pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2240

pipe_ctx->stream_res.test_pattern_params.test_pattern,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2241

pipe_ctx->stream_res.test_pattern_params.color_space,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2242

pipe_ctx->stream_res.test_pattern_params.color_depth,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2244

pipe_ctx->stream_res.test_pattern_params.width,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2245

pipe_ctx->stream_res.test_pattern_params.height,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2246

pipe_ctx->stream_res.test_pattern_params.offset);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2261

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2268

if (resource_is_pipe_type(pipe_ctx, OTG_MASTER)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2269

if (pipe_ctx->update_flags.bits.enable ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2270

pipe_ctx->update_flags.bits.odm ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2271

pipe_ctx->stream->update_flags.bits.abm_level) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2273

dc->hwseq->funcs.blank_pixel_data_sequence(dc, pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2274

!pipe_ctx->plane_state || !pipe_ctx->plane_state->visible,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2280

if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2281

&& !pipe_ctx->prev_odm_pipe) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2284

hwss_add_tg_program_global_sync(seq_state, pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2285

dcn401_calculate_vready_offset_for_group(pipe_ctx),

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2286

(unsigned int)pipe_ctx->global_sync.dcn4x.vstartup_lines,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2287

(unsigned int)pipe_ctx->global_sync.dcn4x.vupdate_offset_pixels,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2288

(unsigned int)pipe_ctx->global_sync.dcn4x.vupdate_vupdate_width_pixels,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2289

(unsigned int)pipe_ctx->global_sync.dcn4x.pstate_keepout_start_lines);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2292

if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2293

hwss_add_tg_wait_for_state(seq_state, pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2296

hwss_add_tg_set_vtg_params(seq_state, pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2300

dcn401_setup_vupdate_interrupt_sequence(dc, pipe_ctx, seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2303

if (pipe_ctx->update_flags.bits.odm) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2305

hws->funcs.update_odm_sequence(dc, context, pipe_ctx, seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2308

if (pipe_ctx->update_flags.bits.enable) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2310

dc->hwss.enable_plane_sequence(dc, pipe_ctx, context, seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2313

if (pipe_ctx->update_flags.bits.det_size) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2316

pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2321

pipe_ctx->plane_res.hubp->inst, pipe_ctx->hubp_regs.det_size);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2325

if (pipe_ctx->plane_state && (pipe_ctx->update_flags.raw ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2326

pipe_ctx->plane_state->update_flags.raw ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2327

pipe_ctx->stream->update_flags.raw)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2330

dc->hwss.update_dchubp_dpp_sequence(dc, pipe_ctx, context, seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2333

if (pipe_ctx->plane_state && (pipe_ctx->update_flags.bits.enable ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2334

pipe_ctx->plane_state->update_flags.bits.hdr_mult)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2336

hws->funcs.set_hdr_multiplier_sequence(pipe_ctx, seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2339

if (pipe_ctx->plane_state &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2340

(pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2341

pipe_ctx->plane_state->update_flags.bits.gamma_change ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2342

pipe_ctx->plane_state->update_flags.bits.lut_3d ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2343

pipe_ctx->update_flags.bits.enable)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2345

hwss_add_dpp_set_input_transfer_func(seq_state, dc, pipe_ctx, pipe_ctx->plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2352

if (pipe_ctx->update_flags.bits.enable ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2353

pipe_ctx->update_flags.bits.plane_changed ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2354

pipe_ctx->stream->update_flags.bits.out_tf) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2355

hwss_add_dpp_set_output_transfer_func(seq_state, dc, pipe_ctx, pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2363

if (pipe_ctx->update_flags.bits.enable

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2364

|| pipe_ctx->update_flags.bits.opp_changed) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2366

hwss_add_opp_set_dyn_expansion(seq_state, pipe_ctx->stream_res.opp, COLOR_SPACE_YCBCR601,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2367

pipe_ctx->stream->timing.display_color_depth, pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2369

hwss_add_opp_program_fmt(seq_state, pipe_ctx->stream_res.opp,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2370

&pipe_ctx->stream->bit_depth_params, &pipe_ctx->stream->clamping);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2374

if ((pipe_ctx->plane_state && pipe_ctx->plane_state->visible)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2375

if (pipe_ctx->stream_res.abm) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2376

hwss_add_abm_set_pipe(seq_state, dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2378

hwss_add_abm_set_level(seq_state, pipe_ctx->stream_res.abm, pipe_ctx->stream->abm_level);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2382

if (pipe_ctx->update_flags.bits.test_pattern_changed) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2383

struct output_pixel_processor *odm_opp = pipe_ctx->stream_res.opp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2385

hwss_add_opp_program_bit_depth_reduction(seq_state, odm_opp, true, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2389

pipe_ctx->stream_res.test_pattern_params.test_pattern,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2390

pipe_ctx->stream_res.test_pattern_params.color_space,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2391

pipe_ctx->stream_res.test_pattern_params.color_depth,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2394

pipe_ctx->stream_res.test_pattern_params.width,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2395

pipe_ctx->stream_res.test_pattern_params.height,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2396

pipe_ctx->stream_res.test_pattern_params.offset);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2409

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2418

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2432

if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2434

if (context->res_ctx.pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2447

dc->hwss.detect_pipe_changes(dc->current_state, context, &dc->current_state->res_ctx.pipe_ctx[i],

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2448

&context->res_ctx.pipe_ctx[i]);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2454

struct dc_stream_state *stream = dc->current_state->res_ctx.pipe_ctx[i].stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2456

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2458

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable && stream &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2460

struct timing_generator *tg = dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2472

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2473

&& !context->res_ctx.pipe_ctx[i].top_pipe

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2474

&& !context->res_ctx.pipe_ctx[i].prev_odm_pipe

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2475

&& context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2476

hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2480

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2481

|| context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2490

if ((context->res_ctx.pipe_ctx[i].update_flags.bits.disable ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2491

(context->res_ctx.pipe_ctx[i].plane_state &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2492

dc_state_get_pipe_subvp_type(context, &context->res_ctx.pipe_ctx[i]) ==

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2496

dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2499

hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2502

&dc->current_state->res_ctx.pipe_ctx[i]);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2503

DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2508

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2521

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2546

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2579

if (resource_is_pipe_type(&dc->current_state->res_ctx.pipe_ctx[i], OPP_HEAD) &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2580

!resource_is_pipe_type(&context->res_ctx.pipe_ctx[i], OPP_HEAD))

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2582

&dc->current_state->res_ctx.pipe_ctx[i]);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2585

if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2586

dc->hwss.disable_plane(dc, dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i]);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2595

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2609

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2610

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2636

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2716

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2718

if (pipe_ctx->plane_state == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2721

if (pipe_ctx->top_pipe == NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2722

bool blank = !is_pipe_tree_visible(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2724

pipe_ctx->stream_res.tg->funcs->program_global_sync(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2725

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2726

dcn401_calculate_vready_offset_for_group(pipe_ctx),

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2727

(unsigned int)pipe_ctx->global_sync.dcn4x.vstartup_lines,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2728

(unsigned int)pipe_ctx->global_sync.dcn4x.vupdate_offset_pixels,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2729

(unsigned int)pipe_ctx->global_sync.dcn4x.vupdate_vupdate_width_pixels,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2730

(unsigned int)pipe_ctx->global_sync.dcn4x.pstate_keepout_start_lines);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2732

pipe_ctx->stream_res.tg->funcs->set_vtg_params(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2733

pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2735

if (pipe_ctx->prev_odm_pipe == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2736

hws->funcs.blank_pixel_data(dc, pipe_ctx, blank);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2739

hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2742

if (pipe_ctx->plane_res.hubp->funcs->hubp_setup2)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2743

pipe_ctx->plane_res.hubp->funcs->hubp_setup2(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2744

pipe_ctx->plane_res.hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2745

&pipe_ctx->hubp_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2746

&pipe_ctx->global_sync,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2747

&pipe_ctx->stream->timing);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2755

struct pipe_ctx *old_pipe,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2756

struct pipe_ctx *new_pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2986

void dcn401_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2989

const struct pipe_ctx *top_pipe = resource_get_otg_master(pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3084

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3087

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3088

int dpp_id = pipe_ctx->plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3092

struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3106

if (dc_state_get_pipe_subvp_type(state, pipe_ctx) != SUBVP_PHANTOM) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3108

hwss_add_opp_set_mpcc_disconnect_pending(seq_state, opp, pipe_ctx->plane_res.mpcc_inst, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3125

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3130

struct stream_resource *stream_res = &pipe_ctx->stream_res;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3131

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3135

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3146

hwss_add_abm_set_immediate_disable(seq_state, dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3156

odm_pipe = pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3194

hwss_add_abm_set_pipe(seq_state, dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3223

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i_pipe];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3225

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3228

if (pipe_ctx->plane_state == wb_info->writeback_source_plane) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3229

mpcc_inst = pipe_ctx->plane_res.mpcc_inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3354

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3367

if (pipe_ctx->stream_res.gsl_group > 0)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3372

pipe_ctx->stream_res.gsl_group = group_idx;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3394

group_idx = pipe_ctx->stream_res.gsl_group;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3398

pipe_ctx->stream_res.gsl_group = 0;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3421

hwss_add_tg_set_gsl(seq_state, pipe_ctx->stream_res.tg, gsl);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3422

hwss_add_tg_set_gsl_source_select(seq_state, pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3428

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3431

bool is_phantom = dc_state_get_pipe_subvp_type(state, pipe_ctx) == SUBVP_PHANTOM;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3432

struct timing_generator *tg = is_phantom ? pipe_ctx->stream_res.tg : NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3434

if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3439

dc->hwss.wait_for_mpcc_disconnect_sequence(dc, dc->res_pool, pipe_ctx, seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3444

if (pipe_ctx->stream_res.gsl_group != 0)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3445

dcn401_setup_gsl_group_as_lock_sequence(dc, pipe_ctx, false, seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3448

if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs->hubp_update_mall_sel)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3449

hwss_add_hubp_update_mall_sel(seq_state, pipe_ctx->plane_res.hubp, 0, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3452

hwss_add_hubp_set_flip_control_gsl(seq_state, pipe_ctx->plane_res.hubp, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3455

hwss_add_hubp_clk_cntl(seq_state, pipe_ctx->plane_res.hubp, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3458

hwss_add_dpp_dppclk_control(seq_state, pipe_ctx->plane_res.dpp, false, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3462

dc->hwseq->funcs.plane_atomic_power_down_sequence(dc, pipe_ctx->plane_res.dpp,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3463

pipe_ctx->plane_res.hubp, seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3465

pipe_ctx->stream = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3466

memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3467

memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3468

pipe_ctx->top_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3469

pipe_ctx->bottom_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3470

pipe_ctx->prev_odm_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3471

pipe_ctx->next_odm_pipe = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3472

pipe_ctx->plane_state = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3481

struct pipe_ctx *opp_head,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3525

void dcn401_enable_plane_sequence(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3532

if (!pipe_ctx->plane_res.dpp || !pipe_ctx->plane_res.hubp || !pipe_ctx->stream_res.opp)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3540

hwss_add_dpp_root_clock_control(seq_state, hws, pipe_ctx->plane_res.dpp->inst, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3548

hwss_add_dpp_pg_control(seq_state, hws, pipe_ctx->plane_res.dpp->inst, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3552

hwss_add_hubp_pg_control(seq_state, hws, pipe_ctx->plane_res.hubp->inst, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3559

if (pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3560

hwss_add_hubp_clk_cntl(seq_state, pipe_ctx->plane_res.hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3563

if (pipe_ctx->plane_res.hubp->funcs->hubp_init)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3564

hwss_add_hubp_init(seq_state, pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3567

if (pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3568

hwss_add_opp_pipe_clock_control(seq_state, pipe_ctx->stream_res.opp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3571

if (dc->vm_pa_config.valid && pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3572

hwss_add_hubp_set_vm_system_aperture_settings(seq_state, pipe_ctx->plane_res.hubp, 0,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3577

if (!pipe_ctx->top_pipe

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3578

&& pipe_ctx->plane_state

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3579

&& pipe_ctx->plane_state->flip_int_enabled

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3580

&& pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3581

hwss_add_hubp_set_flip_int(seq_state, pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3586

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3591

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3592

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3593

struct dc_plane_state *plane_state = pipe_ctx->plane_state;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3596

enum mall_stream_type pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3602

if (pipe_ctx->update_flags.bits.dppclk)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3606

if (pipe_ctx->update_flags.bits.enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3607

hwss_add_dccg_update_dpp_dto(seq_state, dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3610

if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3611

hwss_add_hubp_vtg_sel(seq_state, hubp, pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3615

hwss_add_hubp_setup2(seq_state, hubp, &pipe_ctx->hubp_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3616

&pipe_ctx->global_sync, &pipe_ctx->stream->timing);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3618

hwss_add_hubp_setup(seq_state, hubp, &pipe_ctx->dlg_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3619

&pipe_ctx->ttu_regs, &pipe_ctx->rq_regs, &pipe_ctx->pipe_dlg_param);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3624

if (pipe_ctx->update_flags.bits.unbounded_req && hubp->funcs->set_unbounded_requesting)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3625

hwss_add_hubp_set_unbounded_requesting(seq_state, hubp, pipe_ctx->unbounded_req);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3628

if (pipe_ctx->update_flags.bits.hubp_interdependent) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3630

hwss_add_hubp_setup_interdependent2(seq_state, hubp, &pipe_ctx->hubp_regs);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3632

hwss_add_hubp_setup_interdependent(seq_state, hubp, &pipe_ctx->dlg_regs, &pipe_ctx->ttu_regs);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3636

if (pipe_ctx->update_flags.bits.enable ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3637

pipe_ctx->update_flags.bits.plane_changed ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3642

hwss_add_dpp_setup_dpp(seq_state, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3652

hwss_add_dpp_program_bias_and_scale(seq_state, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3656

if (pipe_ctx->update_flags.bits.mpcc ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3657

pipe_ctx->update_flags.bits.plane_changed ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3663

hws->funcs.update_mpcc_sequence(dc, pipe_ctx, seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3667

if (pipe_ctx->update_flags.bits.scaler ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3671

pipe_ctx->stream->update_flags.bits.scaling) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3672

pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3673

ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_36BPP);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3674

hwss_add_dpp_set_scaler(seq_state, pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3678

if (pipe_ctx->update_flags.bits.viewport ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3681

(context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3683

&pipe_ctx->plane_res.scl_data.viewport, &pipe_ctx->plane_res.scl_data.viewport_c);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3689

hwss_add_hubp_program_mcache_id(seq_state, hubp, &pipe_ctx->mcache_regs);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3692

if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3693

pipe_ctx->update_flags.bits.scaler || viewport_changed == true) &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3694

pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3696

hwss_add_abort_cursor_offload_update(seq_state, dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3698

hwss_add_set_cursor_attribute(seq_state, dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3701

hwss_add_set_cursor_position(seq_state, dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3705

hwss_add_set_cursor_sdr_white_level(seq_state, dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3709

if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3710

pipe_ctx->update_flags.bits.plane_changed ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3711

pipe_ctx->stream->update_flags.bits.gamut_remap ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3713

pipe_ctx->stream->update_flags.bits.out_csc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3716

hwss_add_dpp_program_gamut_remap(seq_state, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3719

hwss_add_program_output_csc(seq_state, dc, pipe_ctx, pipe_ctx->stream->output_color_space,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3720

pipe_ctx->stream->csc_color_matrix.matrix, hubp->opp_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3724

if (pipe_ctx->update_flags.bits.enable ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3725

pipe_ctx->update_flags.bits.plane_changed ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3726

pipe_ctx->update_flags.bits.opp_changed ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3737

size.surface_size = pipe_ctx->plane_res.scl_data.viewport;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3746

if (pipe_ctx->update_flags.bits.enable ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3747

pipe_ctx->update_flags.bits.plane_changed ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3751

if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) && pipe_mall_type == SUBVP_MAIN) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3753

&pipe_ctx->plane_state->address, pipe_ctx->subvp_index);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3757

hwss_add_hubp_update_plane_addr(seq_state, dc, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3761

if (pipe_ctx->update_flags.bits.enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3770

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3773

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3779

struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3781

if (!hubp || !pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3784

per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3791

blnd_cfg.pre_multiplied_alpha = pipe_ctx->plane_state->pre_multiplied_alpha;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3792

if (pipe_ctx->plane_state->global_alpha) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3794

blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

380

static void dcn401_get_mcm_lut_xable_from_pipe_ctx(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3803

if (pipe_ctx->plane_state->global_alpha)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3804

blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3814

if (pipe_ctx->plane_state->format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3821

if (!pipe_ctx->plane_state->update_flags.bits.full_update &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3822

!pipe_ctx->update_flags.bits.mpcc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3828

hwss_add_mpc_update_visual_confirm(seq_state, dc, pipe_ctx, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3848

hwss_add_mpc_update_visual_confirm(seq_state, dc, pipe_ctx, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3851

hubp->opp_id = pipe_ctx->stream_res.opp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3870

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3878

if (!pipe_ctx->stream_res.opp)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

388

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3882

if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3885

if (pipe_ctx->stream_res.tg &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3886

pipe_ctx->stream_res.tg->funcs->is_tg_enabled(pipe_ctx->stream_res.tg)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3889

pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3899

void dcn401_setup_vupdate_interrupt_sequence(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

390

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3902

struct timing_generator *tg = pipe_ctx->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3903

int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3912

void dcn401_set_hdr_multiplier_sequence(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3915

struct fixed31_32 multiplier = pipe_ctx->plane_state->hdr_mult;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

392

shaper_3dlut_setting = pipe_ctx->plane_state->mcm_shaper_3dlut_setting;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3926

hwss_add_dpp_set_hdr_multiplier(seq_state, pipe_ctx->plane_res.dpp, hw_mult);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

393

lut1d_enable = pipe_ctx->plane_state->mcm_lut1d_enable;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3940

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

395

pipe_ctx->plane_state->mcm_location = MPCC_MOVABLE_CM_LOCATION_BEFORE;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3981

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4016

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4018

if (pipe_ctx != NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4019

hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4030

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4032

if (pipe_ctx != NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4033

hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4041

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4043

if (pipe_ctx != NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4044

hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4055

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4057

if (pipe_ctx != NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4058

hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

414

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

418

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

419

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

436

dcn401_get_mcm_lut_xable_from_pipe_ctx(dc, pipe_ctx, &shaper_xable, &lut3d_xable, &lut1d_xable);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

610

void dcn401_trigger_3dlut_dma_load(struct dc *dc, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

612

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

619

bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

622

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

623

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

624

struct dc *dc = pipe_ctx->stream_res.opp->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

631

dcn401_populate_mcm_luts(dc, pipe_ctx, plane_state->mcm_luts, plane_state->lut_bank_a);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

636

pipe_ctx->plane_state->mcm_location = MPCC_MOVABLE_CM_LOCATION_BEFORE;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

673

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

676

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

677

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

682

if (resource_is_pipe_type(pipe_ctx, OPP_HEAD)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

684

ret = dcn32_set_mpc_shaper_3dlut(pipe_ctx, stream);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

688

else if (pipe_ctx->stream->out_transfer_func.type ==

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

706

void dcn401_calculate_dccg_tmds_div_value(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

709

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

726

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

732

struct pipe_ctx *opp_heads[MAX_PIPES],

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

737

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

741

dcn401_calculate_dccg_tmds_div_value(pipe_ctx, tmds_div);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

743

*opp_cnt = resource_get_opp_heads_for_otg_master(pipe_ctx, &context->res_ctx, opp_heads);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

766

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

771

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

776

struct pipe_ctx *opp_heads[MAX_PIPES] = {0};

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

785

if (!resource_is_pipe_type(pipe_ctx, OTG_MASTER))

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

788

enable_stream_timing_calc(pipe_ctx, context, dc, &tmds_div, opp_inst,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

793

dc->res_pool->dccg, pipe_ctx->stream_res.tg->inst,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

800

odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

801

last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

802

pipe_ctx->stream_res.tg->funcs->set_odm_combine(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

803

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

811

dc->res_pool->dccg->funcs->set_dtbclk_p_src(dc->res_pool->dccg, DPREFCLK, pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

818

pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

820

if (false == pipe_ctx->clock_source->funcs->program_pix_clk(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

821

pipe_ctx->clock_source,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

822

&pipe_ctx->stream_res.pix_clk_params,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

823

dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings),

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

824

&pipe_ctx->pll_settings)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

830

dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

834

patched_crtc_timing.h_addressable = patched_crtc_timing.h_addressable + pipe_ctx->dsc_padding_params.dsc_hactive_padding;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

835

patched_crtc_timing.h_total = patched_crtc_timing.h_total + pipe_ctx->dsc_padding_params.dsc_htotal_padding;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

836

patched_crtc_timing.pix_clk_100hz = pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

839

pipe_ctx->stream_res.tg->funcs->program_timing(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

840

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

842

(unsigned int)pipe_ctx->global_sync.dcn4x.vready_offset_pixels,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

843

(unsigned int)pipe_ctx->global_sync.dcn4x.vstartup_lines,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

844

(unsigned int)pipe_ctx->global_sync.dcn4x.vupdate_offset_pixels,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

845

(unsigned int)pipe_ctx->global_sync.dcn4x.vupdate_vupdate_width_pixels,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

846

(unsigned int)pipe_ctx->global_sync.dcn4x.pstate_keepout_start_lines,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

847

pipe_ctx->stream->signal,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

860

pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

861

pipe_ctx->stream_res.opp,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

864

hws->funcs.blank_pixel_data(dc, pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

867

if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

872

hws->funcs.wait_for_blank_complete(pipe_ctx->stream_res.opp);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

873

set_drr_and_clear_adjust_pending(pipe_ctx, stream, &params);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

879

if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

880

pipe_ctx->stream_res.tg->funcs->set_static_screen_control(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

881

pipe_ctx->stream_res.tg, event_triggers, 2);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

891

if (dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

892

if (pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

893

pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable(pipe_ctx->stream_res.tg);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

91

void dcn401_program_gamut_remap(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

918

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

925

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

926

struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

928

pipe_ctx->stream->link->cur_link_settings.lane_count;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

931

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

932

*dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

933

*phyd32clk = get_phyd32clk_src(pipe_ctx->stream->link);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

936

if (dc_is_tmds_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

937

dcn401_calculate_dccg_tmds_div_value(pipe_ctx, tmds_div);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

95

unsigned int mpcc_id = pipe_ctx->plane_res.mpcc_inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

955

void dcn401_enable_stream(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

958

struct timing_generator *tg = pipe_ctx->stream_res.tg;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

959

struct dc_link *link = pipe_ctx->stream->link;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

96

struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

960

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

961

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

967

struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

968

struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

973

dcn401_enable_stream_calc(pipe_ctx, &dp_hpo_inst, &phyd32clk,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

976

if (dc_is_dp_signal(pipe_ctx->stream->signal) || dc_is_virtual_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

977

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

99

if (pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

993

pipe_ctx->stream_res.tg->inst,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

998

link_hwss->setup_stream_encoder(pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

101

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

105

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

108

void dcn401_perform_3dlut_wa_unlock(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

115

struct pipe_ctx *old_pipe,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

116

struct pipe_ctx *new_pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

126

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

130

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

134

void dcn401_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

162

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

169

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

174

struct pipe_ctx *opp_head,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

179

void dcn401_enable_plane_sequence(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

184

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

189

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

195

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

198

void dcn401_setup_vupdate_interrupt_sequence(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

201

void dcn401_set_hdr_multiplier_sequence(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

35

void dcn401_program_gamut_remap(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

39

bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

42

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

45

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

46

void dcn401_calculate_dccg_tmds_div_value(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

49

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

52

void dcn401_enable_stream(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

54

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

63

void dcn401_set_cursor_position(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

68

const struct pipe_ctx *top_pipe_to_program);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

82

void dcn401_unblank_stream(struct pipe_ctx *pipe_ctx, struct dc_link_settings *link_settings);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

85

struct pipe_ctx *otg_master);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

87

struct pipe_ctx *otg_master, struct block_sequence_state *seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

89

void dcn401_wait_for_det_buffer_update_under_otg_master(struct dc *dc, struct dc_state *context, struct pipe_ctx *otg_master);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

94

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1007

void (*disable_plane)(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1008

void (*disable_plane_sequence)(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1010

void (*disable_pixel_data)(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1021

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1026

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1029

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1035

struct pipe_ctx *pipe_ctx, bool enableTripleBuffer);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1036

void (*update_pending_status)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1038

void (*clear_surface_dcc_and_tiling)(struct pipe_ctx *pipe_ctx, struct dc_plane_state *plane_state, bool clear_tiling);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1042

struct pipe_ctx *pipe, bool lock);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1045

void (*set_flip_control_gsl)(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1047

void (*cursor_lock)(struct dc *dc, struct pipe_ctx *pipe, bool lock);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

105

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1050

void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1052

int (*get_vupdate_offset_from_vsync)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1055

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1059

int group_size, struct pipe_ctx *grouped_pipes[]);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1063

struct pipe_ctx *grouped_pipes[]);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1066

struct pipe_ctx *grouped_pipes[]);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1068

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1069

void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1071

void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1076

void (*enable_stream)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1077

void (*disable_stream)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1078

void (*blank_stream)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1079

void (*unblank_stream)(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1088

void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

109

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1090

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1093

void (*update_info_frame)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1094

void (*set_dmdata_attributes)(struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1095

void (*program_dmdata_engine)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1096

bool (*dmdata_status_done)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1099

void (*set_cursor_position)(struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1100

void (*set_cursor_attribute)(struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1101

void (*set_cursor_sdr_white_level)(struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1102

void (*abort_cursor_offload_update)(struct dc *dc, const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1103

void (*begin_cursor_offload_update)(struct dc *dc, const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1104

void (*commit_cursor_offload_update)(struct dc *dc, const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1105

void (*update_cursor_offload_pipe)(struct dc *dc, const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1108

void (*program_cursor_offload_now)(struct dc *dc, const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1111

void (*program_gamut_remap)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1112

void (*program_output_csc)(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1115

void (*trigger_3dlut_dma_load)(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

114

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1151

void (*enable_audio_stream)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1152

void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1155

void (*setup_stereo)(struct pipe_ctx *pipe_ctx, struct dc *dc);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1165

bool (*set_backlight_level)(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1168

void (*set_abm_immediate_disable)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1170

void (*set_pipe)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

120

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1210

struct pipe_ctx *top_pipe_to_program,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1220

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1231

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1235

struct pipe_ctx *phantom_pipe);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1236

void (*apply_update_flags_for_phantom)(struct pipe_ctx *phantom_pipe);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1252

const struct pipe_ctx *top_pipe_to_program);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1260

void (*set_long_vtotal)(struct pipe_ctx **pipe_ctx, int num_pipes, uint32_t v_total_min, uint32_t v_total_max);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1264

void (*wait_for_all_pending_updates)(const struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1267

struct pipe_ctx *old_pipe,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1268

struct pipe_ctx *new_pipe);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1270

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1273

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1277

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1280

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1284

struct pipe_ctx *opp_head);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1287

struct pipe_ctx *opp_head,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1318

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1321

const struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1325

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1328

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1334

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1337

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1342

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1346

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1350

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1355

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1361

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1364

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1377

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

152

const struct pipe_ctx *top_pipe_to_program;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1605

struct dc *dc, struct pipe_ctx *pipe_ctx, bool lock);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1611

struct dc *dc, struct pipe_ctx *pipe_ctx, bool enableTripleBuffer);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1614

struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1617

struct dc *dc, struct pipe_ctx *pipe_ctx, struct dc_plane_state *plane_state);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1620

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1623

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1626

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1629

struct dc *dc, struct pipe_ctx *pipe_ctx, struct dc_stream_state *stream);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1632

struct dc *dc, struct pipe_ctx *pipe_ctx, int mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1650

struct dc *dc, struct pipe_ctx *top_pipe_to_program);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1656

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1659

struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1709

struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1727

struct pipe_ctx *pipe_ctx, bool enable, int opp_cnt);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1739

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1748

struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1764

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

179

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

187

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

192

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1952

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1988

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1992

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1996

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2000

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2004

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

253

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

260

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

265

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

302

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

329

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

349

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

366

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

37

struct pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

376

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

381

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

64

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

680

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

701

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

706

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

711

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

716

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

721

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

75

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

81

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

86

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

91

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

95

struct pipe_ctx *pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

105

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

108

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

112

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

118

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

119

void (*setup_vupdate_interrupt_sequence)(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

121

bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

132

void (*plane_atomic_disable)(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

159

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

161

struct pipe_ctx *pipe_ctx, struct block_sequence_state *seq_state);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

171

void (*set_hdr_multiplier)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

172

void (*set_hdr_multiplier_sequence)(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

178

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

182

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

187

bool (*set_blend_lut)(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

189

bool (*set_shaper_3dlut)(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

191

bool (*set_mcm_luts)(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

194

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

196

void (*enable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

203

unsigned int (*calculate_dccg_k1_k2_values)(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

210

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

213

bool (*is_dp_dig_pixel_rate_div_policy)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

215

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

218

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

221

void (*perform_3dlut_wa_unlock)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

222

void (*wait_for_pipe_update_if_needed)(struct dc *dc, struct pipe_ctx *pipe_ctx, bool is_surface_update_only);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

223

void (*set_wait_for_update_needed_for_pipe)(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

56

struct pipe_ctx;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

77

void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

78

void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

83

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

86

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

88

void (*update_mpcc)(struct dc *dc, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

89

void (*update_mpcc_sequence)(struct dc *dc, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

92

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

95

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

140

struct pipe_ctx *(*acquire_free_pipe_as_secondary_dpp_pipe)(

drivers/gpu/drm/amd/display/dc/inc/core_types.h

144

const struct pipe_ctx *opp_head_pipe);

drivers/gpu/drm/amd/display/dc/inc/core_types.h

146

struct pipe_ctx *(*acquire_free_pipe_as_secondary_opp_head)(

drivers/gpu/drm/amd/display/dc/inc/core_types.h

150

const struct pipe_ctx *otg_master);

drivers/gpu/drm/amd/display/dc/inc/core_types.h

153

struct pipe_ctx *pipe,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

217

void (*build_pipe_pix_clk_params)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/core_types.h

223

unsigned int (*get_vstartup_for_pipe)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/core_types.h

232

struct pipe_ctx *pipes,

drivers/gpu/drm/amd/display/dc/inc/core_types.h

477

struct pipe_ctx *top_pipe;

drivers/gpu/drm/amd/display/dc/inc/core_types.h

478

struct pipe_ctx *bottom_pipe;

drivers/gpu/drm/amd/display/dc/inc/core_types.h

479

struct pipe_ctx *next_odm_pipe;

drivers/gpu/drm/amd/display/dc/inc/core_types.h

480

struct pipe_ctx *prev_odm_pipe;

drivers/gpu/drm/amd/display/dc/inc/core_types.h

524

struct pipe_ctx pipe_ctx[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

538

struct pipe_ctx temp_pipe;

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

35

struct pipe_ctx;

drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h

484

const struct pipe_ctx *pipe,

drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h

42

struct pipe_ctx;

drivers/gpu/drm/amd/display/dc/inc/link_hwss.h

38

struct pipe_ctx;

drivers/gpu/drm/amd/display/dc/inc/link_hwss.h

49

void (*set_hblank_min_symbol_width)(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/inc/link_hwss.h

52

void (*set_throttled_vcp_size)(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/inc/link_hwss.h

77

void (*setup_stream_encoder)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/link_hwss.h

78

void (*reset_stream_encoder)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/link_hwss.h

79

void (*setup_stream_attribute)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/link_hwss.h

83

void (*setup_audio_output)(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/inc/link_hwss.h

85

void (*enable_audio_packet)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/link_hwss.h

86

void (*disable_audio_packet)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/link_service.h

154

void (*set_dpms_on)(struct dc_state *state, struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/link_service.h

155

void (*set_dpms_off)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/link_service.h

161

struct pipe_ctx *pipe_ctx, uint32_t req_pbn);

drivers/gpu/drm/amd/display/dc/inc/link_service.h

163

struct pipe_ctx *pipe_ctx, uint32_t req_pbn);

drivers/gpu/drm/amd/display/dc/inc/link_service.h

164

void (*set_dsc_on_stream)(struct pipe_ctx *pipe_ctx, bool enable);

drivers/gpu/drm/amd/display/dc/inc/link_service.h

165

bool (*set_dsc_enable)(struct pipe_ctx *pipe_ctx, bool enable);

drivers/gpu/drm/amd/display/dc/inc/link_service.h

166

bool (*update_dsc_config)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/link_service.h

196

bool (*dp_is_128b_132b_signal)(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/resource.h

116

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/resource.h

118

bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/resource.h

124

void resource_build_info_frame(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/resource.h

151

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/resource.h

164

bool resource_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/resource.h

287

bool resource_is_pipe_type(const struct pipe_ctx *pipe_ctx, enum pipe_type type);

drivers/gpu/drm/amd/display/dc/inc/resource.h

315

struct pipe_ctx *otg_master_pipe,

drivers/gpu/drm/amd/display/dc/inc/resource.h

379

struct pipe_ctx *resource_get_otg_master_for_stream(

drivers/gpu/drm/amd/display/dc/inc/resource.h

389

int resource_get_opp_heads_for_otg_master(const struct pipe_ctx *otg_master,

drivers/gpu/drm/amd/display/dc/inc/resource.h

391

struct pipe_ctx *opp_heads[MAX_PIPES]);

drivers/gpu/drm/amd/display/dc/inc/resource.h

399

int resource_get_dpp_pipes_for_opp_head(const struct pipe_ctx *opp_head,

drivers/gpu/drm/amd/display/dc/inc/resource.h

401

struct pipe_ctx *dpp_pipes[MAX_PIPES]);

drivers/gpu/drm/amd/display/dc/inc/resource.h

410

struct pipe_ctx *dpp_pipes[MAX_PIPES]);

drivers/gpu/drm/amd/display/dc/inc/resource.h

417

struct pipe_ctx *resource_get_otg_master(const struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/resource.h

424

struct pipe_ctx *resource_get_opp_head(const struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/resource.h

430

struct pipe_ctx *resource_get_primary_dpp_pipe(const struct pipe_ctx *dpp_pipe);

drivers/gpu/drm/amd/display/dc/inc/resource.h

437

int resource_get_mpc_slice_index(const struct pipe_ctx *dpp_pipe);

drivers/gpu/drm/amd/display/dc/inc/resource.h

444

int resource_get_mpc_slice_count(const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/inc/resource.h

451

int resource_get_odm_slice_count(const struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/inc/resource.h

454

int resource_get_odm_slice_index(const struct pipe_ctx *opp_head);

drivers/gpu/drm/amd/display/dc/inc/resource.h

457

struct rect resource_get_odm_slice_src_rect(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/resource.h

460

struct rect resource_get_odm_slice_dst_rect(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/resource.h

463

int resource_get_odm_slice_dst_width(struct pipe_ctx *otg_master,

drivers/gpu/drm/amd/display/dc/inc/resource.h

477

bool resource_is_odm_topology_changed(const struct pipe_ctx *otg_master_a,

drivers/gpu/drm/amd/display/dc/inc/resource.h

478

const struct pipe_ctx *otg_master_b);

drivers/gpu/drm/amd/display/dc/inc/resource.h

493

const struct pipe_ctx *cur_otg_master);

drivers/gpu/drm/amd/display/dc/inc/resource.h

505

const struct pipe_ctx *cur_opp_head);

drivers/gpu/drm/amd/display/dc/inc/resource.h

566

struct pipe_ctx *resource_find_free_secondary_pipe_legacy(

drivers/gpu/drm/amd/display/dc/inc/resource.h

569

const struct pipe_ctx *primary_pipe);

drivers/gpu/drm/amd/display/dc/inc/resource.h

589

struct pipe_ctx *pipe_ctx_old,

drivers/gpu/drm/amd/display/dc/inc/resource.h

590

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/resource.h

628

struct pipe_ctx *pri_pipe,

drivers/gpu/drm/amd/display/dc/inc/resource.h

629

struct pipe_ctx *sec_pipe,

drivers/gpu/drm/amd/display/dc/inc/resource.h

639

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/resource.h

645

struct dscl_prog_data *resource_get_dscl_prog_data(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/inc/resource.h

655

int resource_calculate_det_for_stream(struct dc_state *state, struct pipe_ctx *otg_master);

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

219

tg = dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

196

struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

197

struct pipe_ctx *pipe_ctx = &pipes[0];

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

269

for (modes = 0; modes < pipe_ctx->stream->audio_info.mode_count; modes++) {

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

482

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

487

enum dc_color_depth color_depth = pipe_ctx->

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

490

struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

491

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

497

pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

498

controller_test_pattern = pipe_ctx->stream_res.test_pattern_params.test_pattern;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

508

pipe_ctx->stream->bit_depth_params = params;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

509

if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) {

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

511

pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

517

controller_color_space = pipe_ctx->stream_res.test_pattern_params.color_space;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

524

odm_pipe = pipe_ctx;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

546

resource_build_bit_depth_reduction_params(pipe_ctx->stream, &params);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

547

pipe_ctx->stream->bit_depth_params = params;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

548

if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) {

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

550

pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

556

odm_pipe = pipe_ctx;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

656

struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

657

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

672

pipe_ctx = &pipes[i];

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

677

if (pipe_ctx == NULL)

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

686

set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

687

dp_set_hw_test_pattern(link, &pipe_ctx->link_res, test_pattern,

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

69

struct pipe_ctx *pipes[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

693

pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

718

dp_set_hw_lane_settings(link, &pipe_ctx->link_res, p_link_settings, DPRX);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

730

link->dc->hwss.blank_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

733

dp_set_hw_test_pattern(link, &pipe_ctx->link_res, test_pattern,

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

877

if (!pipe_ctx->stream)

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

880

if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable) {

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

881

if (should_use_dmub_inbox1_lock(pipe_ctx->stream->link->dc, pipe_ctx->stream->link)) {

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

886

inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

893

pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable(

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

894

pipe_ctx->stream_res.tg);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

897

pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

899

link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

900

pipe_ctx->stream->output_color_space = color_space;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

901

link_hwss->setup_stream_attribute(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

903

if (pipe_ctx->stream->use_vsc_sdp_for_colorimetry) {

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

905

pipe_ctx->stream->vsc_infopacket.sb[17] |= (1 << 7); // sb17 bit 7 Dynamic Range: 0 = VESA range, 1 = CTA range

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

907

pipe_ctx->stream->vsc_infopacket.sb[17] &= ~(1 << 7);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

910

pipe_ctx->stream->vsc_infopacket.sb[16] &= 0xf0;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

912

pipe_ctx->stream->vsc_infopacket.sb[16] |= 1;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

914

resource_build_info_frame(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

915

link->dc->hwss.update_info_frame(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

919

set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

920

pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

921

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

923

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

925

pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

928

if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable) {

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

929

if (should_use_dmub_inbox1_lock(pipe_ctx->stream->link->dc, pipe_ctx->stream->link)) {

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

934

inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

941

pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable(

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

942

pipe_ctx->stream_res.tg);

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

959

struct pipe_ctx *pipe;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

974

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

101

pipe_ctx->stream->signal, false);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

103

if (!dc_is_rgb_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

106

pipe_ctx->stream_res.stream_enc->id,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

109

if (dc_is_dp_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

110

pipe_ctx->stream->ctx->dc->link_srv->dp_trace_source_sequence(

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

111

pipe_ctx->stream->link,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

116

void setup_dio_stream_attribute(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

118

struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

119

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

126

pipe_ctx->stream_res.tg->inst,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

141

pipe_ctx->stream_res.audio != NULL);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

254

void setup_dio_audio_output(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

257

if (dc_is_dp_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

258

pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup(

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

259

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

261

&pipe_ctx->stream->audio_info);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

263

pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup(

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

264

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

266

&pipe_ctx->stream->audio_info,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

270

void enable_dio_audio_packet(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

272

if (dc_is_dp_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

273

pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

274

pipe_ctx->stream_res.stream_enc);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

276

pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

277

pipe_ctx->stream_res.stream_enc, false);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

279

if (dc_is_dp_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

280

pipe_ctx->stream->ctx->dc->link_srv->dp_trace_source_sequence(

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

281

pipe_ctx->stream->link,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

285

void disable_dio_audio_packet(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

287

pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

288

pipe_ctx->stream_res.stream_enc, true);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

290

if (pipe_ctx->stream_res.audio) {

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

291

if (dc_is_dp_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

292

pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable(

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

293

pipe_ctx->stream_res.stream_enc);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

295

pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable(

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

296

pipe_ctx->stream_res.stream_enc);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

299

if (dc_is_dp_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

300

pipe_ctx->stream->ctx->dc->link_srv->dp_trace_source_sequence(

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

301

pipe_ctx->stream->link,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

39

void set_dio_throttled_vcp_size(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

42

struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

49

void setup_dio_stream_encoder(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

51

struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

52

struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

54

if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

55

link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

61

if (!dc_is_rgb_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

63

pipe_ctx->stream_res.stream_enc->id, true);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

64

if (dc_is_dp_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

65

pipe_ctx->stream->ctx->dc->link_srv->dp_trace_source_sequence(pipe_ctx->stream->link,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

69

pipe_ctx->stream->signal, true);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

75

pipe_ctx->stream_res.pix_clk_params.dio_se_pix_per_cycle);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

80

void reset_dio_stream_encoder(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

82

struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

83

struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

85

if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c

86

link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h

35

void set_dio_throttled_vcp_size(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h

37

void setup_dio_stream_encoder(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h

38

void reset_dio_stream_encoder(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h

39

void setup_dio_stream_attribute(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h

55

void setup_dio_audio_output(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h

57

void enable_dio_audio_packet(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h

58

void disable_dio_audio_packet(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

178

void setup_hpo_dp_audio_output(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

181

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_setup(

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

182

pipe_ctx->stream_res.hpo_dp_stream_enc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

184

&pipe_ctx->stream->audio_info);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

187

void enable_hpo_dp_audio_packet(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

189

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_enable(

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

190

pipe_ctx->stream_res.hpo_dp_stream_enc);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

193

void disable_hpo_dp_audio_packet(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

195

if (pipe_ctx->stream_res.audio)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

196

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_disable(

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

197

pipe_ctx->stream_res.hpo_dp_stream_enc);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

33

void set_hpo_dp_throttled_vcp_size(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

37

pipe_ctx->stream_res.hpo_dp_stream_enc;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

39

pipe_ctx->link_res.hpo_dp_link_enc;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

46

void set_hpo_dp_hblank_min_symbol_width(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

51

pipe_ctx->stream_res.hpo_dp_stream_enc;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

52

struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

56

pipe_ctx->stream->link, link_settings);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

74

void setup_hpo_dp_stream_encoder(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

76

struct hpo_dp_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

77

struct hpo_dp_link_encoder *link_enc = pipe_ctx->link_res.hpo_dp_link_enc;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

83

void reset_hpo_dp_stream_encoder(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

85

struct hpo_dp_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

90

void setup_hpo_dp_stream_attribute(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

92

struct hpo_dp_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

93

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h

31

void set_hpo_dp_throttled_vcp_size(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h

33

void set_hpo_dp_hblank_min_symbol_width(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h

36

void set_hpo_dp_hblank_min_symbol_width(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h

39

void setup_hpo_dp_stream_encoder(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h

40

void reset_hpo_dp_stream_encoder(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h

41

void setup_hpo_dp_stream_attribute(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h

53

void setup_hpo_dp_audio_output(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h

55

void enable_hpo_dp_audio_packet(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h

56

void disable_hpo_dp_audio_packet(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_virtual.c

28

void virtual_setup_stream_encoder(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_virtual.c

32

void virtual_setup_stream_attribute(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_virtual.c

36

void virtual_reset_stream_encoder(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_virtual.h

30

void virtual_setup_stream_encoder(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_virtual.h

31

void virtual_setup_stream_attribute(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_virtual.h

32

void virtual_reset_stream_encoder(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1000

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet(

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1001

pipe_ctx->stream_res.hpo_dp_stream_enc,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1006

pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1007

pipe_ctx->stream_res.stream_enc, false, NULL, true);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1014

bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1016

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1019

if (!pipe_ctx->stream->timing.flags.DSC)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1026

link_set_dsc_on_stream(pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1030

dp_set_dsc_on_rx(pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1031

link_set_dsc_on_stream(pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1038

bool link_update_dsc_config(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1040

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1042

if (!pipe_ctx->stream->timing.flags.DSC)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1047

link_set_dsc_on_stream(pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1048

link_set_dsc_pps_packet(pipe_ctx, true, false);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1052

static void enable_stream_features(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1054

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1056

if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1161

static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1166

if (dp_is_128b_132b_signal(pipe_ctx))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1171

kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing, link_encoding);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1356

static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1358

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1363

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1376

link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1378

link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1393

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1394

pipe_ctx->stream_res.hpo_dp_stream_enc,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1398

pipe_ctx->pipe_idx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1403

remove_stream_from_alloc_table(link, pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1404

pipe_ctx->stream_res.hpo_dp_stream_enc);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1416

link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1434

static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1436

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1443

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1459

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1460

pipe_ctx->stream_res.hpo_dp_stream_enc,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1464

pipe_ctx->pipe_idx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1478

&pipe_ctx->link_res,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1497

pbn = get_pbn_from_timing(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1503

link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1505

link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

152

struct pipe_ctx *pipes[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1640

static enum dc_status update_sst_payload(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1643

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1648

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1658

link_hwss->ext.set_throttled_vcp_size(pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1661

link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1675

pipe_ctx->pipe_idx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1679

proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1692

link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1709

link_hwss->ext.set_throttled_vcp_size(pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1712

link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1723

enum dc_status link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1725

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1731

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1740

link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1742

link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1760

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1761

pipe_ctx->stream_res.hpo_dp_stream_enc,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1765

pipe_ctx->pipe_idx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1779

link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1790

enum dc_status link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1792

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1799

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1811

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1812

pipe_ctx->stream_res.hpo_dp_stream_enc,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1827

link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1848

link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1850

link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1907

static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1909

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1917

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1918

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1929

if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1930

unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps &

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1934

eng_id = pipe_ctx->stream_res.stream_enc->id;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1936

if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1937

write_i2c_retimer_setting(pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1940

write_i2c_default_retimer_setting(pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1945

write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1949

if (dc_is_hdmi_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1965

if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) || dc_is_dvi_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1966

link_hwss->setup_stream_encoder(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

197

const struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1970

&pipe_ctx->link_res,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1971

pipe_ctx->stream->signal,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1972

pipe_ctx->clock_source->id,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1976

if (dc_is_hdmi_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1981

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1983

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1988

&pipe_ctx->link_config.dp_link_settings;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2023

pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2027

pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2032

if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2042

pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2070

pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2071

pipe_ctx->stream->signal,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2084

dp_set_fec_enable(link, &pipe_ctx->link_res, fec_enable);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

210

struct pipe_ctx *pipes[MAX_PIPES])

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2105

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2107

return enable_link_dp(state, pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2110

static void enable_link_lvds(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2112

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2123

&pipe_ctx->link_res,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2124

pipe_ctx->clock_source->id,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

213

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2131

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2133

struct dc_link *link = pipe_ctx->stream->link;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2155

return enable_link_dp(state, pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2160

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2162

struct dc_link *link = pipe_ctx->stream->link;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2165

link, pipe_ctx->stream->timing.pix_clk_100hz);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

217

pipe = &state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2170

static enum dc_status enable_link_virtual(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2172

struct dc_link *link = pipe_ctx->stream->link;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2175

&pipe_ctx->link_res,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2177

pipe_ctx->clock_source->id,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2178

&pipe_ctx->link_config.dp_link_settings);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2184

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2187

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2201

disable_link(link, &pipe_ctx->link_res, pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2203

switch (pipe_ctx->stream->signal) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2205

status = enable_link_dp(state, pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2208

status = enable_link_edp(state, pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2211

status = enable_link_dp_mst(state, pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2217

enable_link_hdmi(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2221

enable_link_lvds(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2225

status = enable_link_analog(state, pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2228

status = enable_link_virtual(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2235

pipe_ctx->stream->link->link_status.link_active = true;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

226

static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2309

void link_set_dpms_off(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2311

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2312

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2314

struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2317

DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2319

ASSERT(is_master_pipe_for_link(link, pipe_ctx));

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2321

if (dp_is_128b_132b_signal(pipe_ctx))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2322

vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2323

if (dc_is_virtual_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2326

if (pipe_ctx->stream->sink) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2327

if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2328

pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

233

pipe_ctx->stream->ctx->dc_bios->integrated_info;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2330

pipe_ctx->stream->sink->edid_caps.display_name,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2331

pipe_ctx->stream->signal, link->link_index, link->sink_count);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2335

if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2336

if (dc_is_hdmi_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2337

set_avmute(pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2340

dc->hwss.disable_audio_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2342

update_psp_stream_config(pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2343

dc->hwss.blank_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2345

if (pipe_ctx->link_config.dp_tunnel_settings.should_use_dp_bw_allocation)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2346

deallocate_usb4_bandwidth(pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2348

if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2349

deallocate_mst_payload(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2350

else if (dc_is_dp_sst_signal(pipe_ctx->stream->signal) &&

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2351

dp_is_128b_132b_signal(pipe_ctx))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2352

update_sst_payload(pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2354

if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2356

enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2367

if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2368

write_i2c_retimer_setting(pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2371

write_i2c_default_retimer_setting(pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2375

write_i2c_redriver_setting(pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2379

if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2380

!dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2389

disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2390

dc->hwss.disable_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2392

dc->hwss.disable_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2393

disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2395

edp_set_panel_assr(link, pipe_ctx, &panel_mode_dp, false);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2397

if (pipe_ctx->stream->timing.flags.DSC) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2398

if (dc_is_dp_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2399

link_set_dsc_enable(pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2401

if (dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2402

if (pipe_ctx->stream_res.tg->funcs->set_out_mux)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2403

pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2412

enum dp_panel_mode panel_mode = dp_get_panel_mode(pipe_ctx->stream->link);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2420

struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2422

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2423

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2426

struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2428

struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2429

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2431

pipe_ctx->stream->apply_edp_fast_boot_optimization;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2433

DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2435

ASSERT(is_master_pipe_for_link(link, pipe_ctx));

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2437

if (dp_is_128b_132b_signal(pipe_ctx))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2438

vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2439

if (dc_is_virtual_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2442

if (pipe_ctx->stream->sink) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2443

if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2444

pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2446

pipe_ctx->stream->sink->edid_caps.display_name,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2447

pipe_ctx->stream->signal,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2457

if (!dc_is_virtual_signal(pipe_ctx->stream->signal)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2458

&& !dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2462

pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2465

pipe_ctx->stream->link->link_state_valid = true;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2467

if (pipe_ctx->stream_res.tg->funcs->set_out_mux) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2468

if (dp_is_128b_132b_signal(pipe_ctx))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2472

pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2475

link_hwss->setup_stream_attribute(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2477

pipe_ctx->stream->apply_edp_fast_boot_optimization = false;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2483

resource_build_info_frame(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2484

dc->hwss.update_info_frame(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2486

if (dc_is_dp_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2490

if (pipe_ctx->stream->apply_seamless_boot_optimization) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2491

pipe_ctx->stream->dpms_off = false;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2494

if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2495

enable_stream_features(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2496

dc->hwss.enable_audio_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2499

update_psp_stream_config(pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2504

if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2506

!pipe_ctx->stream->timing.flags.DSC &&

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2507

!pipe_ctx->next_odm_pipe) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2508

pipe_ctx->stream->dpms_off = false;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2509

update_psp_stream_config(pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2521

if (pipe_ctx->stream->dpms_off)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2539

if (pipe_ctx->stream->timing.flags.DSC) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2540

if (dc_is_dp_signal(pipe_ctx->stream->signal) ||

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2541

dc_is_virtual_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2542

link_set_dsc_enable(pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2548

status = enable_link(state, pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2552

pipe_ctx->stream->link->link_index,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2561

pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2563

disable_link(stream->link, &pipe_ctx->link_res,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2564

pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2571

if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2572

pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2580

if (!(dc_is_virtual_signal(pipe_ctx->stream->signal) ||

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2581

dp_is_128b_132b_signal(pipe_ctx))) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2586

pipe_ctx->stream->signal);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2590

dc->hwss.enable_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2593

if (pipe_ctx->stream->timing.flags.DSC) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2594

if (dc_is_dp_signal(pipe_ctx->stream->signal) ||

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2595

dc_is_virtual_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2596

dp_set_dsc_on_rx(pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2597

link_set_dsc_pps_packet(pipe_ctx, true, true);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2601

if (dc_is_dp_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2602

dp_set_hblank_reduction_on_rx(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2604

if (pipe_ctx->link_config.dp_tunnel_settings.should_use_dp_bw_allocation)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2605

allocate_usb4_bandwidth(pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2607

if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2608

allocate_mst_payload(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2609

else if (dc_is_dp_sst_signal(pipe_ctx->stream->signal) &&

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2610

dp_is_128b_132b_signal(pipe_ctx))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2611

update_sst_payload(pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2618

if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2622

dc->hwss.unblank_stream(pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2623

&pipe_ctx->stream->link->cur_link_settings);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2628

if (dc_is_dp_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2629

enable_stream_features(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2630

update_psp_stream_config(pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2632

dc->hwss.enable_audio_stream(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2634

if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2635

set_avmute(pipe_ctx, false);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

323

static bool write_i2c(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

334

cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

342

if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

343

pipe_ctx->stream->link, &cmd))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

350

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

362

DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

374

i2c_success = write_i2c(pipe_ctx, slave_address,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

396

pipe_ctx->stream->link->ddc,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

405

i2c_success = write_i2c(pipe_ctx, slave_address,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

424

i2c_success = write_i2c(pipe_ctx, slave_address,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

446

pipe_ctx->stream->link->ddc,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

455

i2c_success = write_i2c(pipe_ctx, slave_address,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

473

i2c_success = write_i2c(pipe_ctx, slave_address,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

484

i2c_success = write_i2c(pipe_ctx, slave_address,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

495

i2c_success = write_i2c(pipe_ctx, slave_address,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

512

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

519

DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

527

i2c_success = write_i2c(pipe_ctx, slave_address,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

538

i2c_success = write_i2c(pipe_ctx, slave_address,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

549

i2c_success = write_i2c(pipe_ctx, slave_address,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

560

i2c_success = write_i2c(pipe_ctx, slave_address,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

571

i2c_success = write_i2c(pipe_ctx, slave_address,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

582

i2c_success = write_i2c(pipe_ctx, slave_address,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

597

i2c_success = write_i2c(pipe_ctx, slave_address,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

608

i2c_success = write_i2c(pipe_ctx, slave_address,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

619

i2c_success = write_i2c(pipe_ctx, slave_address,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

635

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

641

DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

651

i2c_success = write_i2c(pipe_ctx, slave_address,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

663

static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

665

struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

666

struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

669

dp_get_panel_mode(pipe_ctx->stream->link);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

673

if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

674

link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

680

config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

683

config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

686

config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

687

if (dp_is_128b_132b_signal(pipe_ctx))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

689

pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

692

config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

696

if (dp_is_128b_132b_signal(pipe_ctx))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

697

config.link_enc_idx = pipe_ctx->link_res.hpo_dp_link_enc->inst;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

700

if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

701

config.dio_output_idx = pipe_ctx->stream->link->link_id.enum_id - ENUM_ID_1;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

708

pipe_ctx->stream->link->dc, link_enc->transmitter);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

709

if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

715

config.mst_enabled = (pipe_ctx->stream->signal ==

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

717

config.dp2_enabled = dp_is_128b_132b_signal(pipe_ctx) ? 1 : 0;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

718

config.usb4_enabled = (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ?

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

723

config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

728

static void set_avmute(struct pipe_ctx *pipe_ctx, bool enable)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

730

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

732

if (!dc_is_hdmi_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

735

dc->hwss.set_avmute(pipe_ctx, enable);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

773

static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

775

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

776

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

786

static bool dp_set_hblank_reduction_on_rx(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

788

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

789

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

803

void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

808

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

809

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

810

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

811

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

827

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

836

dsc_cfg.pic_width = (stream->timing.h_addressable + pipe_ctx->dsc_padding_params.dsc_hactive_padding +

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

841

dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

850

dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

851

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

861

dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

866

if (dc_is_dp_signal(stream->signal) && !dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

867

DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

869

if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

870

pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

879

DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

881

pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

887

pipe_ctx->stream_res.tg->funcs->set_dsc_config(

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

888

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

893

if (dp_is_128b_132b_signal(pipe_ctx))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

894

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet(

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

895

pipe_ctx->stream_res.hpo_dp_stream_enc,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

900

if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

901

pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

902

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

904

pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

905

pipe_ctx->stream_res.stream_enc, false, NULL, true);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

910

for (odm_pipe = pipe_ctx; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

949

bool link_set_dsc_pps_packet(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_update)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

951

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

952

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

954

if (!pipe_ctx->stream->timing.flags.DSC)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

974

dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

976

dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

981

DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

982

if (dp_is_128b_132b_signal(pipe_ctx))

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

983

pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet(

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

984

pipe_ctx->stream_res.hpo_dp_stream_enc,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

989

pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

990

pipe_ctx->stream_res.stream_enc,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

999

if (dp_is_128b_132b_signal(pipe_ctx))

drivers/gpu/drm/amd/display/dc/link/link_dpms.h

32

struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.h

33

void link_set_dpms_off(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.h

42

struct pipe_ctx *pipes[MAX_PIPES]);

drivers/gpu/drm/amd/display/dc/link/link_dpms.h

43

enum dc_status link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t req_pbn);

drivers/gpu/drm/amd/display/dc/link/link_dpms.h

44

enum dc_status link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t req_pbn);

drivers/gpu/drm/amd/display/dc/link/link_dpms.h

45

bool link_set_dsc_pps_packet(struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/link_dpms.h

50

void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);

drivers/gpu/drm/amd/display/dc/link/link_dpms.h

51

bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable);

drivers/gpu/drm/amd/display/dc/link/link_dpms.h

52

bool link_update_dsc_config(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_frl.c

29

static void setup_hpo_frl_stream_attribute(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_frl.c

31

struct hpo_frl_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_frl_stream_enc;

drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_frl.c

32

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_frl.c

33

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_frl.c

37

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)

drivers/gpu/drm/amd/display/dc/link/link_resource.c

36

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/link/link_resource.c

41

pipe = &link->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/link/link_validation.c

377

if (context->res_ctx.pipe_ctx[i].stream && (context->res_ctx.pipe_ctx[i].stream == stream)) {

drivers/gpu/drm/amd/display/dc/link/link_validation.c

378

dp_tunnel_settings = &context->res_ctx.pipe_ctx[i].link_config.dp_tunnel_settings;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

378

bool dp_is_128b_132b_signal(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

381

ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

382

return (pipe_ctx->stream_res.hpo_dp_stream_enc &&

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

383

pipe_ctx->link_res.hpo_dp_link_enc &&

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

384

dc_is_dp_signal(pipe_ctx->stream->signal));

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h

68

bool dp_is_128b_132b_signal(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

310

struct pipe_ctx *pipes[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

128

if (dc->current_state->res_ctx.pipe_ctx[i].stream

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

134

dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg->inst + 1;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

219

if (dc->current_state->res_ctx.pipe_ctx[i].stream &&

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

220

dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

222

if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

223

*inst_out = dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

280

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

286

if (dc->current_state->res_ctx.pipe_ctx[i].stream &&

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

287

dc->current_state->res_ctx.pipe_ctx[i].stream->link &&

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

288

dc->current_state->res_ctx.pipe_ctx[i].stream->link == link &&

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

289

dc_is_dp_sst_signal(dc->current_state->res_ctx.pipe_ctx[i].stream->link->connector_signal)) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

290

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

296

if (!pipe_ctx)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

308

if (pipe_ctx->plane_res.dpp)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

309

cmd.pr_copy_settings.data.dpp_inst = pipe_ctx->plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

312

if (pipe_ctx->stream_res.tg)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

313

cmd.pr_copy_settings.data.otg_inst = pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

321

cmd.pr_copy_settings.data.flags.bitfields.dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

330

if (pipe_ctx->stream->timing.dsc_cfg.num_slices_v > 0)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

331

cmd.pr_copy_settings.data.dsc_slice_height = (pipe_ctx->stream->timing.v_addressable +

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

332

pipe_ctx->stream->timing.v_border_top + pipe_ctx->stream->timing.v_border_bottom) /

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

333

pipe_ctx->stream->timing.dsc_cfg.num_slices_v;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

60

if (dc->current_state->res_ctx.pipe_ctx[i].stream &&

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

61

dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

62

struct dc_stream_state *stream = dc->current_state->res_ctx.pipe_ctx[i].stream;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1622

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1628

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1634

const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1648

link_hwss->setup_stream_encoder(pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1661

&pipe_ctx->link_res,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1663

pipe_ctx->clock_source->id,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1672

edp_set_panel_assr(link, pipe_ctx, &panel_mode, true);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1677

dp_perform_link_training_skip_aux(link, &pipe_ctx->link_res, &cur_link_settings);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1683

&pipe_ctx->link_res,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1689

dp_set_hw_test_pattern(link, &pipe_ctx->link_res, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1701

&pipe_ctx->link_res,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

1755

dp_disable_link_phy(link, &pipe_ctx->link_res, signal);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h

35

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1032

if (dc->current_state->res_ctx.pipe_ctx[i].stream

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1038

dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg->inst + 1;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1196

struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1197

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1200

abm = pipe_ctx->stream_res.abm;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1283

void edp_set_panel_assr(struct dc_link *link, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1286

struct link_resource *link_res = &pipe_ctx->link_res;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1287

struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

531

static struct pipe_ctx *get_pipe_from_link(const struct dc_link *link)

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

535

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

538

if (dc->current_state->res_ctx.pipe_ctx[i].stream) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

539

if (dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

540

pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

546

return pipe_ctx;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

560

struct pipe_ctx *pipe_ctx = get_pipe_from_link(link);

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

565

if (pipe_ctx) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

569

if (pipe_ctx->plane_state == NULL)

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

578

pipe_ctx,

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

800

if (dc->current_state->res_ctx.pipe_ctx[i].stream

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

807

pipe_ctx[i].stream_res.tg->inst + 1;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h

78

void edp_set_panel_assr(struct dc_link *link, struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

403

struct pipe_ctx *pipe_ctx = &pg_cntl->ctx->dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

405

if (pipe_ctx) {

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

406

if (pipe_ctx->stream)

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

852

struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

854

if (!pipe_ctx)

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

857

dce110_resource_build_pipe_hw_param(pipe_ctx);

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

859

resource_build_info_frame(pipe_ctx);

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

875

stream = context->res_ctx.pipe_ctx[i].stream;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1127

static struct pipe_ctx *dce110_acquire_underlay(

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1131

const struct pipe_ctx *opp_head_pipe)

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1138

struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx];

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1140

if (res_ctx->pipe_ctx[underlay_idx].stream)

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1143

pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx];

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1144

pipe_ctx->plane_res.mi = pool->mis[underlay_idx];

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1146

pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx];

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1147

pipe_ctx->stream_res.opp = pool->opps[underlay_idx];

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1148

pipe_ctx->pipe_idx = underlay_idx;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1150

pipe_ctx->stream = stream;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1152

if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) {

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1158

pipe_ctx->stream_res.tg->inst,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1166

pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1173

pipe_ctx->stream->signal,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1176

pipe_ctx->stream_res.tg->funcs->enable_advanced_request(

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1177

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1181

pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1189

pipe_ctx->stream_res.tg->funcs->set_blank_color(

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1190

pipe_ctx->stream_res.tg,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1194

return pipe_ctx;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

887

const struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

890

const struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

898

if (dc_is_rgb_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

900

pixel_clk_params->signal_type = pipe_ctx->stream->signal;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

901

pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

923

void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

925

get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

926

pipe_ctx->clock_source->funcs->get_pix_clk_dividers(

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

927

pipe_ctx->clock_source,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

928

&pipe_ctx->stream_res.pix_clk_params,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

929

&pipe_ctx->pll_settings);

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

930

resource_build_bit_depth_reduction_params(pipe_ctx->stream,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

931

&pipe_ctx->stream->bit_depth_params);

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

932

pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

935

static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigned int underlay_idx)

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

937

if (pipe_ctx->pipe_idx != underlay_idx)

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

939

if (!pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

941

if (pipe_ctx->plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

951

struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

953

if (!pipe_ctx)

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

956

if (!is_surface_pixel_format_supported(pipe_ctx,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

960

dce110_resource_build_pipe_hw_param(pipe_ctx);

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

964

resource_build_info_frame(pipe_ctx);

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

984

context->res_ctx.pipe_ctx,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.h

41

void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

878

struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

880

if (!pipe_ctx)

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

883

dce110_resource_build_pipe_hw_param(pipe_ctx);

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

885

resource_build_info_frame(pipe_ctx);

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

905

context->res_ctx.pipe_ctx,

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

969

struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

972

if (!pipe_ctx)

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

975

if (dc_is_dp_signal(pipe_ctx->stream->signal)

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

976

|| dc_is_virtual_signal(pipe_ctx->stream->signal))

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

977

pipe_ctx->clock_source =

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

981

pipe_ctx->clock_source = find_matching_pll(

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

986

if (pipe_ctx->clock_source == NULL)

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

992

pipe_ctx->clock_source);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1029

const struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1032

const struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1035

pixel_clk_params->signal_type = pipe_ctx->stream->signal;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1036

pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1063

static void build_pipe_hw_param(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1066

get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1068

pipe_ctx->clock_source->funcs->get_pix_clk_dividers(

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1069

pipe_ctx->clock_source,

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1070

&pipe_ctx->stream_res.pix_clk_params,

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1071

&pipe_ctx->pll_settings);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1073

pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1075

resource_build_bit_depth_reduction_params(pipe_ctx->stream,

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1076

&pipe_ctx->stream->bit_depth_params);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1077

build_clamping_params(pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1085

struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1087

if (!pipe_ctx)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1090

build_pipe_hw_param(pipe_ctx);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1113

static struct pipe_ctx *dcn10_acquire_free_pipe_for_layer(

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1117

const struct pipe_ctx *opp_head_pipe)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1120

struct pipe_ctx *head_pipe = resource_get_otg_master_for_stream(res_ctx, opp_head_pipe->stream);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1121

struct pipe_ctx *idle_pipe = resource_find_free_secondary_pipe_legacy(res_ctx, pool, head_pipe);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1300

unsigned int dcn10_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1302

return pipe_ctx->pipe_dlg_param.vstartup_start;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.h

54

unsigned int dcn10_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1251

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1254

const struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1255

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1258

struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1259

struct dc *dc = pipe_ctx->stream->ctx->dc;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1262

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1272

pixel_clk_params->signal_type = pipe_ctx->stream->signal;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1273

pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1289

else if (pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing) || opp_cnt == 2)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1292

if (hws->funcs.is_dp_dig_pixel_rate_div_policy(pipe_ctx))

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1299

if ((pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container &&

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1300

pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&pipe_ctx->stream->timing)) ||

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1302

hws->funcs.is_dp_dig_pixel_rate_div_policy(pipe_ctx)) ||

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1317

void dcn20_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1319

get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1320

pipe_ctx->clock_source->funcs->get_pix_clk_dividers(

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1321

pipe_ctx->clock_source,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1322

&pipe_ctx->stream_res.pix_clk_params,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1323

&pipe_ctx->pll_settings);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1326

static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1328

struct resource_pool *pool = pipe_ctx->stream->ctx->dc->res_pool;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1331

pool->funcs->build_pipe_pix_clk_params(pipe_ctx);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1333

dcn20_build_pipe_pix_clk_params(pipe_ctx);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1336

pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1338

resource_build_bit_depth_reduction_params(pipe_ctx->stream,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1339

&pipe_ctx->stream->bit_depth_params);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1340

build_clamping_params(pipe_ctx->stream);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1348

struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1350

if (!pipe_ctx)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1354

status = build_pipe_hw_param(pipe_ctx);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1367

struct display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_res.dsc;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1420

struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1422

if (pipe_ctx->top_pipe)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1425

if (pipe_ctx->stream != dc_stream)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1428

if (pipe_ctx->stream_res.dsc)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1431

dcn20_acquire_dsc(dc, &dc_ctx->res_ctx, &pipe_ctx->stream_res.dsc, i);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1434

if (!pipe_ctx->stream_res.dsc) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1449

struct pipe_ctx *pipe_ctx = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1453

if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1454

pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1456

if (pipe_ctx->stream_res.dsc)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1457

dcn20_release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1461

if (!pipe_ctx)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1516

struct pipe_ctx *prev_odm_pipe,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1517

struct pipe_ctx *next_odm_pipe)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1571

struct pipe_ctx *primary_pipe,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1572

struct pipe_ctx *secondary_pipe)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1575

struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1642

if (!context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1646

if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1652

if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1653

if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1684

struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1685

struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1687

struct pipe_ctx *odm_pipe;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1690

for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1694

if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1697

dsc_cfg.pic_width = (stream->timing.h_addressable + pipe_ctx->dsc_padding_params.dsc_hactive_padding

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1703

dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1708

if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg))

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1714

struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1717

const struct pipe_ctx *primary_pipe)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1719

struct pipe_ctx *secondary_pipe = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1731

if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1732

preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1733

if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1734

secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1739

dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1740

preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1741

if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1742

secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1755

if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1756

&& dc->current_state->res_ctx.pipe_ctx[j].prev_odm_pipe == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1759

if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1760

secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1780

if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1781

secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1800

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1801

struct pipe_ctx *odm_pipe = pipe->next_odm_pipe;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1808

struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1829

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1830

struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1872

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1896

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1914

if (!context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1933

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1938

if (!context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2080

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2081

struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2180

struct pipe_ctx *dcn20_acquire_free_pipe_for_layer(

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2184

const struct pipe_ctx *opp_head)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2187

struct pipe_ctx *otg_master = resource_get_otg_master_for_stream(res_ctx, opp_head->stream);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2188

struct pipe_ctx *sec_dpp_pipe = resource_find_free_secondary_pipe_legacy(res_ctx, pool, otg_master);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2246

struct pipe_ctx *pipe,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

139

struct pipe_ctx *primary_pipe,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

140

struct pipe_ctx *secondary_pipe);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

144

struct pipe_ctx *prev_odm_pipe,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

145

struct pipe_ctx *next_odm_pipe);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

150

struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

153

const struct pipe_ctx *primary_pipe);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

168

void dcn20_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

61

struct pipe_ctx *dcn20_acquire_free_pipe_for_layer(

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

65

const struct pipe_ctx *opp_head_pipe);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

67

struct pipe_ctx *pipe,

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1033

static struct pipe_ctx *dcn201_acquire_free_pipe_for_layer(

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1037

const struct pipe_ctx *opp_head_pipe)

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1040

struct pipe_ctx *head_pipe = resource_get_otg_master_for_stream(res_ctx, opp_head_pipe->stream);

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1041

struct pipe_ctx *idle_pipe = resource_find_free_secondary_pipe_legacy(res_ctx, pool, head_pipe);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

849

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

850

struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

873

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

874

struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1365

if (!res_ctx->pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1421

if (!context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1425

struct dc_writeback_info *writeback_info = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j];

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1442

wb_arb_params->time_per_pixel = (1000000 << 6) / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* time_per_pixel should be in u6.6 format */

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1556

struct pipe_ctx *pri_pipe,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1557

struct pipe_ctx *sec_pipe,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1615

static struct pipe_ctx *dcn30_find_split_pipe(

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1620

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1623

if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1624

pipe = &context->res_ctx.pipe_ctx[old_index];

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1630

if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1631

&& dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1632

if (context->res_ctx.pipe_ctx[i].stream == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1633

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1647

if (context->res_ctx.pipe_ctx[i].stream == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1648

pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1734

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1735

struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1755

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1780

struct pipe_ctx *top_pipe = pipe->top_pipe;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1781

struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1800

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1801

struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1802

struct pipe_ctx *hsplit_pipe = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1843

struct pipe_ctx *pipe_4to1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1886

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1679

struct pipe_ctx *pipe = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1689

if (!res_ctx->pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1691

pipe = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2282

struct pipe_ctx *pipes,

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h

72

struct pipe_ctx *pipes,

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1678

if (!res_ctx->pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1682

if (res_ctx->pipe_ctx[i].stream->src.width != res_ctx->pipe_ctx[i].stream->dst.width ||

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1683

res_ctx->pipe_ctx[i].stream->src.height != res_ctx->pipe_ctx[i].stream->dst.height ||

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1684

(res_ctx->pipe_ctx[i].plane_state && (res_ctx->pipe_ctx[i].plane_state->src_rect.width

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1685

!= res_ctx->pipe_ctx[i].plane_state->dst_rect.width ||

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1686

res_ctx->pipe_ctx[i].plane_state->src_rect.height

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1687

!= res_ctx->pipe_ctx[i].plane_state->dst_rect.height)))

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1690

if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state != res_ctx->pipe_ctx[i].plane_state)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1703

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1715

if (!res_ctx->pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1717

pipe = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1779

pipe = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1648

struct pipe_ctx *pipe = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1658

if (!res_ctx->pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1660

pipe = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1681

struct pipe_ctx *curr_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1725

struct pipe_ctx *ref_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1764

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1907

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1939

pipe = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1940

if (!res_ctx->pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1954

if (!res_ctx->pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1956

pipe = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1975

odm_slice_count = resource_get_odm_slice_count(&res_ctx->pipe_ctx[subvp_main_pipe_index]);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2675

const struct pipe_ctx *new_opp_head)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2677

const struct pipe_ctx *cur_opp_head;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2680

cur_opp_head = &cur_res_ctx->pipe_ctx[new_opp_head->pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2708

static struct pipe_ctx *find_idle_secondary_pipe_check_mpo(

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2711

const struct pipe_ctx *primary_pipe)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2714

struct pipe_ctx *secondary_pipe = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2715

struct pipe_ctx *next_odm_mpo_pipe = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2717

struct pipe_ctx *old_primary_pipe = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2740

old_primary_pipe = &primary_pipe->stream->ctx->dc->current_state->res_ctx.pipe_ctx[primary_index];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2746

if ((res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) &&

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2748

secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2759

if ((res_ctx->pipe_ctx[i].stream == NULL) &&

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2761

secondary_pipe = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2770

static struct pipe_ctx *dcn32_acquire_idle_pipe_for_head_pipe_in_layer(

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2774

const struct pipe_ctx *head_pipe)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2777

struct pipe_ctx *idle_pipe, *pipe;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2793

pipe = &old_ctx->pipe_ctx[head_index];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2794

if (pipe->bottom_pipe && res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx].stream == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2795

idle_pipe = &res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2819

const struct pipe_ctx *new_otg_master)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2821

const struct pipe_ctx *cur_otg_master;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2824

cur_otg_master = &cur_res_ctx->pipe_ctx[new_otg_master->pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2842

struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_dpp_pipe(

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2846

const struct pipe_ctx *opp_head_pipe)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2850

struct pipe_ctx *free_pipe;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2860

free_pipe = &new_ctx->res_ctx.pipe_ctx[free_pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2879

struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_opp_head(

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2883

const struct pipe_ctx *otg_master)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2888

struct pipe_ctx *free_pipe;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2891

free_pipe = &new_ctx->res_ctx.pipe_ctx[free_pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

118

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

137

bool dcn32_is_center_timing(struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

138

bool dcn32_is_psr_capable(struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

144

const struct pipe_ctx *new_opp_head);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

146

struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_dpp_pipe(

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

150

const struct pipe_ctx *opp_head_pipe);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

152

struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_opp_head(

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

156

const struct pipe_ctx *otg_master);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

159

struct pipe_ctx *pipe,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

171

bool dcn32_allow_subvp_with_active_margin(struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

173

bool dcn32_allow_subvp_high_refresh_rate(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

179

bool dcn32_check_native_scaling_for_res(struct pipe_ctx *pipe, unsigned int width, unsigned int height);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

114

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

136

struct pipe_ctx *top_pipe = pipe->top_pipe;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

137

struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

159

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

176

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

201

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

212

bool dcn32_is_center_timing(struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

233

bool dcn32_is_psr_capable(struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

260

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

262

if (pipe_ctx->stream && pipe_ctx->plane_state && dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

263

if (dcn32_allow_subvp_high_refresh_rate(dc, context, pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

265

if (pipe_ctx->stream->timing.v_addressable == 1080 && pipe_ctx->stream->timing.h_addressable == 1920) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

275

struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

277

if (pipe_ctx->stream && pipe_ctx->plane_state && dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

278

if (pipe_ctx->stream->timing.v_addressable == 1080 && pipe_ctx->stream->timing.h_addressable == 1920) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

340

if (context->res_ctx.pipe_ctx[j].stream == context->streams[i] &&

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

348

current_plane = context->res_ctx.pipe_ctx[j].plane_state;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

350

if (k != j && context->res_ctx.pipe_ctx[k].stream == context->streams[i] &&

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

351

context->res_ctx.pipe_ctx[k].plane_state == current_plane) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

359

if (k != j && context->res_ctx.pipe_ctx[k].stream == context->streams[i] &&

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

360

context->res_ctx.pipe_ctx[k].plane_state == current_plane) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

370

if (!context->res_ctx.pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

386

struct pipe_ctx *pipe = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

391

if (!res_ctx->pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

394

pipe = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

41

struct pipe_ctx *pipe_ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

44

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

48

switch (pipe_ctx->stream->cursor_attributes.color_format) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

591

bool dcn32_check_native_scaling_for_res(struct pipe_ctx *pipe, unsigned int width, unsigned int height)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

618

static bool disallow_subvp_in_active_plus_blank(struct pipe_ctx *pipe)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

656

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

67

if (pipe_ctx->stream->cursor_position.enable && (ignore_cursor_buf ||

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

717

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

755

struct pipe_ctx *pipe = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

760

if (!res_ctx->pipe_ctx[i].stream)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

762

pipe = &res_ctx->pipe_ctx[i];

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1730

static void dcn401_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1732

const struct dc_stream_state *stream = pipe_ctx->stream;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1734

struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1735

struct pixel_clk_params *pixel_clk_params = &pipe_ctx->stream_res.pix_clk_params;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1739

if (pipe_ctx->dsc_padding_params.dsc_hactive_padding != 0)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1740

pixel_clk_params->requested_pix_clk_100hz = pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1742

if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1747

pixel_clk_params->signal_type = pipe_ctx->stream->signal;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1748

pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1770

pipe_ctx->clock_source->funcs->get_pix_clk_dividers(

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1771

pipe_ctx->clock_source,

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1772

&pipe_ctx->stream_res.pix_clk_params,

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1773

&pipe_ctx->pll_settings);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1809

unsigned int dcn401_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1811

return pipe_ctx->global_sync.dcn4x.vstartup_lines;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

31

unsigned int dcn401_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx);