drivers/net/phy/adin.c

571

phydev_dbg(phydev, "PHY is using mode '%s'\n",

drivers/net/phy/adin1100.c

258

phydev_dbg(phydev, "PHY supports 2.4V TX level: %s\n",

drivers/net/phy/air_en8811h.c

535

phydev_dbg(phydev, "CRC Check %s!\n",

drivers/net/phy/aquantia/aquantia_firmware.c

244

phydev_dbg(phydev, "primary %d IRAM offset=%d size=%d DRAM offset=%d size=%d\n",

drivers/net/phy/aquantia/aquantia_firmware.c

265

phydev_dbg(phydev, "loading DRAM 0x%08x from offset=%d size=%d\n",

drivers/net/phy/aquantia/aquantia_firmware.c

272

phydev_dbg(phydev, "loading IRAM 0x%08x from offset=%d size=%d\n",

drivers/net/phy/aquantia/aquantia_main.c

1000

phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n",

drivers/net/phy/aquantia/aquantia_main.c

744

phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u, Misc ID %u, Version %u\n",

drivers/net/phy/aquantia/aquantia_main.c

898

phydev_dbg(phydev,

drivers/net/phy/bcm54140.c

607

phydev_dbg(phydev, "probed (port %d, base PHY address %d)\n",

drivers/net/phy/dp83822.c

926

phydev_dbg(phydev, "SOR1 strap register: 0x%04x\n", val);

drivers/net/phy/mediatek/mtk-ge-soc.c

413

phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret);

drivers/net/phy/mediatek/mtk-ge-soc.c

710

phydev_dbg(phydev, "Start TX-VCM SW cal.\n");

drivers/net/phy/mediatek/mtk-ge-soc.c

770

phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx);

drivers/net/phy/meson-gxl.c

178

phydev_dbg(phydev, "LPA corruption - aneg restart\n");

drivers/net/phy/micrel.c

4504

phydev_dbg(phydev, "successfully registered ptp clock\n");

drivers/net/phy/motorcomm.c

2917

phydev_dbg(phydev,

drivers/net/phy/motorcomm.c

2923

phydev_dbg(phydev,

drivers/net/phy/mxl-86110.c

408

phydev_dbg(phydev,

drivers/net/phy/nxp-c45-tja11xx-macsec.c

1049

phydev_dbg(phydev, "update SecY SCI %016llx\n",

drivers/net/phy/nxp-c45-tja11xx-macsec.c

1088

phydev_dbg(phydev, "delete SecY SCI %016llx\n",

drivers/net/phy/nxp-c45-tja11xx-macsec.c

1122

phydev_dbg(phydev, "add RX SC SCI %016llx %s\n",

drivers/net/phy/nxp-c45-tja11xx-macsec.c

1152

phydev_dbg(phydev, "update RX SC SCI %016llx %s\n",

drivers/net/phy/nxp-c45-tja11xx-macsec.c

1172

phydev_dbg(phydev, "delete RX SC SCI %016llx %s\n",

drivers/net/phy/nxp-c45-tja11xx-macsec.c

1196

phydev_dbg(phydev, "add RX SA %u %s to RX SC SCI %016llx\n",

drivers/net/phy/nxp-c45-tja11xx-macsec.c

1226

phydev_dbg(phydev, "update RX SA %u %s to RX SC SCI %016llx\n",

drivers/net/phy/nxp-c45-tja11xx-macsec.c

1256

phydev_dbg(phydev, "delete RX SA %u %s to RX SC SCI %016llx\n",

drivers/net/phy/nxp-c45-tja11xx-macsec.c

1286

phydev_dbg(phydev, "add TX SA %u %s to TX SC %016llx\n",

drivers/net/phy/nxp-c45-tja11xx-macsec.c

1316

phydev_dbg(phydev, "update TX SA %u %s to TX SC %016llx\n",

drivers/net/phy/nxp-c45-tja11xx-macsec.c

1345

phydev_dbg(phydev, "delete TX SA %u %s to TX SC %016llx\n",

drivers/net/phy/nxp-c45-tja11xx-macsec.c

1711

phydev_dbg(phydev, "pn_wrapped: TX SC %d, encoding_sa %u\n",

drivers/net/phy/nxp-c45-tja11xx-macsec.c

298

phydev_dbg(phydev, "write addr 0x%x value 0x%x\n", addr, value);

drivers/net/phy/nxp-c45-tja11xx-macsec.c

334

phydev_dbg(phydev, "read addr 0x%x value 0x%x\n", addr, *value);

drivers/net/phy/nxp-c45-tja11xx-macsec.c

709

phydev_dbg(phydev, "XPN %s\n", phy_secy->secy->xpn ? "on" : "off");

drivers/net/phy/nxp-c45-tja11xx-macsec.c

715

phydev_dbg(phydev, "key len %u\n", phy_secy->secy->key_len);

drivers/net/phy/nxp-c45-tja11xx-macsec.c

721

phydev_dbg(phydev, "encryption %s\n",

drivers/net/phy/nxp-c45-tja11xx-macsec.c

728

phydev_dbg(phydev, "protect frames %s\n",

drivers/net/phy/nxp-c45-tja11xx-macsec.c

735

phydev_dbg(phydev, "send sci %s\n",

drivers/net/phy/nxp-c45-tja11xx-macsec.c

742

phydev_dbg(phydev, "end station %s\n",

drivers/net/phy/nxp-c45-tja11xx-macsec.c

749

phydev_dbg(phydev, "scb %s\n",

drivers/net/phy/nxp-c45-tja11xx-macsec.c

824

phydev_dbg(phydev, "validate frames %u\n",

drivers/net/phy/nxp-c45-tja11xx-macsec.c

826

phydev_dbg(phydev, "replay_protect %s window %u\n",

drivers/net/phy/nxp-c45-tja11xx-macsec.c

837

phydev_dbg(phydev, "rx_sc->active %s\n",

drivers/net/phy/nxp-c45-tja11xx-macsec.c

845

phydev_dbg(phydev, "key len %u\n", phy_secy->secy->key_len);

drivers/net/phy/nxp-c45-tja11xx-macsec.c

851

phydev_dbg(phydev, "XPN %s\n", phy_secy->secy->xpn ? "on" : "off");

drivers/net/phy/nxp-c45-tja11xx-macsec.c

981

phydev_dbg(phydev, "add SecY SCI %016llx\n",

drivers/net/phy/nxp-c45-tja11xx.c

1539

phydev_dbg(phydev, "Clause 45 managed PHY abilities 0x%x\n", ret);

drivers/net/phy/nxp-c45-tja11xx.c

1757

phydev_dbg(phydev, "the phy does not support PTP");

drivers/net/phy/nxp-c45-tja11xx.c

1774

phydev_dbg(phydev, "PTP support not enabled even if the phy supports it");

drivers/net/phy/nxp-c45-tja11xx.c

1786

phydev_dbg(phydev, "MACsec support enabled.");

drivers/net/phy/nxp-c45-tja11xx.c

1788

phydev_dbg(phydev, "MACsec support not enabled even if the phy supports it");

drivers/net/phy/phy.c

68

phydev_dbg(phydev, "PHY state change %s -> %s\n",

drivers/net/phy/phy_device.c

3408

phydev_dbg(phydev, "ignoring leds node defined with no PHY driver support\n");

drivers/net/phy/qcom/at803x.c

551

phydev_dbg(phydev, "%s(): phy was reset\n", __func__);

drivers/net/phy/realtek/realtek_main.c

628

phydev_dbg(phydev,

drivers/net/phy/realtek/realtek_main.c

632

phydev_dbg(phydev,

drivers/net/phy/realtek/realtek_main.c

645

phydev_dbg(phydev,

drivers/net/phy/realtek/realtek_main.c

649

phydev_dbg(phydev,

drivers/net/phy/smsc.c

505

phydev_dbg(phydev, "pattern not valid at %d\n", rc);