phy_clear_bits_mmd
return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_B10L_PMA_CTRL,
ret = phy_clear_bits_mmd(phydev, MDIO_MMD_AN, ADIN_FORCED_MODE, ADIN_FORCED_MODE_EN);
ret = phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H,
return phy_clear_bits_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_10T1L_CTRL,
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_SC,
err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_TXDIS,
return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR,
ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR,
phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
return phy_clear_bits_mmd(phydev, DP83869_DEVADDR,
return phy_clear_bits_mmd(phydev, DP83811_DEVADDR,
return phy_clear_bits_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,
ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PCS,
return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_TXDIS,
int ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PCS, MV_1GBX_CTRL,
return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
return phy_clear_bits_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1,
return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2,
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_BLINK_CTRL,
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL,
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_DIR, BIT(pin));
return phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));
ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL1, tmp);
ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL2, tmp);
return phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_EN, tmp);
ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));
ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));
return phy_clear_bits_mmd(clock->phydev, PTP_MMD(clock), reg,
ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, LAN887X_DSP_PMA_CONTROL,
ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_REG_REG26,
ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, regmap->cable_test,
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID, ID_ENABLE);
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID, ID_ENABLE);
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID,
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID,
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, TJA1120_EGRESS_TS_DATA_S,
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR,
ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, mask);
return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, RTL822X_VND2_TSALRM, 3);