pci_iomap
#define pci_iomap pci_iomap
void __iomem *pci_iomap(struct pci_dev *, int, unsigned long);
EXPORT_SYMBOL(pci_iomap);
#define pci_iomap pci_iomap
mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
barp = pci_iomap(pdev, 5, 0x10);
card->config_regs = pci_iomap(dev, 0, CONFIG_RAM_SIZE);
card->buffers = pci_iomap(dev, 1, DATA_RAM_SIZE);
bus->mmio = pci_iomap(dev, 0, ~0UL);
_iobase = pci_iomap(dev, 0, 0);
bar->virt_addr = pci_iomap(accel_pci_dev->pci_dev, bar_nr, 0);
bar->virt_addr = pci_iomap(accel_pci_dev->pci_dev, bar_nr, 0);
bar->virt_addr = pci_iomap(accel_pci_dev->pci_dev, bar_nr, 0);
bar->virt_addr = pci_iomap(accel_pci_dev->pci_dev, bar_nr, 0);
bar->virt_addr = pci_iomap(accel_pci_dev->pci_dev, bar_nr, 0);
bar->virt_addr = pci_iomap(accel_pci_dev->pci_dev, bar_nr, 0);
cpt->reg_base = pci_iomap(pdev, OTX_CPT_PF_PCI_CFG_BAR, 0);
cptvf->reg_base = pci_iomap(pdev, OTX_CPT_VF_PCI_CFG_BAR, 0);
idxd->reg_base = pci_iomap(pdev, IDXD_MMIO_BAR, 0);
regs = pd->membase = pci_iomap(pdev, 1, 0);
conf->map = pci_iomap(pdev, CVP_BAR, 0);
rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
xe->mmio.regs = pci_iomap(pdev, GTTMMADR_BAR, 0);
base_addr = pci_iomap(pdev, 1, 0);
vnic->bar[i].vaddr = pci_iomap(pdev, i, vnic->bar[i].len);
fc_pci->io_mem = pci_iomap(fc_pci->pdev, 0, 0x800);
cobalt->bar0 = pci_iomap(pci_dev, 0, 0);
cobalt->bar1 = pci_iomap(pci_dev, 1, 0);
cobalt->bar1 = pci_iomap(pci_dev, 2, 0);
dev->io_mem = pci_iomap(pdev, 0, pci_resource_len(pdev, 0));
pd->regs = pci_iomap(pdev, 0, pci_resource_len(pd->pdev, 0));
cis = pci_iomap(pdev, 1, 0);
pluto->io_mem = pci_iomap(pdev, 0, 0x40);
regs = pci_iomap(pdev, 0, 0);
mcam->regs = pci_iomap(pdev, 0, 0);
base = pci_iomap(parent, 0, LS7A_PCI_CFG_SIZE);
cd->mmio = pci_iomap(pci_dev, 0, 0);
cd->mmio = pci_iomap(pci_dev, 0, 0);
hw->mmio_vaddr = pci_iomap(pdev, 1, 0);
hw->db_vaddr = pci_iomap(pdev, 3, max_ccb * ONE_DB_SIZE);
chip->pch_phub_base_address = pci_iomap(pdev, 1, 0);
pht->caddr = pci_iomap(pdev, 0, 0);
pht->iaddr = pci_iomap(pdev, 2, 0);
pht->oaddr = pci_iomap(pdev, 3, 0);
pci_iomap(pci_dev, SDRICOH_PCI_REGION, SDRICOH_PCI_REGION_SIZE);
host->ioaddr = pci_iomap(pdev, 0, 0);
priv->start = pci_iomap(PCI_Device, 0, priv->asize);
cafe->mmio = pci_iomap(pdev, 0, 0);
addr = pci_iomap(pdev, c_can_pci_data->bar,
addr = pci_iomap(pdev, 1, pci_resource_len(pdev, 1));
bar0_base = pci_iomap(pdev, 0, pci_resource_len(pdev, 0));
card->addr = pci_iomap(pdev, PCI402_BAR, PCI402_IO_LEN_TOTAL);
pcie->reg_base = pci_iomap(pdev, 0, 0);
pciefd->reg_base = pci_iomap(pdev, 0, PCIEFD_BAR0_SIZE);
card->conf_addr = pci_iomap(pdev, conf_bar, conf_size);
card->base_addr = pci_iomap(pdev, base_bar, EMS_PCI_BASE_SIZE);
conf_addr = pci_iomap(pdev, 0, PCI_CONFIG_PORT_SIZE);
res_addr = pci_iomap(pdev, 2, PCI_PORT_XILINX_SIZE);
base_addr = pci_iomap(pdev, 1, PCI_PORT_SIZE);
cfg_base = pci_iomap(pdev, 0, PEAK_PCI_CFG_SIZE);
reg_base = pci_iomap(pdev, 1, PEAK_PCI_CHAN_SIZE * channels);
reset_addr = pci_iomap(pdev, reset_bar[i], 0);
addr = pci_iomap(pdev, chan_map->bar, chan_map->size);
bar0_addr = pci_iomap(pdev, 0, 0);
addr = pci_iomap(pdev, ci->conf_map.bar, ci->conf_map.size);
addr = pci_iomap(pdev, cm->bar, cm->size);
ioaddr = pci_iomap(pdev, pci_bar, 0);
ioaddr = pci_iomap(pdev, 0, 0);
vp->cb_fn_base = pci_iomap(pdev, 2, 0);
void __iomem *ioaddr = pci_iomap(pdev, 1, 128);
ioaddr = pci_iomap(pdev, use_mmio, 128);
bars[j].vaddr = pci_iomap(pdev, i, bars[j].len);
adapter->hw.hw_addr = pci_iomap(pdev, BAR_0, 0);
adapter->hw.hw_addr = pci_iomap(pdev, 0, 0);
bd->bar1 = pci_iomap(bd->pdev, 2, bd->db_size);
bp->regview = pci_iomap(pdev, 0, MB_GET_CID_ADDR(TX_TSS_CID +
bp->bar1 = pci_iomap(bp->pdev, 2, bp->db_size);
enic->bar[i].vaddr = pci_iomap(pdev, i, enic->bar[i].len);
db->ioaddr = pci_iomap(pdev, 0, 0);
ioaddr = pci_iomap(pdev, 0, 0);
ioaddr = pci_iomap(pdev, TULIP_BAR, netdev_res_size);
private->ioaddr = pci_iomap(pdev, 0, 0);
ioaddr = pci_iomap(pdev, 0, 0);
ioaddr = pci_iomap(pdev, 1, 0);
ioaddr = pci_iomap(pdev, bar, netdev_io_size);
io = pci_iomap(dev, 0, 0);
dma_io = pci_iomap(dev, 2, 0);
adapter->csr = pci_iomap(pdev, 2, 0);
addr = pci_iomap(pdev, db_bar(adapter), 0);
addr = pci_iomap(pdev, BE2_chip(adapter) ? 1 : 0, 0);
ioaddr = pci_iomap(pdev, bar, len);
port_regs = pci_iomap(pdev, 0, 0);
reg_bar = pci_iomap(pdev, GVE_REGISTER_BAR, 0);
db_bar = pci_iomap(pdev, GVE_DOORBELL_BAR, 0);
hw->hw.io_base = pci_iomap(pdev, 2, 0);
nic->csr = pci_iomap(pdev, (use_io ? 1 : 0), sizeof(struct csr));
adapter->io_addr = pci_iomap(pdev, 0, 0);
bar0_va = pci_iomap(pdev, bar, 0);
ioaddr = pci_iomap(pdev, bar, YELLOWFIN_SIZE);
bars[j].vaddr = pci_iomap(pdev, i, bars[j].len);
ioaddr = pci_iomap(pdev, bar, io_size);
ioaddr = pci_iomap(pdev, bar, 0);
port_base = pci_iomap(pdev, SC92031_USE_PIO, 0);
ioaddr = pci_iomap(pci_dev, 0, 0);
ioaddr = pci_iomap(pdev, EPIC_BAR, 0);
cp->regs = pci_iomap(pdev, 0, casreg_len);
regs = pci_iomap(pdev, 0, TN40_REGS_SIZE);
ioaddr = pci_iomap(pdev, (quirks & rqNeedEnMMIO ? 1 : 0), io_size);
priv->map = pci_iomap(pdev, 1, mem_len);
priv->map = pci_iomap(pdev, 0, io_len);
ar_pci->mem = pci_iomap(pdev, BAR_NUM, 0);
ab->mem = pci_iomap(pdev, ATH11K_PCI_BAR_NUM, 0);
ab->mem = pci_iomap(pdev, ATH12K_PCI_BAR_NUM, 0);
mem = pci_iomap(pdev, 0, 0);
mem = pci_iomap(pdev, 0, 0);
ioaddr = pci_iomap(pci_dev, 0, 0);
card->pci_mmap = pci_iomap(pdev, 0, 0);
card->pci_mmap1 = pci_iomap(pdev, 2, 0);
priv->sram = pci_iomap(pdev, 0, 0x10000);
priv->regs = pci_iomap(pdev, 1, 0x10000);
priv->regs = pci_iomap(pdev, 2, 0x10000);
priv->map = pci_iomap(pdev, 1, mem_len);
priv->map = pci_iomap(pdev, 0, io_len);
(unsigned long)pci_iomap(pdev,
rtwpci->mmap = pci_iomap(pdev, bar_id, len);
rtwpci->mmap = pci_iomap(pdev, bar_id, resource_len);
ndev->self_mmio = pci_iomap(pdev, 0, 0);
ndev->ctrl_reg = pci_iomap(pdev, ndev->barno_map[BAR_CONFIG], 0);
ndev->peer_spad_reg = pci_iomap(pdev,
ndev->db_reg = pci_iomap(pdev, ndev->barno_map[BAR_DB], 0);
ndev->peer_mmio = pci_iomap(pdev, b2b_bar,
ndev->self_mmio = pci_iomap(pdev, 0, 0);
sndev->peer_shared = pci_iomap(sndev->stdev->pdev, self_bar, LUT_SIZE);
membar2 = pci_iomap(dev, VMD_MEMBAR2, 0);
mapping = pci_iomap(pdev, bar, maxlen);
res->baseaddr = pci_iomap(pdev, bar, 0);
EXPORT_SYMBOL(pci_iomap);
void __iomem *regs = pci_iomap(dev, 0, 0);
mmio_base = pci_iomap(dev, 0, 0);
bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg));
bar = pci_iomap(pdev, 0, 0);
mmio = pci_iomap(pdev, 0, 0);
map = pci_iomap(pdev, 0, 0x23000);
tw_dev->base_addr = pci_iomap(pdev, 1, 0);
esp->regs = pci_iomap(pdev, 0, pci_resource_len(pdev, 0));
bfad->pci_bar0_kva = pci_iomap(pdev, 0, pci_resource_len(pdev, 0));
bfad->pci_bar2_kva = pci_iomap(pdev, 2, pci_resource_len(pdev, 2));
hba->regview = pci_iomap(hba->pcidev, 0, BNX2_MQ_CONFIG2);
hba->regview = pci_iomap(hba->pcidev, 0, 4096);
fnic->bar0.vaddr = pci_iomap(pdev, 0, 0);
addr_array[i] = pci_iomap(dev, i, 0);
mapped_pci_addr = pci_iomap(pdev, 0, 0);
snic->bar0.vaddr = pci_iomap(pdev, 0, 0);
device->s.ioaddr = pci_iomap(pdev, 1,
device->s.ioaddr = pci_iomap(pdev, 0,
device->s.ramaddr = pci_iomap(pdev, i,
adapter->mmioBase = pci_iomap(pdev, i, PVSCSI_MEM_SPACE_SIZE);
wd->base = pci_iomap(pdev, 0, 0);
data->io_remap_addr = pci_iomap(board_dat->pdev, 1, 0);
mmio = pci_iomap(bus->host_pci, 0, ~0UL);
dc->base_addr = pci_iomap(dc->pdev, 0, dc->card_type);
p = pci_iomap(dev, 0, 5);
membase = pci_iomap(priv->pdev, 1, 0);
info->priv = pci_iomap(pdev, 0, 0);
tbl[bar] = pci_iomap(pdev, bar, pci_resource_len(pdev, bar));
io = pci_iomap(pdev, 0, 0);
io = pci_iomap(pdev, bar, 0);
par->mmio_base = pci_iomap(dev, 1, 0);
ne_pci_dev->iomem_base = pci_iomap(pdev, PCI_BAR_NE, 0);
ldev->ioaddr = pci_iomap(pci_dev, 0, 0);
pci_mem_addr = pci_iomap(dev, 1, 0x80);
extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20);