of_for_each_phandle
of_for_each_phandle(&it, err, np, "access-controllers", "#access-controller-cells", 0) {
of_for_each_phandle(&it, rc, node, "clocks", "#clock-cells", -1) {
of_for_each_phandle(&it, err, wakeup_node, "wakeup-source", NULL, 0) {
of_for_each_phandle(&it, err, np, "nvidia,outputs", NULL, 0)
of_for_each_phandle(&it, rc, sgrp, "sensors", NULL, 0)
of_for_each_phandle(it, err, dev->of_node, "mmu-masters",
of_for_each_phandle(&it, err, dev->of_node, "memory-region", NULL, 0) {
of_for_each_phandle(&it, ret, dev->of_node, "msi-parent", "#msi-cells", -1) {
of_for_each_phandle(&it, err, node, "ti,unmapped-event-sources", NULL, 0) {
of_for_each_phandle(&it, rc, np, list_name, cells_name, cell_count) {
of_for_each_phandle(&it, rc, of_node, "memory-region", NULL, 0) {
of_for_each_phandle(&it, err, np, "msi-parent", "#msi-cells", 0) {
of_for_each_phandle(&it, ret, dev_of_node(cspmu->dev), "cpus", NULL, 0) {
of_for_each_phandle(&it, ret, node, "power-domains", "#power-domain-cells", -1) {
of_for_each_phandle(&it, ret, dn, "domain-idle-states", NULL, 0) {
of_for_each_phandle(&it, err, dev->of_node, SUNXI_SRAM_PROP,
of_for_each_phandle(&it, err, dev->of_node, SUNXI_SRAM_PROP,
of_for_each_phandle(&it, err, dn, "link", NULL, 0) {
of_for_each_phandle(&it, rc, node, "dais", NULL, 0) {
of_for_each_phandle(&it, rc, node, "links", NULL, 0) {