drivers/gpu/drm/nouveau/nvkm/core/engine.c
173
nvkm_debug(&engine->subdev, "disabled\n");
drivers/gpu/drm/nouveau/nvkm/core/firmware.c
100
nvkm_debug(subdev, "firmware \"%s\" unavailable\n", f);
drivers/gpu/drm/nouveau/nvkm/core/firmware.c
95
nvkm_debug(subdev, "firmware \"%s\" loaded - %zu byte(s)\n",
drivers/gpu/drm/nouveau/nvkm/core/intr.c
112
nvkm_debug(intr->subdev, "intr %d/%08x allowed by %s\n", leaf, mask, subdev->name);
drivers/gpu/drm/nouveau/nvkm/core/intr.c
138
nvkm_debug(intr->subdev, "intr %d/%08x blocked by %s\n", leaf, mask, subdev->name);
drivers/gpu/drm/nouveau/nvkm/core/intr.c
215
nvkm_debug(intr->subdev, "intr%d: %08x\n",
drivers/gpu/drm/nouveau/nvkm/core/intr.c
434
nvkm_debug(intr->subdev, "intr %d/%08x requested by %s\n",
drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c
1019
nvkm_debug(subdev, "supervisor %d\n", ffs(disp->super.pending));
drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c
846
nvkm_debug(subdev, "supervisor %d: %08x\n", ffs(disp->super.pending), stat);
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
1376
nvkm_debug(subdev, "supervisor %08x %08x\n", disp->super.pending, super);
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
1598
nvkm_debug(subdev, "Window(s): %d (%08lx)\n", disp->wndw.nr, disp->wndw.mask);
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
1602
nvkm_debug(subdev, " Head(s): %d (%02lx)\n", disp->head.nr, disp->head.mask);
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
1611
nvkm_debug(subdev, " DAC(s): %d (%02lx)\n", disp->dac.nr, disp->dac.mask);
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
1621
nvkm_debug(subdev, " PIOR(s): %d (%02lx)\n", disp->pior.nr, disp->pior.mask);
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
1630
nvkm_debug(subdev, " SOR(s): %d (%02lx)\n", disp->sor.nr, disp->sor.mask);
drivers/gpu/drm/nouveau/nvkm/engine/falcon.c
152
nvkm_debug(subdev, "falcon version: %d\n", falcon->version);
drivers/gpu/drm/nouveau/nvkm/engine/falcon.c
153
nvkm_debug(subdev, "secret level: %d\n", falcon->secret);
drivers/gpu/drm/nouveau/nvkm/engine/falcon.c
154
nvkm_debug(subdev, "code limit: %d\n", falcon->code.limit);
drivers/gpu/drm/nouveau/nvkm/engine/falcon.c
155
nvkm_debug(subdev, "data limit: %d\n", falcon->data.limit);
drivers/gpu/drm/nouveau/nvkm/engine/falcon.c
243
nvkm_debug(subdev, "firmware: %s (%s)\n", name, falcon->data.data ?
drivers/gpu/drm/nouveau/nvkm/engine/falcon.c
82
nvkm_debug(subdev, "ucode halted\n");
drivers/gpu/drm/nouveau/nvkm/engine/gr/ga102.c
288
nvkm_debug(subdev, "netlist version %d, %d regions\n",
drivers/gpu/drm/nouveau/nvkm/engine/gr/ga102.c
298
nvkm_debug(subdev, "\t%2d: %08x %08x\n",
drivers/gpu/drm/nouveau/nvkm/engine/sec2/ga102.c
88
nvkm_debug(subdev, "%s booted\n", name);
drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c
54
nvkm_debug(subdev, "%s booted\n", name);
drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c
73
nvkm_debug(subdev, "Enabling FIFO_CTRL\n");
drivers/gpu/drm/nouveau/nvkm/falcon/base.c
293
nvkm_debug(falcon->user, "released %s falcon\n", falcon->name);
drivers/gpu/drm/nouveau/nvkm/falcon/base.c
312
nvkm_debug(user, "acquired %s falcon\n", falcon->name);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
100
nvkm_debug(subdev, "\tappCodeOff : 0x%x\n", hdr->app_code_off);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
101
nvkm_debug(subdev, "\tappCodeSize : 0x%x\n", hdr->app_code_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
102
nvkm_debug(subdev, "\tappDataOff : 0x%x\n", hdr->app_data_off);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
103
nvkm_debug(subdev, "\tappDataSize : 0x%x\n", hdr->app_data_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
104
nvkm_debug(subdev, "\tflags : 0x%x\n", hdr->flags);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
124
nvkm_debug(subdev, "acrDesc\n");
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
125
nvkm_debug(subdev, "\twprRegionId : %d\n", hdr->wpr_region_id);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
126
nvkm_debug(subdev, "\twprOffset : 0x%x\n", hdr->wpr_offset);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
127
nvkm_debug(subdev, "\tmmuMemRange : 0x%x\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
129
nvkm_debug(subdev, "\tnoRegions : %d\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
133
nvkm_debug(subdev, "\tregion[%d] :\n", i);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
134
nvkm_debug(subdev, "\t startAddr : 0x%x\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
136
nvkm_debug(subdev, "\t endAddr : 0x%x\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
138
nvkm_debug(subdev, "\t regionId : %d\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
140
nvkm_debug(subdev, "\t readMask : 0x%x\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
142
nvkm_debug(subdev, "\t writeMask : 0x%x\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
144
nvkm_debug(subdev, "\t clientMask : 0x%x\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
148
nvkm_debug(subdev, "\tucodeBlobSize: %d\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
150
nvkm_debug(subdev, "\tucodeBlobBase: 0x%llx\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
152
nvkm_debug(subdev, "\tvprEnabled : %d\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
154
nvkm_debug(subdev, "\tvprStart : 0x%x\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
156
nvkm_debug(subdev, "\tvprEnd : 0x%x\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
158
nvkm_debug(subdev, "\thdcpPolicies : 0x%x\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
167
nvkm_debug(subdev, "acrDesc\n");
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
168
nvkm_debug(subdev, "\twprRegionId : %d\n", hdr->wpr_region_id);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
169
nvkm_debug(subdev, "\twprOffset : 0x%x\n", hdr->wpr_offset);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
170
nvkm_debug(subdev, "\tmmuMemoryRange : 0x%x\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
172
nvkm_debug(subdev, "\tnoRegions : %d\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
176
nvkm_debug(subdev, "\tregion[%d] :\n", i);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
177
nvkm_debug(subdev, "\t startAddr : 0x%x\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
179
nvkm_debug(subdev, "\t endAddr : 0x%x\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
181
nvkm_debug(subdev, "\t regionId : %d\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
183
nvkm_debug(subdev, "\t readMask : 0x%x\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
185
nvkm_debug(subdev, "\t writeMask : 0x%x\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
187
nvkm_debug(subdev, "\t clientMask : 0x%x\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
189
nvkm_debug(subdev, "\t shadowMemStartAddr: 0x%x\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
193
nvkm_debug(subdev, "\tucodeBlobSize : %d\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
195
nvkm_debug(subdev, "\tucodeBlobBase : 0x%llx\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
197
nvkm_debug(subdev, "\tvprEnabled : %d\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
199
nvkm_debug(subdev, "\tvprStart : 0x%x\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
201
nvkm_debug(subdev, "\tvprEnd : 0x%x\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
203
nvkm_debug(subdev, "\thdcpPolicies : 0x%x\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
28
nvkm_debug(subdev, "wprHeader\n");
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
29
nvkm_debug(subdev, "\tfalconID : %d\n", hdr->falcon_id);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
30
nvkm_debug(subdev, "\tlsbOffset : 0x%x\n", hdr->lsb_offset);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
31
nvkm_debug(subdev, "\tbootstrapOwner: %d\n", hdr->bootstrap_owner);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
32
nvkm_debug(subdev, "\tlazyBootstrap : %d\n", hdr->lazy_bootstrap);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
33
nvkm_debug(subdev, "\tstatus : %d\n", hdr->status);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
39
nvkm_debug(subdev, "wprHeader\n");
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
40
nvkm_debug(subdev, "\tfalconID : %d\n", hdr->falcon_id);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
41
nvkm_debug(subdev, "\tlsbOffset : 0x%x\n", hdr->lsb_offset);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
42
nvkm_debug(subdev, "\tbootstrapOwner: %d\n", hdr->bootstrap_owner);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
43
nvkm_debug(subdev, "\tlazyBootstrap : %d\n", hdr->lazy_bootstrap);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
44
nvkm_debug(subdev, "\tbinVersion : %d\n", hdr->bin_version);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
45
nvkm_debug(subdev, "\tstatus : %d\n", hdr->status);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
51
nvkm_debug(subdev, "wprGenericHeader\n");
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
52
nvkm_debug(subdev, "\tidentifier : %04x\n", hdr->identifier);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
53
nvkm_debug(subdev, "\tversion : %04x\n", hdr->version);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
54
nvkm_debug(subdev, "\tsize : %08x\n", hdr->size);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
68
nvkm_debug(subdev, "lsbHeader\n");
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
69
nvkm_debug(subdev, "\tucodeOff : 0x%x\n", hdr->ucode_off);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
70
nvkm_debug(subdev, "\tucodeSize : 0x%x\n", hdr->ucode_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
71
nvkm_debug(subdev, "\tdataSize : 0x%x\n", hdr->data_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
72
nvkm_debug(subdev, "\tblCodeSize : 0x%x\n", hdr->bl_code_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
73
nvkm_debug(subdev, "\tblImemOff : 0x%x\n", hdr->bl_imem_off);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
74
nvkm_debug(subdev, "\tblDataOff : 0x%x\n", hdr->bl_data_off);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
75
nvkm_debug(subdev, "\tblDataSize : 0x%x\n", hdr->bl_data_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
76
nvkm_debug(subdev, "\treserved0 : %08x\n", hdr->rsvd0);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
77
nvkm_debug(subdev, "\tappCodeOff : 0x%x\n", hdr->app_code_off);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
78
nvkm_debug(subdev, "\tappCodeSize : 0x%x\n", hdr->app_code_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
79
nvkm_debug(subdev, "\tappDataOff : 0x%x\n", hdr->app_data_off);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
80
nvkm_debug(subdev, "\tappDataSize : 0x%x\n", hdr->app_data_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
81
nvkm_debug(subdev, "\tappImemOffset : 0x%x\n", hdr->app_imem_offset);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
82
nvkm_debug(subdev, "\tappDmemOffset : 0x%x\n", hdr->app_dmem_offset);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
83
nvkm_debug(subdev, "\tflags : 0x%x\n", hdr->flags);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
84
nvkm_debug(subdev, "\tmonitorCodeOff: 0x%x\n", hdr->monitor_code_offset);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
85
nvkm_debug(subdev, "\tmonitorDataOff: 0x%x\n", hdr->monitor_data_offset);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
86
nvkm_debug(subdev, "\tmanifestOffset: 0x%x\n", hdr->manifest_offset);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
92
nvkm_debug(subdev, "lsbHeader\n");
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
93
nvkm_debug(subdev, "\tucodeOff : 0x%x\n", hdr->ucode_off);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
94
nvkm_debug(subdev, "\tucodeSize : 0x%x\n", hdr->ucode_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
95
nvkm_debug(subdev, "\tdataSize : 0x%x\n", hdr->data_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
96
nvkm_debug(subdev, "\tblCodeSize : 0x%x\n", hdr->bl_code_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
97
nvkm_debug(subdev, "\tblImemOff : 0x%x\n", hdr->bl_imem_off);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
98
nvkm_debug(subdev, "\tblDataOff : 0x%x\n", hdr->bl_data_off);
drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c
99
nvkm_debug(subdev, "\tblDataSize : 0x%x\n", hdr->bl_data_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
100
nvkm_debug(subdev, "\tnonSecCodeSize: 0x%x\n", hdr->non_sec_code_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
101
nvkm_debug(subdev, "\tsecCodeOff : 0x%x\n", hdr->sec_code_off);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
102
nvkm_debug(subdev, "\tsecCodeSize : 0x%x\n", hdr->sec_code_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
103
nvkm_debug(subdev, "\tcodeEntryPoint: 0x%x\n", hdr->code_entry_point);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
104
nvkm_debug(subdev, "\tdataDmaBase : 0x%llx\n", hdr->data_dma_base);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
105
nvkm_debug(subdev, "\tdataSize : 0x%x\n", hdr->data_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
113
nvkm_debug(subdev, "\targc : 0x%08x\n", hdr->argc);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
114
nvkm_debug(subdev, "\targv : 0x%08x\n", hdr->argv);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
28
nvkm_debug(subdev, "loaderConfig\n");
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
29
nvkm_debug(subdev, "\tdmaIdx : %d\n", hdr->dma_idx);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
30
nvkm_debug(subdev, "\tcodeDmaBase : 0x%xx\n", hdr->code_dma_base);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
31
nvkm_debug(subdev, "\tcodeSizeTotal : 0x%x\n", hdr->code_size_total);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
32
nvkm_debug(subdev, "\tcodeSizeToLoad: 0x%x\n", hdr->code_size_to_load);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
33
nvkm_debug(subdev, "\tcodeEntryPoint: 0x%x\n", hdr->code_entry_point);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
34
nvkm_debug(subdev, "\tdataDmaBase : 0x%x\n", hdr->data_dma_base);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
35
nvkm_debug(subdev, "\tdataSize : 0x%x\n", hdr->data_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
36
nvkm_debug(subdev, "\toverlayDmaBase: 0x%x\n", hdr->overlay_dma_base);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
37
nvkm_debug(subdev, "\targc : 0x%08x\n", hdr->argc);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
38
nvkm_debug(subdev, "\targv : 0x%08x\n", hdr->argv);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
39
nvkm_debug(subdev, "\tcodeDmaBase1 : 0x%x\n", hdr->code_dma_base1);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
40
nvkm_debug(subdev, "\tdataDmaBase1 : 0x%x\n", hdr->data_dma_base1);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
41
nvkm_debug(subdev, "\tovlyDmaBase1 : 0x%x\n", hdr->overlay_dma_base1);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
48
nvkm_debug(subdev, "loaderConfig\n");
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
49
nvkm_debug(subdev, "\treserved : 0x%08x\n", hdr->reserved);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
50
nvkm_debug(subdev, "\tdmaIdx : %d\n", hdr->dma_idx);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
51
nvkm_debug(subdev, "\tcodeDmaBase : 0x%llxx\n", hdr->code_dma_base);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
52
nvkm_debug(subdev, "\tcodeSizeTotal : 0x%x\n", hdr->code_size_total);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
53
nvkm_debug(subdev, "\tcodeSizeToLoad: 0x%x\n", hdr->code_size_to_load);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
54
nvkm_debug(subdev, "\tcodeEntryPoint: 0x%x\n", hdr->code_entry_point);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
55
nvkm_debug(subdev, "\tdataDmaBase : 0x%llx\n", hdr->data_dma_base);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
56
nvkm_debug(subdev, "\tdataSize : 0x%x\n", hdr->data_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
57
nvkm_debug(subdev, "\toverlayDmaBase: 0x%llx\n", hdr->overlay_dma_base);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
58
nvkm_debug(subdev, "\targc : 0x%08x\n", hdr->argc);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
59
nvkm_debug(subdev, "\targv : 0x%08x\n", hdr->argv);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
66
nvkm_debug(subdev, "flcnBlDmemDesc\n");
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
67
nvkm_debug(subdev, "\treserved : 0x%08x 0x%08x 0x%08x 0x%08x\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
70
nvkm_debug(subdev, "\tsignature : 0x%08x 0x%08x 0x%08x 0x%08x\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
73
nvkm_debug(subdev, "\tctxDma : %d\n", hdr->ctx_dma);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
74
nvkm_debug(subdev, "\tcodeDmaBase : 0x%x\n", hdr->code_dma_base);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
75
nvkm_debug(subdev, "\tnonSecCodeOff : 0x%x\n", hdr->non_sec_code_off);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
76
nvkm_debug(subdev, "\tnonSecCodeSize: 0x%x\n", hdr->non_sec_code_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
77
nvkm_debug(subdev, "\tsecCodeOff : 0x%x\n", hdr->sec_code_off);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
78
nvkm_debug(subdev, "\tsecCodeSize : 0x%x\n", hdr->sec_code_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
79
nvkm_debug(subdev, "\tcodeEntryPoint: 0x%x\n", hdr->code_entry_point);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
80
nvkm_debug(subdev, "\tdataDmaBase : 0x%x\n", hdr->data_dma_base);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
81
nvkm_debug(subdev, "\tdataSize : 0x%x\n", hdr->data_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
82
nvkm_debug(subdev, "\tcodeDmaBase1 : 0x%x\n", hdr->code_dma_base1);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
83
nvkm_debug(subdev, "\tdataDmaBase1 : 0x%x\n", hdr->data_dma_base1);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
90
nvkm_debug(subdev, "flcnBlDmemDesc\n");
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
91
nvkm_debug(subdev, "\treserved : 0x%08x 0x%08x 0x%08x 0x%08x\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
94
nvkm_debug(subdev, "\tsignature : 0x%08x 0x%08x 0x%08x 0x%08x\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
97
nvkm_debug(subdev, "\tctxDma : %d\n", hdr->ctx_dma);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
98
nvkm_debug(subdev, "\tcodeDmaBase : 0x%llx\n", hdr->code_dma_base);
drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.c
99
nvkm_debug(subdev, "\tnonSecCodeOff : 0x%x\n", hdr->non_sec_code_off);
drivers/gpu/drm/nouveau/nvkm/nvfw/fw.c
29
nvkm_debug(subdev, "binHdr:\n");
drivers/gpu/drm/nouveau/nvkm/nvfw/fw.c
30
nvkm_debug(subdev, "\tbinMagic : 0x%08x\n", hdr->bin_magic);
drivers/gpu/drm/nouveau/nvkm/nvfw/fw.c
31
nvkm_debug(subdev, "\tbinVer : %d\n", hdr->bin_ver);
drivers/gpu/drm/nouveau/nvkm/nvfw/fw.c
32
nvkm_debug(subdev, "\tbinSize : %d\n", hdr->bin_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/fw.c
33
nvkm_debug(subdev, "\theaderOffset : 0x%x\n", hdr->header_offset);
drivers/gpu/drm/nouveau/nvkm/nvfw/fw.c
34
nvkm_debug(subdev, "\tdataOffset : 0x%x\n", hdr->data_offset);
drivers/gpu/drm/nouveau/nvkm/nvfw/fw.c
35
nvkm_debug(subdev, "\tdataSize : 0x%x\n", hdr->data_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/fw.c
43
nvkm_debug(subdev, "blDesc\n");
drivers/gpu/drm/nouveau/nvkm/nvfw/fw.c
44
nvkm_debug(subdev, "\tstartTag : 0x%x\n", hdr->start_tag);
drivers/gpu/drm/nouveau/nvkm/nvfw/fw.c
45
nvkm_debug(subdev, "\tdmemLoadOff : 0x%x\n", hdr->dmem_load_off);
drivers/gpu/drm/nouveau/nvkm/nvfw/fw.c
46
nvkm_debug(subdev, "\tcodeOff : 0x%x\n", hdr->code_off);
drivers/gpu/drm/nouveau/nvkm/nvfw/fw.c
47
nvkm_debug(subdev, "\tcodeSize : 0x%x\n", hdr->code_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/fw.c
48
nvkm_debug(subdev, "\tdataOff : 0x%x\n", hdr->data_off);
drivers/gpu/drm/nouveau/nvkm/nvfw/fw.c
49
nvkm_debug(subdev, "\tdataSize : 0x%x\n", hdr->data_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/hs.c
29
nvkm_debug(subdev, "hsHeader:\n");
drivers/gpu/drm/nouveau/nvkm/nvfw/hs.c
30
nvkm_debug(subdev, "\tsigDbgOffset : 0x%x\n", hdr->sig_dbg_offset);
drivers/gpu/drm/nouveau/nvkm/nvfw/hs.c
31
nvkm_debug(subdev, "\tsigDbgSize : 0x%x\n", hdr->sig_dbg_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/hs.c
32
nvkm_debug(subdev, "\tsigProdOffset : 0x%x\n", hdr->sig_prod_offset);
drivers/gpu/drm/nouveau/nvkm/nvfw/hs.c
33
nvkm_debug(subdev, "\tsigProdSize : 0x%x\n", hdr->sig_prod_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/hs.c
34
nvkm_debug(subdev, "\tpatchLoc : 0x%x\n", hdr->patch_loc);
drivers/gpu/drm/nouveau/nvkm/nvfw/hs.c
35
nvkm_debug(subdev, "\tpatchSig : 0x%x\n", hdr->patch_sig);
drivers/gpu/drm/nouveau/nvkm/nvfw/hs.c
36
nvkm_debug(subdev, "\thdrOffset : 0x%x\n", hdr->hdr_offset);
drivers/gpu/drm/nouveau/nvkm/nvfw/hs.c
37
nvkm_debug(subdev, "\thdrSize : 0x%x\n", hdr->hdr_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/hs.c
46
nvkm_debug(subdev, "hsHeader:\n");
drivers/gpu/drm/nouveau/nvkm/nvfw/hs.c
47
nvkm_debug(subdev, "\tsigProdOffset : 0x%x\n", hdr->sig_prod_offset);
drivers/gpu/drm/nouveau/nvkm/nvfw/hs.c
48
nvkm_debug(subdev, "\tsigProdSize : 0x%x\n", hdr->sig_prod_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/hs.c
49
nvkm_debug(subdev, "\tpatchLoc : 0x%x\n", hdr->patch_loc);
drivers/gpu/drm/nouveau/nvkm/nvfw/hs.c
50
nvkm_debug(subdev, "\tpatchSig : 0x%x\n", hdr->patch_sig);
drivers/gpu/drm/nouveau/nvkm/nvfw/hs.c
51
nvkm_debug(subdev, "\tmetadataOffset : 0x%x\n", hdr->meta_data_offset);
drivers/gpu/drm/nouveau/nvkm/nvfw/hs.c
52
nvkm_debug(subdev, "\tmetadataSize : 0x%x\n", hdr->meta_data_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/hs.c
53
nvkm_debug(subdev, "\tnumSig : 0x%x\n", hdr->num_sig);
drivers/gpu/drm/nouveau/nvkm/nvfw/hs.c
54
nvkm_debug(subdev, "\theaderOffset : 0x%x\n", hdr->header_offset);
drivers/gpu/drm/nouveau/nvkm/nvfw/hs.c
55
nvkm_debug(subdev, "\theaderSize : 0x%x\n", hdr->header_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/hs.c
65
nvkm_debug(subdev, "hsLoadHeader:\n");
drivers/gpu/drm/nouveau/nvkm/nvfw/hs.c
66
nvkm_debug(subdev, "\tnonSecCodeOff : 0x%x\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/hs.c
68
nvkm_debug(subdev, "\tnonSecCodeSize : 0x%x\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/hs.c
70
nvkm_debug(subdev, "\tdataDmaBase : 0x%x\n", hdr->data_dma_base);
drivers/gpu/drm/nouveau/nvkm/nvfw/hs.c
71
nvkm_debug(subdev, "\tdataSize : 0x%x\n", hdr->data_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/hs.c
72
nvkm_debug(subdev, "\tnumApps : 0x%x\n", hdr->num_apps);
drivers/gpu/drm/nouveau/nvkm/nvfw/hs.c
74
nvkm_debug(subdev,
drivers/gpu/drm/nouveau/nvkm/nvfw/hs.c
88
nvkm_debug(subdev, "hsLoadHeader:\n");
drivers/gpu/drm/nouveau/nvkm/nvfw/hs.c
89
nvkm_debug(subdev, "\tosCodeOffset : 0x%x\n", hdr->os_code_offset);
drivers/gpu/drm/nouveau/nvkm/nvfw/hs.c
90
nvkm_debug(subdev, "\tosCodeSize : 0x%x\n", hdr->os_code_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/hs.c
91
nvkm_debug(subdev, "\tosDataOffset : 0x%x\n", hdr->os_data_offset);
drivers/gpu/drm/nouveau/nvkm/nvfw/hs.c
92
nvkm_debug(subdev, "\tosDataSize : 0x%x\n", hdr->os_data_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/hs.c
93
nvkm_debug(subdev, "\tnumApps : 0x%x\n", hdr->num_apps);
drivers/gpu/drm/nouveau/nvkm/nvfw/hs.c
95
nvkm_debug(subdev,
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
102
nvkm_debug(subdev, "\tloadOvl[%2d] : 0x%x %d\n", i,
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
105
nvkm_debug(subdev, "\tcompressed : %d\n", hdr->compressed);
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
117
nvkm_debug(subdev, "lsUcodeImgDesc:\n");
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
118
nvkm_debug(subdev, "\tdescriptorSize : %d\n", hdr->descriptor_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
119
nvkm_debug(subdev, "\timageSize : %d\n", hdr->image_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
120
nvkm_debug(subdev, "\ttoolsVersion : 0x%x\n", hdr->tools_version);
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
121
nvkm_debug(subdev, "\tappVersion : 0x%x\n", hdr->app_version);
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
124
nvkm_debug(subdev, "\tdate : %s\n", date);
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
127
nvkm_debug(subdev, "\tsecureBootloader : 0x%x\n", hdr->secure_bootloader);
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
128
nvkm_debug(subdev, "\tbootloaderStartOffset: 0x%x\n", hdr->bootloader_start_offset);
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
129
nvkm_debug(subdev, "\tbootloaderSize : 0x%x\n", hdr->bootloader_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
130
nvkm_debug(subdev, "\tbootloaderImemOffset : 0x%x\n", hdr->bootloader_imem_offset);
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
131
nvkm_debug(subdev, "\tbootloaderEntryPoint : 0x%x\n", hdr->bootloader_entry_point);
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
133
nvkm_debug(subdev, "\tappStartOffset : 0x%x\n", hdr->app_start_offset);
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
134
nvkm_debug(subdev, "\tappSize : 0x%x\n", hdr->app_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
135
nvkm_debug(subdev, "\tappImemOffset : 0x%x\n", hdr->app_imem_offset);
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
136
nvkm_debug(subdev, "\tappImemEntry : 0x%x\n", hdr->app_imem_entry);
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
137
nvkm_debug(subdev, "\tappDmemOffset : 0x%x\n", hdr->app_dmem_offset);
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
138
nvkm_debug(subdev, "\tappResidentCodeOffset: 0x%x\n", hdr->app_resident_code_offset);
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
139
nvkm_debug(subdev, "\tappResidentCodeSize : 0x%x\n", hdr->app_resident_code_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
140
nvkm_debug(subdev, "\tappResidentDataOffset: 0x%x\n", hdr->app_resident_data_offset);
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
141
nvkm_debug(subdev, "\tappResidentDataSize : 0x%x\n", hdr->app_resident_data_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
143
nvkm_debug(subdev, "\tnbImemOverlays : %d\n", hdr->nb_imem_overlays);
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
144
nvkm_debug(subdev, "\tnbDmemOverlays : %d\n", hdr->nb_dmem_overlays);
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
146
nvkm_debug(subdev, "\tloadOvl[%d] : 0x%x %d\n", i,
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
158
nvkm_debug(subdev, "lsHsblBinHdr:\n");
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
159
nvkm_debug(subdev, "\tbinMagic : 0x%08x\n", hdr->bin_magic);
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
160
nvkm_debug(subdev, "\tbinVer : %d\n", hdr->bin_ver);
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
161
nvkm_debug(subdev, "\tbinSize : %d\n", hdr->bin_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
162
nvkm_debug(subdev, "\theaderOffset : 0x%x\n", hdr->header_offset);
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
171
nvkm_debug(subdev, "lsHsblHdr:\n");
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
172
nvkm_debug(subdev, "\tsigProdOffset : 0x%x\n", hdr->sig_prod_offset);
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
173
nvkm_debug(subdev, "\tsigProdSize : 0x%x\n", hdr->sig_prod_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
174
nvkm_debug(subdev, "\tpatchLoc : 0x%x\n", hdr->patch_loc);
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
175
nvkm_debug(subdev, "\tpatchSig : 0x%x\n", hdr->patch_sig);
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
176
nvkm_debug(subdev, "\tmetadataOffset : 0x%x\n", hdr->meta_data_offset);
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
177
nvkm_debug(subdev, "\tmetadataSize : 0x%x\n", hdr->meta_data_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
178
nvkm_debug(subdev, "\tnumSig : 0x%x\n", hdr->num_sig);
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
31
nvkm_debug(subdev, "lsUcodeImgDesc:\n");
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
32
nvkm_debug(subdev, "\tdescriptorSize : %d\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
34
nvkm_debug(subdev, "\timageSize : %d\n", hdr->image_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
35
nvkm_debug(subdev, "\ttoolsVersion : 0x%x\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
37
nvkm_debug(subdev, "\tappVersion : 0x%x\n", hdr->app_version);
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
40
nvkm_debug(subdev, "\tdate : %s\n", date);
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
43
nvkm_debug(subdev, "\tbootloaderStartOffset: 0x%x\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
45
nvkm_debug(subdev, "\tbootloaderSize : 0x%x\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
47
nvkm_debug(subdev, "\tbootloaderImemOffset : 0x%x\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
49
nvkm_debug(subdev, "\tbootloaderEntryPoint : 0x%x\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
52
nvkm_debug(subdev, "\tappStartOffset : 0x%x\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
54
nvkm_debug(subdev, "\tappSize : 0x%x\n", hdr->app_size);
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
55
nvkm_debug(subdev, "\tappImemOffset : 0x%x\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
57
nvkm_debug(subdev, "\tappImemEntry : 0x%x\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
59
nvkm_debug(subdev, "\tappDmemOffset : 0x%x\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
61
nvkm_debug(subdev, "\tappResidentCodeOffset: 0x%x\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
63
nvkm_debug(subdev, "\tappResidentCodeSize : 0x%x\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
65
nvkm_debug(subdev, "\tappResidentDataOffset: 0x%x\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
67
nvkm_debug(subdev, "\tappResidentDataSize : 0x%x\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
79
nvkm_debug(subdev, "\tnbOverlays : %d\n", hdr->nb_overlays);
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
81
nvkm_debug(subdev, "\tloadOvl[%d] : 0x%x %d\n", i,
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
84
nvkm_debug(subdev, "\tcompressed : %d\n", hdr->compressed);
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
97
nvkm_debug(subdev, "\tnbImemOverlays : %d\n",
drivers/gpu/drm/nouveau/nvkm/nvfw/ls.c
99
nvkm_debug(subdev, "\tnbDmemOverlays : %d\n",
drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c
228
nvkm_debug(subdev, "No HSFW(s)\n");
drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c
296
nvkm_debug(subdev, "WPR region is from 0x%llx-0x%llx (shadow 0x%llx)\n",
drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c
97
nvkm_debug(subdev, "No LSF(s) present.\n");
drivers/gpu/drm/nouveau/nvkm/subdev/bios/base.c
184
nvkm_debug(&bios->subdev, "BMP version %x.%x\n",
drivers/gpu/drm/nouveau/nvkm/subdev/bios/base.c
192
nvkm_debug(&bios->subdev, "BIT signature found\n");
drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c
90
nvkm_debug(subdev, "DCB contains no useful data\n");
drivers/gpu/drm/nouveau/nvkm/subdev/bios/image.c
45
nvkm_debug(subdev, "%08x: ROM signature (%04x) unknown\n",
drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c
2330
nvkm_debug(subdev, "running init tables\n");
drivers/gpu/drm/nouveau/nvkm/subdev/bios/mxm.c
35
nvkm_debug(subdev, "BIT 'x' table not present\n");
drivers/gpu/drm/nouveau/nvkm/subdev/bios/npde.c
39
nvkm_debug(&bios->subdev,
drivers/gpu/drm/nouveau/nvkm/subdev/bios/pcir.c
41
nvkm_debug(&bios->subdev,
drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c
115
nvkm_debug(subdev, "trying %s...\n", name ? name : func->name);
drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c
126
nvkm_debug(subdev, "scored %d\n", mthd->score);
drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c
242
nvkm_debug(subdev, "using image from %s\n", best->func ?
drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c
65
nvkm_debug(subdev, "%08x: header fetch failed\n",
drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c
71
nvkm_debug(subdev, "image %d invalid\n", idx);
drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c
75
nvkm_debug(subdev, "%08x: type %02x, %d bytes\n",
drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c
79
nvkm_debug(subdev, "%08x: fetch failed\n", image.base);
drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c
87
nvkm_debug(subdev, "%08x: checksum failed\n",
drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.c
77
nvkm_debug(subdev, "... display disabled\n");
drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.c
90
nvkm_debug(subdev, "... not enabled\n");
drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.c
94
nvkm_debug(subdev, "... not in vram\n");
drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c
118
nvkm_debug(hwsq->subdev, " FLAG[%02x] = %d\n", flag, data);
drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c
130
nvkm_debug(hwsq->subdev, " WAIT[%02x] = %d\n", flag, data);
drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c
157
nvkm_debug(subdev, "WAIT VBLANK !NO ACTIVE HEAD\n");
drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c
161
nvkm_debug(subdev, "WAIT VBLANK HEAD%d\n", head_sync);
drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c
175
nvkm_debug(hwsq->subdev, " DELAY = %d ns\n", nsec);
drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c
93
nvkm_debug(hwsq->subdev, "R[%06x] = %08x\n", addr, data);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c
280
nvkm_debug(subdev, "setting performance state %d\n", pstatei);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c
364
nvkm_debug(subdev, "%02x: %10d KHz\n", clock->name, lo);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c
369
nvkm_debug(subdev, "%10d KHz\n", freq);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c
385
nvkm_debug(subdev, "%s: %s %s %s\n", name, info[0], info[1], info[2]);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
136
nvkm_debug(subdev, "low_PL %d(div%d), high_PL %d(div%d)", low_pl,
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
194
nvkm_debug(subdev,
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
204
nvkm_debug(subdev,
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
639
nvkm_debug(&clk->base.subdev, "parent clock rate: %d Khz\n",
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
1013
nvkm_debug(subdev, "safe fmax @ vmin = %u Khz\n", clk->safe_fmax_vmin);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
212
nvkm_debug(subdev, "%s uv: %d coeff: %x, ext_cal: %d, det_max: %d\n",
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
262
nvkm_debug(subdev, "%s n_eff: %d, n_int: %d, sdm_din: %d\n", __func__,
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
480
nvkm_debug(subdev, "%s uv: %d uv\n", __func__, clk->new_uv);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
794
nvkm_debug(subdev, "calibrated DVFS parameters: offs %d, slope %d\n",
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c
975
nvkm_debug(subdev, "fused calibration data: slope %d, offs %d\n",
drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
157
nvkm_debug(subdev, "unknown clock source %d %08x\n", src, mast);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
270
nvkm_debug(subdev, "nvpll: %08x %08x %08x\n",
drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
272
nvkm_debug(subdev, " spll: %08x %08x %08x\n",
drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
274
nvkm_debug(subdev, " vdiv: %08x\n", clk->vdiv);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
276
nvkm_debug(subdev, "core: hrefm4\n");
drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
278
nvkm_debug(subdev, "core: nvpll\n");
drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
281
nvkm_debug(subdev, "shader: hrefm4\n");
drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
283
nvkm_debug(subdev, "shader: nvpll\n");
drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
285
nvkm_debug(subdev, "shader: spll\n");
drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
288
nvkm_debug(subdev, "vdec: 500MHz\n");
drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
290
nvkm_debug(subdev, "vdec: core\n");
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c
119
nvkm_debug(subdev, "unknown clock source %d %08x\n", src, mast);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
321
nvkm_debug(subdev, "unknown clock source %d %08x\n", src, mast);
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c
421
nvkm_debug(subdev, "adaptor not initialised\n");
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c
112
nvkm_debug(subdev, "adaptor not initialised\n");
drivers/gpu/drm/nouveau/nvkm/subdev/fault/base.c
86
nvkm_debug(subdev, "buffer %d: %d entries\n", id, buffer->entries);
drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c
182
nvkm_debug(subdev, "intr %08x\n", stat);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c
131
nvkm_debug(subdev, "%d comptags\n", tags);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c
151
nvkm_debug(subdev, "VPR not locked\n");
drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c
155
nvkm_debug(subdev, "VPR locked, running scrubber binary\n");
drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c
173
nvkm_debug(subdev, "VPR scrubber binary successful\n");
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c
39
nvkm_debug(subdev, "PFFB intr\n");
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c
41
nvkm_debug(subdev, "PBFB intr\n");
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c
504
nvkm_debug(subdev, "%d FBP(s)\n", fbps);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c
508
nvkm_debug(subdev, "FBP %d: %4d MiB, %d LTC(s)\n",
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c
514
nvkm_debug(subdev, "FBP %d: disabled\n", fbp);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c
522
nvkm_debug(subdev, "Lower: %4lld MiB @ %010llx\n", lower >> 20, 0ULL);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c
523
nvkm_debug(subdev, "Upper: %4lld MiB @ %010llx\n", usize >> 20, ubase);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c
524
nvkm_debug(subdev, "Total: %4lld MiB\n", total >> 20);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c
1073
nvkm_debug(subdev, "successfully calced PLLs for clock %i kHz"
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
248
nvkm_debug(subdev, "Train: %08x", result[i]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
251
nvkm_debug(subdev, "Train: %08x %08x %08x", train->r_100720,
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
414
nvkm_debug(subdev, "Entry: 220: %08x %08x %08x %08x\n",
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
416
nvkm_debug(subdev, " 230: %08x %08x %08x %08x\n",
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
418
nvkm_debug(subdev, " 240: %08x\n", timing[8]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
142
nvkm_debug(subdev, " 220: %08x %08x %08x %08x\n",
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
144
nvkm_debug(subdev, " 230: %08x %08x %08x %08x\n",
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
146
nvkm_debug(subdev, " 240: %08x\n", timing[8]);
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
514
nvkm_debug(subdev, "memcfg %08x %08x %08x %08x\n",
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
536
nvkm_debug(subdev, "rblock %d bytes\n", rblock_size);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/fwsec.c
371
nvkm_debug(subdev, "fwsec-frts: WPR2 @ %08x - %08x\n", wpr2_lo, wpr2_hi);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/alloc.c
34
nvkm_debug(&gsp->subdev, "cli:0x%08x obj:0x%08x free\n",
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/alloc.c
85
nvkm_debug(&gsp->subdev, "cli:0x%08x obj:0x%08x new obj:0x%08x\n",
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/alloc.c
89
nvkm_debug(&gsp->subdev, "cls:0x%08x params_size:%d\n", oclass,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/ctrl.c
72
nvkm_debug(&gsp->subdev, "cli:0x%08x obj:0x%08x ctrl cmd:0x%08x params_size:%d\n",
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c
1009
nvkm_debug(&disp->engine.subdev,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c
1105
nvkm_debug(&disp->engine.subdev,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c
1376
nvkm_debug(&disp->engine.subdev, "event: dp irq displayId %08x\n", irq->displayId);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c
1391
nvkm_debug(&disp->engine.subdev, "event: hpd plug %08x unplug %08x\n",
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c
1673
nvkm_debug(&disp->engine.subdev, " SOR(s): %d (%02lx)\n", disp->sor.nr, disp->sor.mask);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c
857
nvkm_debug(&disp->engine.subdev, "DFP %08x: flags:%08x flags2:%08x\n",
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fbsr.c
243
nvkm_debug(subdev, "fbsr: %016llx %016llx %s\n",
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fbsr.c
250
nvkm_debug(subdev, "fbsr: %d regions (0x%llx bytes)\n", fbsr.regions, items_size);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fbsr.c
254
nvkm_debug(subdev, "fbsr: size: 0x%llx bytes\n", fbsr.size);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gr.c
131
nvkm_debug(subdev,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gr.c
211
nvkm_debug(subdev, "%02x: size:0x%08x %s\n", i,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c
1015
nvkm_debug(subdev, "seq: %08x %08x\n", seq->bufferSizeDWord, seq->cmdIndex);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c
1288
nvkm_debug(subdev, "received libos print from class 0x%x for %u bytes\n",
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c
1420
nvkm_debug(&gsp->subdev, "created debugfs GSP-RM logging entries\n");
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c
153
nvkm_debug(&gsp->subdev,
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c
186
nvkm_debug(&gsp->subdev, "fb region %d: "
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c
70
nvkm_debug(subdev, "inte %08x %08x\n", intr, inte);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c
967
nvkm_debug(subdev, "event: %08x %08x %d %08x %08x %d %d\n",
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/fbsr.c
129
nvkm_debug(subdev, "fbsr: size: 0x%llx bytes\n", size);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/tu102.c
326
nvkm_debug(&gsp->subdev, "MMU_LOCK range: 0x%llx - 0x%llx\n", addr_lo, addr_hi);
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/tu102.c
55
nvkm_debug(subdev, "WPR2 not set - skipping booter unload\n");
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c
284
nvkm_debug(&i2c->subdev, "ccb %02x: type %02x drive %02x "
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c
357
nvkm_debug(&i2c->subdev, "dcb %02x no bus\n", i);
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c
369
nvkm_debug(&i2c->subdev, "dcb %02x drv %02x unknown\n",
drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/base.c
290
nvkm_debug(subdev, "create rail for extdev %i: { idx: %i, mohm: %i }\n", pwr_rail->extdev_id, r, rail->mohm);
drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c
152
nvkm_debug(&imem->base.subdev, "vaddr used: %x/%x\n", imem->vaddr_use,
drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c
218
nvkm_debug(&imem->base.subdev, "vaddr used: %x/%x\n",
drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c
523
nvkm_debug(subdev, "%s (%s): size: %x align: %x\n", __func__,
drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c
542
nvkm_debug(subdev, "alloc size: 0x%x, align: 0x%x, gaddr: 0x%llx\n",
drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c
145
nvkm_debug(subdev, "evict %016llx %016llx @ %016llx\n",
drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c
135
nvkm_debug(<c->subdev, "LTC invalidate took %lld ns\n", taken);
drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c
148
nvkm_debug(<c->subdev, "LTC flush took %lld ns\n", taken);
drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c
109
nvkm_debug(subdev, "DSM MXMS failed\n");
drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c
117
nvkm_debug(subdev, "DSM MXMS returned 0x%llx\n",
drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c
142
nvkm_debug(subdev, "WMMX MXMI returned %d\n", status);
drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c
149
nvkm_debug(subdev, "WMMX MXMI version %d.%d\n",
drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c
153
nvkm_debug(subdev, "WMMX MXMI returned non-integer\n");
drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c
171
nvkm_debug(subdev, "WMMX GUID not found\n");
drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c
183
nvkm_debug(subdev, "WMMX MXMS returned %d\n", status);
drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c
217
nvkm_debug(&mxm->subdev, "checking %s\n", shadow->name);
drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c
248
nvkm_debug(&mxm->subdev, "no VBIOS data, nothing to do\n");
drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c
253
nvkm_debug(&mxm->subdev, "module flags: %02x\n",
drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c
255
nvkm_debug(&mxm->subdev, "config flags: %02x\n",
drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c
272
nvkm_debug(&mxm->subdev, "MXMS Version %d.%d\n",
drivers/gpu/drm/nouveau/nvkm/subdev/mxm/mxms.c
144
nvkm_debug(subdev, "unknown descriptor type %d\n", type);
drivers/gpu/drm/nouveau/nvkm/subdev/mxm/mxms.c
161
nvkm_debug(subdev, "%4s: %s\n", mxms_desc[type], data);
drivers/gpu/drm/nouveau/nvkm/subdev/mxm/mxms.c
165
nvkm_debug(subdev, " %s\n", data);
drivers/gpu/drm/nouveau/nvkm/subdev/mxm/mxms.c
50
nvkm_debug(&mxm->subdev, "unknown version %d.%d\n", mxms[4], mxms[5]);
drivers/gpu/drm/nouveau/nvkm/subdev/mxm/mxms.c
74
nvkm_debug(&mxm->subdev, "checksum invalid\n");
drivers/gpu/drm/nouveau/nvkm/subdev/mxm/mxms.c
85
nvkm_debug(&mxm->subdev, "signature invalid\n");
drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.c
106
nvkm_debug(&mxm->subdev, "disable %d: %08x %08x\n",
drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c
200
nvkm_debug(&pci->subdev, "MSI enabled\n");
drivers/gpu/drm/nouveau/nvkm/subdev/pci/gk104.c
171
nvkm_debug(subdev, "adjusting lnkctl to max speed\n");
drivers/gpu/drm/nouveau/nvkm/subdev/pci/pcie.c
142
nvkm_debug(subdev, "%s not supported by bus or card, dropping"
drivers/gpu/drm/nouveau/nvkm/subdev/pci/pcie.c
152
nvkm_debug(subdev, "requested matches current speed\n");
drivers/gpu/drm/nouveau/nvkm/subdev/pci/pcie.c
156
nvkm_debug(subdev, "set link to %s x%i\n",
drivers/gpu/drm/nouveau/nvkm/subdev/pci/pcie.c
83
nvkm_debug(&pci->subdev, "pcie max speed: %s\n",
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c
138
nvkm_debug(subdev, "ACR WPR init complete\n");
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c
102
nvkm_debug(&memx->pmu->subdev, "R[%06x] = %08x\n", addr, data);
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c
110
nvkm_debug(&memx->pmu->subdev, "R[%06x] & %08x == %08x, %d us\n",
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c
119
nvkm_debug(&memx->pmu->subdev, " DELAY = %d ns\n", nsec);
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c
149
nvkm_debug(subdev, "WAIT VBLANK !NO ACTIVE HEAD\n");
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c
153
nvkm_debug(subdev, "WAIT VBLANK HEAD%d\n", head_sync);
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c
161
nvkm_debug(&memx->pmu->subdev, " MEM TRAIN\n");
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c
194
nvkm_debug(&memx->pmu->subdev, " HOST BLOCKED\n");
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c
201
nvkm_debug(&memx->pmu->subdev, " HOST UNBLOCKED\n");
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c
91
nvkm_debug(subdev, "Exec took %uns, PMU_IN %08x\n",
drivers/gpu/drm/nouveau/nvkm/subdev/privring/gf100.c
34
nvkm_debug(privring, "HUB%d: %06x %08x (%08x)\n", i, addr, data, stat);
drivers/gpu/drm/nouveau/nvkm/subdev/privring/gf100.c
44
nvkm_debug(privring, "ROP%d: %06x %08x (%08x)\n", i, addr, data, stat);
drivers/gpu/drm/nouveau/nvkm/subdev/privring/gf100.c
54
nvkm_debug(privring, "GPC%d: %06x %08x (%08x)\n", i, addr, data, stat);
drivers/gpu/drm/nouveau/nvkm/subdev/privring/gk104.c
34
nvkm_debug(privring, "HUB%d: %06x %08x (%08x)\n", i, addr, data, stat);
drivers/gpu/drm/nouveau/nvkm/subdev/privring/gk104.c
44
nvkm_debug(privring, "ROP%d: %06x %08x (%08x)\n", i, addr, data, stat);
drivers/gpu/drm/nouveau/nvkm/subdev/privring/gk104.c
54
nvkm_debug(privring, "GPC%d: %06x %08x (%08x)\n", i, addr, data, stat);
drivers/gpu/drm/nouveau/nvkm/subdev/privring/gk20a.c
55
nvkm_debug(privring, "resetting privring ring\n");
drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c
158
nvkm_debug(subdev, "FAN target request: %d%%\n", duty);
drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c
169
nvkm_debug(subdev, "default fan speed -> %d%%\n", fan);
drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c
209
nvkm_debug(subdev, "fan management: %s\n", name[mode]);
drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c
309
nvkm_debug(&therm->subdev,
drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c
320
nvkm_debug(&therm->subdev,
drivers/gpu/drm/nouveau/nvkm/subdev/therm/fan.c
237
nvkm_debug(subdev, "GPIO_FAN is in input mode\n");
drivers/gpu/drm/nouveau/nvkm/subdev/therm/fan.c
253
nvkm_debug(subdev, "FAN control: %s\n", therm->fan->type);
drivers/gpu/drm/nouveau/nvkm/subdev/therm/fan.c
273
nvkm_debug(subdev, "parsing the fan table failed\n");
drivers/gpu/drm/nouveau/nvkm/subdev/therm/fan.c
48
nvkm_debug(subdev, "FAN target: %d\n", target);
drivers/gpu/drm/nouveau/nvkm/subdev/therm/fan.c
73
nvkm_debug(subdev, "FAN update: %d\n", duty);
drivers/gpu/drm/nouveau/nvkm/subdev/therm/g84.c
80
nvkm_debug(subdev,
drivers/gpu/drm/nouveau/nvkm/subdev/therm/ic.c
49
nvkm_debug(&therm->subdev,
drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.c
197
nvkm_debug(&therm->subdev,
drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.c
235
nvkm_debug(&therm->subdev, "internal sensor: %s\n", sensor_avail);
drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c
128
nvkm_debug(subdev, "input frequency : %dHz\n", f);
drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c
129
nvkm_debug(subdev, "numerator : %08x\n", n);
drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c
130
nvkm_debug(subdev, "denominator : %08x\n", d);
drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c
131
nvkm_debug(subdev, "timer frequency : %dHz\n", f * d / n);
drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c
35
nvkm_debug(subdev, "time low : %08x\n", lo);
drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c
36
nvkm_debug(subdev, "time high : %08x\n", hi);
drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv40.c
65
nvkm_debug(subdev, "input frequency : %dHz\n", f);
drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv40.c
66
nvkm_debug(subdev, "numerator : %08x\n", n);
drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv40.c
67
nvkm_debug(subdev, "denominator : %08x\n", d);
drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv40.c
68
nvkm_debug(subdev, "timer frequency : %dHz\n", f * d / n);
drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv41.c
60
nvkm_debug(subdev, "input frequency : %dHz\n", f);
drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv41.c
61
nvkm_debug(subdev, "input multiplier: %d\n", m);
drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv41.c
62
nvkm_debug(subdev, "numerator : %08x\n", n);
drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv41.c
63
nvkm_debug(subdev, "denominator : %08x\n", d);
drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv41.c
64
nvkm_debug(subdev, "timer frequency : %dHz\n", (f * m) * d / n);
drivers/gpu/drm/nouveau/nvkm/subdev/top/ga100.c
89
nvkm_debug(subdev, "%02x.%d (%8s): addr %06x fault %2d "
drivers/gpu/drm/nouveau/nvkm/subdev/top/gk104.c
99
nvkm_debug(subdev, "%02x.%d (%8s): addr %06x fault %2d "
drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c
197
nvkm_debug(subdev, "found ranged based VIDs\n");
drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c
211
nvkm_debug(subdev, "found entry based VIDs\n");
drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c
247
nvkm_debug(subdev, "current voltage unknown\n");
drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c
250
nvkm_debug(subdev, "current voltage: %duv\n", ret);
drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c
261
nvkm_debug(&volt->subdev, "speedo %x\n", volt->speedo);
drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c
298
nvkm_debug(&volt->subdev, "min: %iuv max: %iuv\n",
drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c
314
nvkm_debug(&volt->subdev, "VID %02x: %duv\n",
drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c
76
nvkm_debug(subdev, "set req %duv to %duv: %d\n", uv,
drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c
138
nvkm_debug(&volt->base.subdev, "Using %s mode\n", mode);
drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c
113
nvkm_debug(subdev, "set voltage as %duv\n", volt->base.vid[vid].uv);
drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c
126
nvkm_debug(subdev, "prev=%d, target=%d, condition=%d\n",
drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c
157
nvkm_debug(&volt->base.subdev, "the default voltage is %duV\n", uv);
drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c
167
nvkm_debug(&volt->base.subdev, "%2d: vid=%d, uv=%d\n", i,
drivers/gpu/drm/nouveau/nvkm/subdev/volt/gpio.c
91
nvkm_debug(subdev, "VID bit %d has no GPIO\n", i);
