arch/x86/kernel/cpu/vmware.c

170

ns = mul_u64_u32_shr(rdtsc(), vmware_cyc2ns.cyc2ns_mul,

arch/x86/kernel/cpu/vmware.c

183

d->cyc2ns_offset = mul_u64_u32_shr(tsc_now, d->cyc2ns_mul,

arch/x86/kernel/cpu/vmware.c

252

return mul_u64_u32_shr(clock, vmware_cyc2ns.cyc2ns_mul,

arch/x86/kernel/tsc.c

135

ns += mul_u64_u32_shr(cyc, data.cyc2ns_mul, data.cyc2ns_shift);

arch/x86/kernel/tsc.c

177

mul_u64_u32_shr(tsc_now, data.cyc2ns_mul, data.cyc2ns_shift);

drivers/clk/renesas/rcar-gen4-cpg.c

129

req->rate = prate * ni + mul_u64_u32_shr(req->best_parent_rate, nf, 24);

drivers/clk/renesas/rcar-gen4-cpg.c

208

rate += mul_u64_u32_shr(parent_rate, nf, 24);

drivers/clk/renesas/rcar-gen4-cpg.c

94

rate += mul_u64_u32_shr(parent_rate, nf, 24);

drivers/clk/renesas/rzg2l-cpg.c

1098

rate = mul_u64_u32_shr(parent_rate, (MDIV(val1) << 16) + KDIV(val1),

drivers/clk/renesas/rzg2l-cpg.c

1134

rate = mul_u64_u32_shr(parent_rate, 4096 * nir + nfr, 12);

drivers/clk/renesas/rzv2h-cpg.c

892

rate = mul_u64_u32_shr(parent_rate, (FIELD_GET(CPG_PLL_CLK1_MDIV, clk1) << 16) +

drivers/gpu/drm/i915/gvt/handlers.c

707

new_rate = DIV64_U64_ROUND_CLOSEST(mul_u64_u32_shr(pixel_clk, MSEC_PER_SEC, 0), mul_u32_u32(htotal + 1, vtotal + 1));

drivers/gpu/drm/i915/i915_hwmon.c

114

return mul_u64_u32_shr(reg_value, scale_factor, nshift);

drivers/gpu/drm/i915/i915_hwmon.c

163

*energy = mul_u64_u32_shr(ei->accum_energy, SF_ENERGY,

drivers/gpu/drm/i915/i915_hwmon.c

194

out = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w);

drivers/gpu/drm/i915/i915_hwmon.c

229

max_win = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w);

drivers/gpu/drm/i915/i915_hwmon.c

433

min = mul_u64_u32_shr(min, SF_POWER, hwmon->scl_shift_power);

drivers/gpu/drm/i915/i915_hwmon.c

435

max = mul_u64_u32_shr(max, SF_POWER, hwmon->scl_shift_power);

drivers/gpu/drm/i915/i915_hwmon.c

522

*val = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval),

drivers/gpu/drm/i915/i915_hwmon.c

639

*val = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval),

drivers/gpu/drm/xe/xe_hwmon.c

376

min = mul_u64_u32_shr(min, SF_POWER, hwmon->scl_shift_power);

drivers/gpu/drm/xe/xe_hwmon.c

377

max = mul_u64_u32_shr(max, SF_POWER, hwmon->scl_shift_power);

drivers/gpu/drm/xe/xe_hwmon.c

481

*value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon->scl_shift_power);

drivers/gpu/drm/xe/xe_hwmon.c

542

*energy = mul_u64_u32_shr(ei->accum_energy, SF_ENERGY,

drivers/gpu/drm/xe/xe_hwmon.c

594

out = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w);

drivers/gpu/drm/xe/xe_hwmon.c

635

max_win = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w);

drivers/gpu/drm/xe/xe_hwmon.c

884

*value = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval),

drivers/iio/accel/adxl355_core.c

282

odr = mul_u64_u32_shr(adxl355_odr_table[data->odr][0], MEGA, 0) +

drivers/iio/accel/adxl355_core.c

287

div = div64_u64_rem(mul_u64_u32_shr(odr, multiplier, 0),

drivers/iio/accel/adxl380.c

480

odr = mul_u64_u32_shr(odr_hz, MEGA, 0);

drivers/iio/accel/adxl380.c

482

div = div64_u64_rem(mul_u64_u32_shr(odr, multiplier, 0),

drivers/perf/arm_pmuv3.c

1641

ns = mul_u64_u32_shr(rd->epoch_cyc, rd->mult, rd->shift);

drivers/perf/riscv_pmu.c

64

ns = mul_u64_u32_shr(rd->epoch_cyc, rd->mult, rd->shift);

drivers/regulator/max5970-regulator.c

93

*val = mul_u64_u32_shr(*val, ddata->mon_rng, 10);

include/linux/math64.h

174

#ifndef mul_u64_u32_shr

include/linux/math64.h

190

#ifndef mul_u64_u32_shr

kernel/sched/fair.c

285

return mul_u64_u32_shr(delta_exec, fact, shift);

kernel/sched/pelt.c

54

val = mul_u64_u32_shr(val, runnable_avg_yN_inv[local_n], 32);

kernel/time/clocksource.c

34

return mul_u64_u32_shr(delta, cs->mult, cs->shift);

net/sched/sch_netem.c

689

mul_u64_u32_shr(q->slot_config.max_delay - q->slot_config.min_delay,

tools/lib/perf/mmap.c

529

delta = time_offset + mul_u64_u32_shr(cyc, time_mult, time_shift);