mt76_rmw_field
mt76_rmw_field(dev, MT_ARB_SCR, MT_ARB_SCR_BCNQ_OPMODE_MASK,
mt76_rmw_field(dev, MT_TMAC_TCR, MT_TMAC_TCR_TX_STREAMS,
mt76_rmw_field(dev, MT_AGG_PCR_RTS, MT_AGG_PCR_RTS_PKT_THR, 3);
mt76_rmw_field(dev, MT_TXREQ, MT_TXREQ_CCA_SRC_SEL, 2);
mt76_rmw_field(dev, MT_LPON_BTEIR, MT_LPON_BTEIR_MBSS_MODE, 2);
mt76_rmw_field(dev, MT_WF_RMACDR, MT_WF_RMACDR_MBSSID_MASK, 2);
mt76_rmw_field(dev, MT_LPON_SBTOR(i), MT_LPON_SBTOR_TIME_OFFSET,
mt76_rmw_field(dev, MT_RXTD(13), MT_RXTD_13_ACI_TH_EN,
mt76_rmw_field(dev, addr + 2 * 4, MT_WTBL1_W2_SMPS, enabled);
mt76_rmw_field(dev, MT_AGG_CONTROL, MT_AGG_CONTROL_CFEND_RATE, val);
mt76_rmw_field(dev, addr + 2 * 4, MT_WTBL1_W2_KEY_TYPE, cipher);
mt76_rmw_field(dev, addr, MT_WTBL1_W0_KEY_IDX, key->keyidx);
mt76_rmw_field(dev, addr, MT_WTBL1_W0_RX_KEY_VALID, !!key);
mt76_rmw_field(dev, MT_RXTD(8), MT_RXTD_8_LOWER_SIGNAL, 0x23);
mt76_rmw_field(dev, MT_AGG_BWCR, MT_AGG_BWCR_BW, bw);
mt76_rmw_field(dev, MT_WF_RMAC_MORE(0), MT_WF_RMAC_MORE_MUAR_MODE, 1);
mt76_rmw_field(dev, MT_WF_RMAC_MORE(0), MT_WF_RMAC_MORE_MUAR_MODE, !!dev->muar_mask);
mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,
mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,
mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,
mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,
mt76_rmw_field(dev, MT_TMAC_CTCR0,
mt76_rmw_field(dev, MT_TMAC_CTCR0,
mt76_rmw_field(dev, MT_AGG_ACR(ext_phy), MT_AGG_ACR_CFEND_RATE, val);
mt76_rmw_field(dev, MT_WF_PHY_RFINTF3_0(i),
mt76_rmw_field(dev, MT_ANT_SWITCH_CON(3), MT_ANT_SWITCH_CON_MODE(0),
mt76_rmw_field(dev, MT_ANT_SWITCH_CON(4), MT_ANT_SWITCH_CON_MODE(2),
mt76_rmw_field(dev, MT_ANT_SWITCH_CON(6), MT_ANT_SWITCH_CON_MODE1(0),
mt76_rmw_field(dev, MT_ANT_SWITCH_CON(7), MT_ANT_SWITCH_CON_MODE1(2),
mt76_rmw_field(dev, MT_ANT_SWITCH_CON(4), MT_ANT_SWITCH_CON_MODE(1),
mt76_rmw_field(dev, MT_ANT_SWITCH_CON(2), MT_ANT_SWITCH_CON_MODE(3),
mt76_rmw_field(dev, MT_ANT_SWITCH_CON(7), MT_ANT_SWITCH_CON_MODE1(1),
mt76_rmw_field(dev, MT_ANT_SWITCH_CON(8), MT_ANT_SWITCH_CON_MODE1(3),
mt76_rmw_field(dev, MT_BBP(AGC, 8), MT_BBP_AGC_GAIN, gain);
mt76_rmw_field(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP, val);
mt76_rmw_field(dev, MT_BEACON_TIME_CFG,
mt76_rmw_field(dev, MT_INT_TIMER_EN,
mt76_rmw_field(dev, MT_INT_TIMER_EN,
mt76_rmw_field(dev, MT_WCID_ATTR(idx), MT_WCID_ATTR_PKEY_MODE, cipher);
mt76_rmw_field(dev, MT_WCID_ATTR(idx), MT_WCID_ATTR_PAIRWISE,
mt76_rmw_field(dev, MT_MAC_APC_BSSID_H(idx), MT_MAC_APC_BSSID_H_ADDR,
mt76_rmw_field(dev, MT_MAC_BSSID_DW1, MT_MAC_BSSID_DW1_MBEACON_N, 7);
mt76_rmw_field(dev, MT_TX_RTS_CFG, MT_TX_RTS_CFG_THRESH, val);
mt76_rmw_field(dev, MT_INT_TIMER_CFG, MT_INT_TIMER_CFG_PRE_TBTT,
mt76_rmw_field(dev, MT_INT_TIMER_CFG, MT_INT_TIMER_CFG_GP_TIMER,
mt76_rmw_field(dev, MT_INT_TIMER_EN, MT_INT_TIMER_EN_PRE_TBTT_EN, en);
mt76_rmw_field(dev, MT_BBP(CORE, 1), MT_BBP_CORE_R1_BW, core_val);
mt76_rmw_field(dev, MT_BBP(AGC, 0), MT_BBP_AGC_R0_BW, agc_val);
mt76_rmw_field(dev, MT_BBP(AGC, 0), MT_BBP_AGC_R0_CTRL_CHAN, ctrl);
mt76_rmw_field(dev, MT_BBP(TXBE, 0), MT_BBP_TXBE_R0_CTRL_CHAN, ctrl);
mt76_rmw_field(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_UPPER_40M,
mt76_rmw_field(dev, MT_TX_ALC_CFG_0, MT_TX_ALC_CFG_0_CH_INIT_0, txp_0);
mt76_rmw_field(dev, MT_TX_ALC_CFG_0, MT_TX_ALC_CFG_0_CH_INIT_1, txp_1);
mt76_rmw_field(dev, MT_PROT_AUTO_TX_CFG,
mt76_rmw_field(dev, MT_PROT_AUTO_TX_CFG,
mt76_rmw_field(dev, MT_BKOFF_SLOT_CFG,
mt76_rmw_field(dev, MT_TX_TIMEOUT_CFG,
mt76_rmw_field(dev, MT_BEACON_TIME_CFG,
mt76_rmw_field(dev, 0x15a10, 0x1f << 16, 0x9);
mt76_rmw_field(dev, 0x15a0c, 0xfU << 28, 0xf);
mt76_rmw_field(dev, 0x15c58, 0x3 << 6, 0x3);
mt76_rmw_field(dev, MT_XO_CTRL5, MT_XO_CTRL5_C2_VAL, eep_val + offset);
mt76_rmw_field(dev, MT_TX_PIN_CFG, MT_TX_PIN_CFG_TXANT, 0xf);
mt76_rmw_field(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP,
mt76_rmw_field(dev, MT_TX_ALC_CFG_2, MT_TX_ALC_CFG_2_TEMP_COMP,
mt76_rmw_field(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP,
mt76_rmw_field(dev, MT_TX_ALC_CFG_2, MT_TX_ALC_CFG_2_TEMP_COMP,
mt76_rmw_field(dev, MT_TX_PIN_CFG, MT_TX_PIN_CFG_TXANT, 0x3);
mt76_rmw_field(dev, MT_BBP(CORE, 32), GENMASK(21, 20), 2);
mt76_rmw_field(dev, MT_BBP(CORE, 33), GENMASK(12, 9), 4);
mt76_rmw_field(dev, MT_BBP(TXBE, 5), 3, 1);
mt76_rmw_field(dev, MT_TX_PIN_CFG, MT_TX_PIN_CFG_TXANT, 0xc);
mt76_rmw_field(dev, MT_BBP(CORE, 32), GENMASK(21, 20), 1);
mt76_rmw_field(dev, MT_BBP(CORE, 33), GENMASK(12, 9), 1);
mt76_rmw_field(dev, MT_XIFS_TIME_CFG, MT_XIFS_TIME_CFG_OFDM_SIFS, 15);
mt76_rmw_field(dev, MT_BBP(AGC, reg), MT_BBP_AGC_LNA_HIGH_GAIN, gain);
mt76_rmw_field(dev, MT_BBP(AGC, reg), MT_BBP_AGC_GAIN, gain);
mt76_rmw_field(dev, MT_VEND_ADDR(CFG, MT_XO_CTRL5),
mt76_rmw_field(dev, MT_XIFS_TIME_CFG,
mt76_rmw_field(dev, MT_BKOFF_SLOT_CFG, MT_BKOFF_SLOT_CFG_CC_DELAY, 1);
mt76_rmw_field(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP,
mt76_rmw_field(dev, MT_TX_ALC_CFG_2, MT_TX_ALC_CFG_2_TEMP_COMP,
mt76_rmw_field(dev, MT_TMAC_CTCR0(band),
mt76_rmw_field(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_MAX_RX_LEN, 0x680);
mt76_rmw_field(dev, MT_LED_GPIO_MUX2,
mt76_rmw_field(dev, MT_LED_GPIO_MUX3,
mt76_rmw_field(dev, MT_LED_GPIO_MUX0,
mt76_rmw_field(dev, MT_LED_GPIO_MUX0,
mt76_rmw_field(dev, MT_LED_GPIO_MUX1,
mt76_rmw_field(dev, MT_LED_GPIO_MUX1,
mt76_rmw_field(dev, MT_LED_GPIO_MUX3,
mt76_rmw_field(dev, MT_LED_GPIO_MUX0,
mt76_rmw_field(dev, MT_LED_GPIO_MUX1,
mt76_rmw_field(dev, MT_LED_GPIO_MUX2,
mt76_rmw_field(dev, MT_LED_GPIO_MUX0,
mt76_rmw_field(dev, MT_LED_GPIO_MUX1,
mt76_rmw_field(dev, MT_MDP_DCR1, MT_MDP_DCR1_MAX_RX_LEN, rx_len);
mt76_rmw_field(dev, MT_AGG_ACR0(band), MT_AGG_ACR_CFEND_RATE, val);
mt76_rmw_field(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_RXD_G5_EN,
mt76_rmw_field(dev, MT_DMA_DCR0(band), MT_MDP_DCR0_RX_HDR_TRANS_EN,
mt76_rmw_field(dev, addr, GENMASK(7, 0), 0xa0);
mt76_rmw_field(dev, addr, GENMASK(31, 24), phy.sgi);
mt76_rmw_field(dev, addr, GENMASK(15, 12), phy.sgi);
mt76_rmw_field(dev, MT_CONN_INFRA_WF_SLP_PROT,
mt76_rmw_field(dev, MT_AFE_DIG_EN_02(0), MT_AFE_MCU_BPLL_CFG_MASK, 0x2);
mt76_rmw_field(dev, MT_AFE_DIG_EN_02(0), MT_AFE_WPLL_CFG_MASK, 0x2);
mt76_rmw_field(dev, MT_CONN_INFRA_EMI_REQ,
mt76_rmw_field(dev, MT_CONN_INFRA_EMI_REQ,
mt76_rmw_field(dev, MT_CONN_INFRA_EMI_REQ,
mt76_rmw_field(dev, MT_CONN_INFRA_EMI_REQ,
mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS,
mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS,
mt76_rmw_field(dev, MT_TOP_MCU_EMI_BASE,
mt76_rmw_field(dev, MT_TOP_WF_AP_PERI_BASE,
mt76_rmw_field(dev, MT_TOP_EFUSE_BASE,
mt76_rmw_field(dev, MT_CONN_INFRA_ADIE_RESET,
mt76_rmw_field(dev, MT_CONN_INFRA_ADIE_RESET,
mt76_rmw_field(dev, MT_AFE_DIG_EN_01(idx),
mt76_rmw_field(dev, MT_AFE_DIG_EN_03(idx),
mt76_rmw_field(dev, MT_AFE_DIG_EN_03(idx),
mt76_rmw_field(dev, MT_INFRA_BUS_OFF_TIMEOUT,
mt76_rmw_field(dev, MT_INFRA_BUS_OFF_TIMEOUT,
mt76_rmw_field(dev, MT_INFRA_BUS_ON_TIMEOUT,
mt76_rmw_field(dev, MT_INFRA_BUS_ON_TIMEOUT,
mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS_WPLL_DIV_1,
mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS_WPLL_DIV_2,
mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS_WPLL_DIV_1,
mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS_WPLL_DIV_2,
mt76_rmw_field(dev, MT_INFRA_CKGEN_RFSPI_WPLL_DIV,
mt76_rmw_field(dev, MT_INFRA_CKGEN_RFSPI_WPLL_DIV,
mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS,
mt76_rmw_field(dev, MT_CONN_INFRA_HW_CTRL,
mt76_rmw_field(dev, MT_ADIE_SLP_CTRL_CK0(0),
mt76_rmw_field(dev, MT_ADIE_SLP_CTRL_CK0(1),
mt76_rmw_field(dev, MT_TOP_WFSYS_WAKEUP,
mt76_rmw_field(dev, MT7986_TOP_WM_RESET,
mt76_rmw_field(dev, MT_MDP_DCR1, MT_MDP_DCR1_MAX_RX_LEN, 1536);
mt76_rmw_field(dev, MT_HIF_REMAP_L1, MT_HIF_REMAP_L1_MASK, base);
mt76_rmw_field(dev, MT_PCIE_MAC_PM, MT_PCIE_MAC_PM_L0S_DIS, 1);
mt76_rmw_field(dev, MT_MDP_DCR1, MT_MDP_DCR1_MAX_RX_LEN, 1536);
mt76_rmw_field(dev, MT_HW_EMI_CTL, MT_HW_EMI_CTL_SLPPROT_EN, 1);
mt76_rmw_field(dev, MT_PCIE_MAC_PM, MT_PCIE_MAC_PM_L0S_DIS, 1);
mt76_rmw_field(dev, MT_TMAC_CTCR0(band),
mt76_rmw_field(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_MAX_RX_LEN, 1536);
mt76_rmw_field(dev, MT_AGG_ACR0(0), MT_AGG_ACR_CFEND_RATE, val);
mt76_rmw_field(dev, MT_TMAC_TCR0(mphy->band_idx), MT_TMAC_TCR0_TX_BLINK, 2);
mt76_rmw_field(dev, i, MT_LED_GPIO_SEL_MASK, 4);
mt76_rmw_field(dev, MT_DMA_DCR0(phy->mt76->band_idx),
mt76_rmw_field(dev, MT_MDP_DCR0,
mt76_rmw_field(dev, addr, GENMASK(31, 24), phy.sgi);
mt76_rmw_field(dev, addr, GENMASK(15, 12), phy.sgi);
mt76_rmw_field(dev, MT_BKOFF_SLOT_CFG,
mt76_rmw_field(dev, MT_TX_RTS_CFG, MT_TX_RTS_CFG_THRESH, value);