mvebu_writel
mvebu_writel(port, unmask, PCIE_INT_UNMASK_OFF);
mvebu_writel(port, unmask, PCIE_INT_UNMASK_OFF);
mvebu_writel(port, port->saved_pcie_stat, PCIE_STAT_OFF);
mvebu_writel(port, stat, PCIE_STAT_OFF);
mvebu_writel(port, cmd, PCIE_CMD_OFF);
mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_UNMASK_OFF);
mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_CAUSE_OFF);
mvebu_writel(port, sspl, PCIE_SSPL_OFF);
mvebu_writel(port, stat, PCIE_STAT_OFF);
mvebu_writel(port, 0, PCIE_BAR_LO_OFF(0));
mvebu_writel(port, 0, PCIE_BAR_HI_OFF(0));
mvebu_writel(port, 0, PCIE_BAR_CTRL_OFF(i));
mvebu_writel(port, 0, PCIE_BAR_LO_OFF(i));
mvebu_writel(port, 0, PCIE_BAR_HI_OFF(i));
mvebu_writel(port, 0, PCIE_WIN04_CTRL_OFF(i));
mvebu_writel(port, 0, PCIE_WIN04_BASE_OFF(i));
mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
mvebu_writel(port, 0, PCIE_WIN5_CTRL_OFF);
mvebu_writel(port, 0, PCIE_WIN5_BASE_OFF);
mvebu_writel(port, 0, PCIE_WIN5_REMAP_OFF);
mvebu_writel(port, cs->base & 0xffff0000,
mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
mvebu_writel(port,
mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1));
mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1));
mvebu_writel(port, ((size - 1) & 0xffff0000) | 1,
mvebu_writel(port, round_down(port->regs.start, SZ_1M), PCIE_BAR_LO_OFF(0));
mvebu_writel(port, 0, PCIE_BAR_HI_OFF(0));
mvebu_writel(port, ctrl, PCIE_CTRL_OFF);
mvebu_writel(port, lnkcap, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP);
mvebu_writel(port, cmd, PCIE_CMD_OFF);
mvebu_writel(port, dev_rev, PCIE_DEV_REV_OFF);
mvebu_writel(port, sspl, PCIE_SSPL_OFF);
mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_UNMASK_OFF);
mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_CAUSE_OFF);
mvebu_writel(port, unmask, PCIE_INT_UNMASK_OFF);
mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
mvebu_writel(port, new, PCIE_CMD_OFF);
mvebu_writel(port, ctrl, PCIE_CTRL_OFF);
mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL);
mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
mvebu_writel(port, sspl, PCIE_SSPL_OFF);
mvebu_writel(port, ~PCIE_INT_PM_PME, PCIE_INT_CAUSE_OFF);
mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL2);
mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL2);
mvebu_writel(port, new, PCIE_CAP_PCIERR_OFF + reg);