arch/x86/events/intel/core.c

2918

return mul_u64_u32_div(slots, val, 0xff);

arch/x86/include/asm/div64.h

126

#define mul_u64_u32_div mul_u64_u32_div

arch/x86/kvm/hyperv.c

1135

mul_u64_u32_div(1ULL << (32 + hv_clock->tsc_shift),

arch/x86/kvm/i8254.c

122

d = mul_u64_u32_div(t, KVM_PIT_FREQ, NSEC_PER_SEC);

arch/x86/kvm/i8254.c

149

d = mul_u64_u32_div(t, KVM_PIT_FREQ, NSEC_PER_SEC);

arch/x86/kvm/i8254.c

332

interval = mul_u64_u32_div(val, NSEC_PER_SEC, KVM_PIT_FREQ);

arch/x86/kvm/lapic.c

2115

ns_remaining_new = mul_u64_u32_div(ns_remaining_old,

arch/x86/kvm/x86.c

2548

ratio = mul_u64_u32_div(1ULL << kvm_caps.tsc_scaling_ratio_frac_bits,

drivers/accel/qaic/qaic_timesync.c

18

#define QAIC_CONV_QTIMER_TO_US(qtimer) (mul_u64_u32_div(qtimer, 10, 192))

drivers/dpll/zl3073x/ref.h

71

return mul_u64_u32_div(ref->freq_base * ref->freq_mult,

drivers/dpll/zl3073x/synth.h

57

return mul_u64_u32_div(synth->freq_base * synth->freq_m,

drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c

208

return mul_u64_u32_div(count, NSEC_PER_SEC, gt->clock_frequency);

drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c

218

return mul_u64_u32_div(ns, gt->clock_frequency, NSEC_PER_SEC);

drivers/gpu/drm/i915/gt/intel_rc6.c

847

return mul_u64_u32_div(time_hw, mul, div);

drivers/gpu/drm/xe/xe_gt_clock.c

83

return mul_u64_u32_div(count, MSEC_PER_SEC, gt->info.reference_clock);

drivers/gpu/drm/xe/xe_gt_idle.c

96

cur_residency = mul_u64_u32_div(cur_residency, gtidle->residency_multiplier, 1e6);

drivers/gpu/drm/xe/xe_guc_engine_activity.c

160

return mul_u64_u32_div(ns, freq, NSEC_PER_SEC);

drivers/gpu/drm/xe/xe_guc_submit.c

1328

#define ADJUST_FIVE_PERCENT(__t) mul_u64_u32_div(__t, 105, 100)

drivers/hwmon/ltc2992.c

628

*val = mul_u64_u32_div(reg_val, LTC2992_VADC_UV_LSB * LTC2992_IADC_NANOV_LSB,

drivers/hwmon/ltc2992.c

638

reg_val = mul_u64_u32_div(val, st->r_sense_uohm[channel] * 1000,

drivers/hwmon/macsmc-hwmon.c

134

*p = mul_u64_u32_div(val, scale, 65536);

drivers/hwmon/occ/common.c

426

mul_u64_u32_div(accum, 1000000UL, samples);

drivers/i2c/busses/i2c-rzv2m.c

115

trf_pclks = mul_u64_u32_div(pclk_hz, trf_ns, NSEC_PER_SEC);

drivers/iio/adc/ad4030.c

420

*val2 = mul_u64_u32_div(gain % AD4030_GAIN_MIDLE_POINT, NANO,

drivers/iio/adc/ad4695.c

1293

mul_u64_u32_div(val2, 1 << 16,

drivers/iio/dac/ltc2664.c

159

return mul_u64_u32_div(4800, fs, st->rfsadj_ohms);

drivers/iio/dac/ltc2664.c

161

return mul_u64_u32_div(LTC2672_SCALE_MULTIPLIER(span), fs, st->rfsadj_ohms);

drivers/media/pci/intel/ipu6/ipu6-isys-video.c

782

pixel_rate = mul_u64_u32_div(link_freq, lanes * 2, bpp);

drivers/pwm/pwm-airoha.c

141

return mul_u64_u32_div(duty_ns, AIROHA_PWM_DUTY_FULL, period_ns);

drivers/pwm/pwm-axi-pwmgen.c

106

mul_u64_u32_div(wf->duty_length_ns, ddata->clk_rate_hz, NSEC_PER_SEC),

drivers/pwm/pwm-axi-pwmgen.c

109

mul_u64_u32_div(wf->duty_offset_ns, ddata->clk_rate_hz, NSEC_PER_SEC),

drivers/pwm/pwm-axi-pwmgen.c

89

mul_u64_u32_div(wf->period_length_ns, ddata->clk_rate_hz, NSEC_PER_SEC),

drivers/pwm/pwm-rz-mtu3.c

333

period_cycles = mul_u64_u32_div(state->period, rz_mtu3_pwm->rate,

drivers/pwm/pwm-rz-mtu3.c

352

duty_cycles = mul_u64_u32_div(state->duty_cycle, rz_mtu3_pwm->rate,

drivers/pwm/pwm-xilinx.c

116

period_cycles = mul_u64_u32_div(period_cycles, rate, NSEC_PER_SEC);

drivers/pwm/pwm-xilinx.c

123

duty_cycles = mul_u64_u32_div(duty_cycles, rate, NSEC_PER_SEC);

drivers/spi/spi-imx.c

780

if (word_delay_ns <= mul_u64_u32_div(NSEC_PER_SEC,

drivers/spi/spi-imx.c

784

} else if (word_delay_ns <= mul_u64_u32_div(NSEC_PER_SEC,

drivers/spi/spi-imx.c

789

word_delay_ns -= mul_u64_u32_div(NSEC_PER_SEC,

fs/ufs/super.c

1156

uspi->s_root_blocks = mul_u64_u32_div(uspi->s_dsize,

fs/ufs/super.c

1164

uspi->s_space_to_time = mul_u64_u32_div(uspi->s_dsize,

include/linux/math64.h

267

#ifndef mul_u64_u32_div

kernel/time/timekeeping.c

1154

corr_real = mul_u64_u32_div