mt76_poll_msec
if (!mt76_poll_msec(dev, MT_MCU_DEBUG_RESET,
mt76_poll_msec(dev, addr, MT_CLIENT_RESET_TX_R_E_1_S,
mt76_poll_msec(dev, addr, MT_CLIENT_RESET_TX_R_E_2_S,
if (!mt76_poll_msec(dev, MT_TOP_MISC2, BIT(0) | BIT(1), BIT(0), 500)) {
if (!mt76_poll_msec(dev, MT_TOP_MISC2, BIT(1), BIT(1), 500)) {
if (!mt76_poll_msec(dev, reg, mask, 0, 1000)) {
if (!mt76_poll_msec(dev, MT_PDMA_BUSY_STATUS,
if (!mt76_poll_msec(dev, MT_PSE_PG_INFO,
if (!mt76_poll_msec(dev, MT_PDMA_BUSY_STATUS,
if (!mt76_poll_msec(dev, MT_TOP_MISC2, MT_TOP_MISC2_FW_STATE,
if (!mt76_poll_msec(dev, MT_TOP_OFF_RSV, MT_TOP_OFF_RSV_FW_STATE,
if (!mt76_poll_msec(dev, MT_CONN_ON_MISC, MT_TOP_MISC2_FW_N9_RDY,
err = !mt76_poll_msec(dev, addr, MT_CFG_LPCR_HOST_FW_OWN, 0, 3000);
if (mt76_poll_msec(dev, MT_CONN_HIF_ON_LPCTL,
!mt76_poll_msec(dev, addr, MT_CFG_LPCR_HOST_FW_OWN,
if (!mt76_poll_msec(dev, MT_PDMA_SLP_PROT,
if (!mt76_poll_msec(dev, MT_CONN_ON_MISC,
if (!mt76_poll_msec(dev, MT_CONN_ON_MISC, MT_TOP_MISC2_FW_PWR_ON,
if (!mt76_poll_msec(dev, MT_CONN_ON_MISC,
if (!mt76_poll_msec(dev, MT_CONN_ON_MISC,
if (!mt76_poll_msec(dev, MT_MCU_COM_REG0, 1, 1, 1000)) {
if (!mt76_poll_msec(dev, MT_BBP(CORE, 34), BIT(4), 0, 200)) {
mt76_poll_msec(dev, MT_BBP(CORE, 34), BIT(4), 0, 200);
if (!mt76_poll_msec(dev, MT_BBP(CORE, 34), BIT(4), 0, 200)) {
if (!mt76_poll_msec(dev, MT_MCU_COM_REG0, 1, 1, 1000)) {
if (!mt76_poll_msec(dev, MT_EFUSE_CTRL, MT_EFUSE_CTRL_KICK, 0, 1000))
WARN_ON(!mt76_poll_msec(dev, MT_MCU_COM_REG0,
if (!mt76_poll_msec(dev, MT_MCU_COM_REG0, 1, 1, 200)) {
if (!mt76_poll_msec(dev, patch_reg, patch_mask, patch_mask, 2000)) {
if (!mt76_poll_msec(dev, MT_WPDMA_GLO_CFG,
if (!mt76_poll_msec(dev, patch_reg, patch_mask, patch_mask, 100)) {
if (!mt76_poll_msec(dev, MT_MCU_COM_REG0, 1, 1, 100)) {
!mt76_poll_msec(dev, MT_MCU_SEMAPHORE_03, 1, 1, 600)) {
if (!mt76_poll_msec(dev, MT_MCU_WFDMA0_DUMMY_CR,
if (!mt76_poll_msec(dev, MT_TOP_LPCR_HOST_BAND(band),
if (!mt76_poll_msec(dev, MT_TOP_MISC, MT_TOP_MISC_FW_STATE,
if (!mt76_poll_msec(dev, reg, MT_TOP_LPCR_HOST_FW_OWN,
if (!mt76_poll_msec(dev, MT_CONN_ON_MISC, MT_TOP_MISC2_FW_N9_RDY,
if (!mt76_poll_msec(dev, MT_CONN_ON_MISC, MT_TOP_MISC2_FW_PWR_ON,
!mt76_poll_msec(dev, MT_FW_DUMP_STATE, 0x3, 0x2, 500))
if (!mt76_poll_msec(dev, MT_TOP_LPCR_HOST_BAND(band),
if (!mt76_poll_msec(dev, MT_TOP_MISC, MT_TOP_MISC_FW_STATE,
if (!mt76_poll_msec(dev, MT_WPDMA_GLO_CFG,
if (!mt76_poll_msec(dev, MT_MAC_STATUS,
if (!mt76_poll_msec(dev, MT_MCU_COM_REG1, BIT(31), BIT(31), 500))
bool mt76_poll_msec(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val,