mt76_get_field
page_count = mt76_get_field(dev, MT_PSE_FC_P0,
qlen += mt76_get_field(dev, MT_PLE_FL_Q3_CTRL,
busy_time = mt76_get_field(dev, MT_MIB_SDR9(idx),
tx_time = mt76_get_field(dev, MT_MIB_SDR36(idx),
rx_time = mt76_get_field(dev, MT_MIB_SDR37(idx),
obss_time = mt76_get_field(dev, obss_reg, MT_MIB_OBSSTIME_MASK);
mib->fcs_err_cnt += mt76_get_field(dev, MT_MIB_SDR3(ext_phy),
val = mt76_get_field(dev, MT_MIB_SDR14(ext_phy),
val2 = mt76_get_field(dev, MT_MIB_SDR15(ext_phy),
val = mt76_get_field(dev, MT_TOP_MISC2, MT_TOP_MISC2_FW_STATE);
val = mt76_get_field(dev, MT_TOP_OFF_RSV, MT_TOP_OFF_RSV_FW_STATE);
ret = mt76_get_field(dev, MT_CONN_ON_MISC, MT_TOP_MISC2_FW_N9_RDY);
ret = mt76_get_field(dev, MT_CONN_ON_MISC,
ret = mt76_get_field(dev, MT_CONN_ON_MISC, MT_TOP_MISC2_FW_N9_RDY);
sdio->sched.pse_data_quota = mt76_get_field(dev, MT_PSE_PG_HIF0_GROUP,
sdio->sched.pse_mcu_quota = mt76_get_field(dev, MT_PSE_PG_HIF1_GROUP,
sdio->sched.ple_data_quota = mt76_get_field(dev, MT_PLE_PG_HIF0_GROUP,
txdwcnt = mt76_get_field(dev, MT_PP_TXDWCNT,
ret = mt76_get_field(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP);
rts_thr = mt76_get_field(dev, MT_TX_RTS_CFG, MT_TX_RTS_CFG_THRESH);
dev->cal.agc_gain_init[0] = mt76_get_field(dev, MT_BBP(AGC, 8),
dev->cal.agc_gain_init[1] = mt76_get_field(dev, MT_BBP(AGC, 9),
tbtt = mt76_get_field(dev, MT_TBTT_TIMER, MT_TBTT_TIMER_VAL);
tbtt = mt76_get_field(dev, MT_TBTT_TIMER, MT_TBTT_TIMER_VAL);
sifs = mt76_get_field(dev, MT_XIFS_TIME_CFG,
temp = mt76_get_field(dev, MT_TEMP_SENSOR, MT_TEMP_SENSOR_VAL);
type = (u32)mt76_get_field(dev, MT_FW_EXCEPT_TYPE, GENMASK(7, 0));
state = (u32)mt76_get_field(dev, MT_FW_ASSERT_STAT, GENMASK(7, 0));
(u32)mt76_get_field(dev, MT_FW_EXCEPT_COUNT, GENMASK(15, 8)) :
(u32)mt76_get_field(dev, MT_FW_EXCEPT_COUNT, GENMASK(7, 0));
(u32)mt76_get_field(dev, base, GENMASK(7, 0)) :
(u32)mt76_get_field(dev, base, GENMASK(15, 8));
oldest = (u32)mt76_get_field(dev, 0x89050200, GENMASK(20, 16)) + 2;
(u32)mt76_get_field(dev, MT_FW_CIRQ_IDX, GENMASK(31, 16)) :
(u32)mt76_get_field(dev, MT_FW_CIRQ_IDX, GENMASK(15, 0));
mt76_get_field(dev, reg, MT_WF_PHY_TPC_POWER));
head = mt76_get_field(dev, MT_FL_Q2_CTRL,
tail = mt76_get_field(dev, MT_FL_Q2_CTRL,
queued = mt76_get_field(dev, MT_FL_Q3_CTRL,
qlen = mt76_get_field(dev, MT_FL_Q3_CTRL,
head = mt76_get_field(dev, MT_PLE_FREEPG_HEAD_TAIL, GENMASK(11, 0));
tail = mt76_get_field(dev, MT_PLE_FREEPG_HEAD_TAIL, GENMASK(27, 16));
head = mt76_get_field(dev, MT_PLE_HIF_PG_INFO, GENMASK(11, 0));
tail = mt76_get_field(dev, MT_PLE_HIF_PG_INFO, GENMASK(27, 16));
txv_time = mt76_get_field(dev, MT_TMAC_ATCR(band),
if (mt76_get_field(dev, MT_CONN_ON_MISC, MT_TOP_MISC2_FW_N9_RDY)) {
if (mt76_get_field(dev, MT_CONN_ON_MISC, MT_TOP_MISC2_FW_N9_RDY)) {
return !mt76_get_field(dev, MT_WFDMA_DUMMY_CR, MT_WFDMA_NEED_REINIT);
qlen += mt76_get_field(dev, MT_PLE_FL_Q3_CTRL,
busy_time = mt76_get_field(dev, MT_MIB_SDR9(idx),
tx_time = mt76_get_field(dev, MT_MIB_SDR36(idx),
rx_time = mt76_get_field(dev, MT_MIB_SDR37(idx),
obss_time = mt76_get_field(dev, MT_WF_RMAC_MIB_AIRTIME14(idx),
mib->fcs_err_cnt += mt76_get_field(dev, MT_MIB_SDR3(0),
mib->ack_fail_cnt += mt76_get_field(dev, MT_MIB_MB_BSDR3(0),
mib->ba_miss_cnt += mt76_get_field(dev, MT_MIB_MB_BSDR2(0),
mib->rts_cnt += mt76_get_field(dev, MT_MIB_MB_BSDR0(0),
mib->rts_retries_cnt += mt76_get_field(dev, MT_MIB_MB_BSDR1(0),
oldest = (u32)mt76_get_field(dev, MT_MCU_WM_EXCP_PC_CTRL,
oldest = (u32)mt76_get_field(dev, MT_MCU_WM_EXCP_LR_CTRL,
head = mt76_get_field(dev, MT_FL_Q2_CTRL,
tail = mt76_get_field(dev, MT_FL_Q2_CTRL,
queued = mt76_get_field(dev, MT_FL_Q3_CTRL,
qlen = mt76_get_field(dev, MT_FL_Q3_CTRL,
head = mt76_get_field(dev, MT_PLE_FREEPG_HEAD_TAIL, GENMASK(11, 0));
tail = mt76_get_field(dev, MT_PLE_FREEPG_HEAD_TAIL, GENMASK(27, 16));
head = mt76_get_field(dev, MT_PLE_HIF_PG_INFO, GENMASK(11, 0));
tail = mt76_get_field(dev, MT_PLE_HIF_PG_INFO, GENMASK(27, 16));