drivers/gpu/drm/msm/dp/dp_ctrl.c

117

struct msm_dp_panel *panel;

drivers/gpu/drm/msm/dp/dp_ctrl.c

2745

struct msm_dp_panel *panel, struct drm_dp_aux *aux,

drivers/gpu/drm/msm/dp/dp_ctrl.h

29

struct msm_dp_panel *panel,

drivers/gpu/drm/msm/dp/dp_debug.c

201

int msm_dp_debug_init(struct device *dev, struct msm_dp_panel *panel,

drivers/gpu/drm/msm/dp/dp_debug.c

23

struct msm_dp_panel *panel;

drivers/gpu/drm/msm/dp/dp_debug.h

28

int msm_dp_debug_init(struct device *dev, struct msm_dp_panel *panel,

drivers/gpu/drm/msm/dp/dp_debug.h

37

int msm_dp_debug_init(struct device *dev, struct msm_dp_panel *panel,

drivers/gpu/drm/msm/dp/dp_display.c

1708

struct msm_dp_panel *msm_dp_panel;

drivers/gpu/drm/msm/dp/dp_display.c

1711

msm_dp_panel = msm_dp_display->panel;

drivers/gpu/drm/msm/dp/dp_display.c

1733

msm_dp_panel->vsc_sdp_supported;

drivers/gpu/drm/msm/dp/dp_display.c

91

struct msm_dp_panel *panel;

drivers/gpu/drm/msm/dp/dp_panel.c

102

msm_dp_panel->vsc_sdp_supported = drm_dp_vsc_sdp_supported(panel->aux, dpcd);

drivers/gpu/drm/msm/dp/dp_panel.c

103

link_info = &msm_dp_panel->link_info;

drivers/gpu/drm/msm/dp/dp_panel.c

116

if (msm_dp_panel->dpcd[DP_EDP_CONFIGURATION_CAP]) {

drivers/gpu/drm/msm/dp/dp_panel.c

214

static u32 msm_dp_panel_get_supported_bpp(struct msm_dp_panel *msm_dp_panel,

drivers/gpu/drm/msm/dp/dp_panel.c

223

link_info = &msm_dp_panel->link_info;

drivers/gpu/drm/msm/dp/dp_panel.c

235

int msm_dp_panel_read_sink_caps(struct msm_dp_panel *msm_dp_panel,

drivers/gpu/drm/msm/dp/dp_panel.c

24

struct msm_dp_panel msm_dp_panel;

drivers/gpu/drm/msm/dp/dp_panel.c

242

if (!msm_dp_panel || !connector) {

drivers/gpu/drm/msm/dp/dp_panel.c

247

panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel);

drivers/gpu/drm/msm/dp/dp_panel.c

249

rc = msm_dp_panel_read_dpcd(msm_dp_panel);

drivers/gpu/drm/msm/dp/dp_panel.c

255

bw_code = drm_dp_link_rate_to_bw_code(msm_dp_panel->link_info.rate);

drivers/gpu/drm/msm/dp/dp_panel.c

257

!is_lane_count_valid(msm_dp_panel->link_info.num_lanes) ||

drivers/gpu/drm/msm/dp/dp_panel.c

258

(bw_code > msm_dp_panel->max_bw_code)) {

drivers/gpu/drm/msm/dp/dp_panel.c

259

DRM_ERROR("Illegal link rate=%d lane=%d\n", msm_dp_panel->link_info.rate,

drivers/gpu/drm/msm/dp/dp_panel.c

260

msm_dp_panel->link_info.num_lanes);

drivers/gpu/drm/msm/dp/dp_panel.c

264

if (drm_dp_is_branch(msm_dp_panel->dpcd)) {

drivers/gpu/drm/msm/dp/dp_panel.c

272

rc = drm_dp_read_downstream_info(panel->aux, msm_dp_panel->dpcd,

drivers/gpu/drm/msm/dp/dp_panel.c

273

msm_dp_panel->downstream_ports);

drivers/gpu/drm/msm/dp/dp_panel.c

277

drm_edid_free(msm_dp_panel->drm_edid);

drivers/gpu/drm/msm/dp/dp_panel.c

279

msm_dp_panel->drm_edid = drm_edid_read_ddc(connector, &panel->aux->ddc);

drivers/gpu/drm/msm/dp/dp_panel.c

281

drm_edid_connector_update(connector, msm_dp_panel->drm_edid);

drivers/gpu/drm/msm/dp/dp_panel.c

283

if (!msm_dp_panel->drm_edid) {

drivers/gpu/drm/msm/dp/dp_panel.c

296

u32 msm_dp_panel_get_mode_bpp(struct msm_dp_panel *msm_dp_panel,

drivers/gpu/drm/msm/dp/dp_panel.c

302

if (!msm_dp_panel || !mode_edid_bpp || !mode_pclk_khz) {

drivers/gpu/drm/msm/dp/dp_panel.c

307

panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel);

drivers/gpu/drm/msm/dp/dp_panel.c

309

if (msm_dp_panel->video_test)

drivers/gpu/drm/msm/dp/dp_panel.c

313

bpp = msm_dp_panel_get_supported_bpp(msm_dp_panel, mode_edid_bpp,

drivers/gpu/drm/msm/dp/dp_panel.c

319

int msm_dp_panel_get_modes(struct msm_dp_panel *msm_dp_panel,

drivers/gpu/drm/msm/dp/dp_panel.c

322

if (!msm_dp_panel) {

drivers/gpu/drm/msm/dp/dp_panel.c

327

if (msm_dp_panel->drm_edid)

drivers/gpu/drm/msm/dp/dp_panel.c

340

void msm_dp_panel_handle_sink_request(struct msm_dp_panel *msm_dp_panel)

drivers/gpu/drm/msm/dp/dp_panel.c

344

if (!msm_dp_panel) {

drivers/gpu/drm/msm/dp/dp_panel.c

349

panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel);

drivers/gpu/drm/msm/dp/dp_panel.c

353

const struct edid *edid = drm_edid_raw(msm_dp_panel->drm_edid);

drivers/gpu/drm/msm/dp/dp_panel.c

359

checksum = msm_dp_panel->connector->real_edid_checksum;

drivers/gpu/drm/msm/dp/dp_panel.c

366

static void msm_dp_panel_tpg_enable(struct msm_dp_panel *msm_dp_panel,

drivers/gpu/drm/msm/dp/dp_panel.c

370

container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel);

drivers/gpu/drm/msm/dp/dp_panel.c

433

static void msm_dp_panel_tpg_disable(struct msm_dp_panel *msm_dp_panel)

drivers/gpu/drm/msm/dp/dp_panel.c

436

container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel);

drivers/gpu/drm/msm/dp/dp_panel.c

443

void msm_dp_panel_tpg_config(struct msm_dp_panel *msm_dp_panel, bool enable)

drivers/gpu/drm/msm/dp/dp_panel.c

447

if (!msm_dp_panel) {

drivers/gpu/drm/msm/dp/dp_panel.c

452

panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel);

drivers/gpu/drm/msm/dp/dp_panel.c

461

msm_dp_panel_tpg_disable(msm_dp_panel);

drivers/gpu/drm/msm/dp/dp_panel.c

466

msm_dp_panel_tpg_enable(msm_dp_panel, &panel->msm_dp_panel.msm_dp_mode.drm_mode);

drivers/gpu/drm/msm/dp/dp_panel.c

469

void msm_dp_panel_clear_dsc_dto(struct msm_dp_panel *msm_dp_panel)

drivers/gpu/drm/msm/dp/dp_panel.c

472

container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel);

drivers/gpu/drm/msm/dp/dp_panel.c

497

u32 hw_revision = panel->msm_dp_panel.hw_revision;

drivers/gpu/drm/msm/dp/dp_panel.c

506

void msm_dp_panel_enable_vsc_sdp(struct msm_dp_panel *msm_dp_panel, struct dp_sdp *vsc_sdp)

drivers/gpu/drm/msm/dp/dp_panel.c

509

container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel);

drivers/gpu/drm/msm/dp/dp_panel.c

535

void msm_dp_panel_disable_vsc_sdp(struct msm_dp_panel *msm_dp_panel)

drivers/gpu/drm/msm/dp/dp_panel.c

538

container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel);

drivers/gpu/drm/msm/dp/dp_panel.c

562

static int msm_dp_panel_setup_vsc_sdp_yuv_420(struct msm_dp_panel *msm_dp_panel)

drivers/gpu/drm/msm/dp/dp_panel.c

569

if (!msm_dp_panel) {

drivers/gpu/drm/msm/dp/dp_panel.c

574

msm_dp_mode = &msm_dp_panel->msm_dp_mode;

drivers/gpu/drm/msm/dp/dp_panel.c

600

msm_dp_panel_enable_vsc_sdp(msm_dp_panel, &vsc_sdp);

drivers/gpu/drm/msm/dp/dp_panel.c

605

int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_bus_en)

drivers/gpu/drm/msm/dp/dp_panel.c

616

panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel);

drivers/gpu/drm/msm/dp/dp_panel.c

617

drm_mode = &panel->msm_dp_panel.msm_dp_mode.drm_mode;

drivers/gpu/drm/msm/dp/dp_panel.c

647

data |= (panel->msm_dp_panel.msm_dp_mode.v_active_low << 31);

drivers/gpu/drm/msm/dp/dp_panel.c

649

data |= (panel->msm_dp_panel.msm_dp_mode.h_active_low << 15);

drivers/gpu/drm/msm/dp/dp_panel.c

674

if (msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420)

drivers/gpu/drm/msm/dp/dp_panel.c

675

msm_dp_panel_setup_vsc_sdp_yuv_420(msm_dp_panel);

drivers/gpu/drm/msm/dp/dp_panel.c

682

int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel)

drivers/gpu/drm/msm/dp/dp_panel.c

687

drm_mode = &msm_dp_panel->msm_dp_mode.drm_mode;

drivers/gpu/drm/msm/dp/dp_panel.c

689

panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel);

drivers/gpu/drm/msm/dp/dp_panel.c

70

struct msm_dp_panel *msm_dp_panel;

drivers/gpu/drm/msm/dp/dp_panel.c

710

drm_dbg_dp(panel->drm_dev, "bpp = %d\n", msm_dp_panel->msm_dp_mode.bpp);

drivers/gpu/drm/msm/dp/dp_panel.c

712

msm_dp_panel->msm_dp_mode.bpp = msm_dp_panel_get_mode_bpp(msm_dp_panel, msm_dp_panel->msm_dp_mode.bpp,

drivers/gpu/drm/msm/dp/dp_panel.c

713

msm_dp_panel->msm_dp_mode.drm_mode.clock);

drivers/gpu/drm/msm/dp/dp_panel.c

716

msm_dp_panel->msm_dp_mode.bpp);

drivers/gpu/drm/msm/dp/dp_panel.c

72

msm_dp_panel = &panel->msm_dp_panel;

drivers/gpu/drm/msm/dp/dp_panel.c

721

struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_aux *aux,

drivers/gpu/drm/msm/dp/dp_panel.c

727

struct msm_dp_panel *msm_dp_panel;

drivers/gpu/drm/msm/dp/dp_panel.c

744

msm_dp_panel = &panel->msm_dp_panel;

drivers/gpu/drm/msm/dp/dp_panel.c

745

msm_dp_panel->max_bw_code = DP_LINK_BW_8_1;

drivers/gpu/drm/msm/dp/dp_panel.c

747

return msm_dp_panel;

drivers/gpu/drm/msm/dp/dp_panel.c

75

if (msm_dp_panel->dpcd[DP_EDP_CONFIGURATION_CAP]) {

drivers/gpu/drm/msm/dp/dp_panel.c

750

void msm_dp_panel_put(struct msm_dp_panel *msm_dp_panel)

drivers/gpu/drm/msm/dp/dp_panel.c

752

if (!msm_dp_panel)

drivers/gpu/drm/msm/dp/dp_panel.c

755

drm_edid_free(msm_dp_panel->drm_edid);

drivers/gpu/drm/msm/dp/dp_panel.c

77

&msm_dp_panel->psr_cap, sizeof(msm_dp_panel->psr_cap));

drivers/gpu/drm/msm/dp/dp_panel.c

78

if (rlen == sizeof(msm_dp_panel->psr_cap)) {

drivers/gpu/drm/msm/dp/dp_panel.c

81

msm_dp_panel->psr_cap.version,

drivers/gpu/drm/msm/dp/dp_panel.c

82

msm_dp_panel->psr_cap.capabilities);

drivers/gpu/drm/msm/dp/dp_panel.c

88

static int msm_dp_panel_read_dpcd(struct msm_dp_panel *msm_dp_panel)

drivers/gpu/drm/msm/dp/dp_panel.c

96

panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel);

drivers/gpu/drm/msm/dp/dp_panel.c

97

dpcd = msm_dp_panel->dpcd;

drivers/gpu/drm/msm/dp/dp_panel.h

47

int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel);

drivers/gpu/drm/msm/dp/dp_panel.h

48

int msm_dp_panel_deinit(struct msm_dp_panel *msm_dp_panel);

drivers/gpu/drm/msm/dp/dp_panel.h

49

int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_bus_en);

drivers/gpu/drm/msm/dp/dp_panel.h

50

int msm_dp_panel_read_sink_caps(struct msm_dp_panel *msm_dp_panel,

drivers/gpu/drm/msm/dp/dp_panel.h

52

u32 msm_dp_panel_get_mode_bpp(struct msm_dp_panel *msm_dp_panel, u32 mode_max_bpp,

drivers/gpu/drm/msm/dp/dp_panel.h

54

int msm_dp_panel_get_modes(struct msm_dp_panel *msm_dp_panel,

drivers/gpu/drm/msm/dp/dp_panel.h

56

void msm_dp_panel_handle_sink_request(struct msm_dp_panel *msm_dp_panel);

drivers/gpu/drm/msm/dp/dp_panel.h

57

void msm_dp_panel_tpg_config(struct msm_dp_panel *msm_dp_panel, bool enable);

drivers/gpu/drm/msm/dp/dp_panel.h

59

void msm_dp_panel_clear_dsc_dto(struct msm_dp_panel *msm_dp_panel);

drivers/gpu/drm/msm/dp/dp_panel.h

61

void msm_dp_panel_enable_vsc_sdp(struct msm_dp_panel *msm_dp_panel, struct dp_sdp *vsc_sdp);

drivers/gpu/drm/msm/dp/dp_panel.h

62

void msm_dp_panel_disable_vsc_sdp(struct msm_dp_panel *msm_dp_panel);

drivers/gpu/drm/msm/dp/dp_panel.h

91

struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_aux *aux,

drivers/gpu/drm/msm/dp/dp_panel.h

95

void msm_dp_panel_put(struct msm_dp_panel *msm_dp_panel);