mcf_write32
mcf_write32(0x00000000, DTRR0);
mcf_write32(0x1, MCFICM_INTC0 + MCFINTC_IMRL);
mcf_write32(0x1, MCFICM_INTC1 + MCFINTC_IMRL);
mcf_write32(val | imrbit, imraddr);
mcf_write32(val & ~imrbit, imraddr);
mcf_write32(imr, MCFSIM2_GPIOINTENABLE);
mcf_write32(imr, MCFSIM2_GPIOINTENABLE);
mcf_write32(0x1 << (d->irq - MCF_IRQ_GPIO0), MCFSIM2_GPIOINTCLEAR);
mcf_write32(imr, MCFSIM2_GPIOINTENABLE);
mcf_write32(imr, MCFSIM2_GPIOINTENABLE);
mcf_write32(imr, MCFSIM2_GPIOINTCLEAR);
mcf_write32(MCFINTC2_VECBASE, MCFINTC2_INTBASE);
mcf_write32(v, intc_irqmap[irq].icr);
mcf_write32(v, intc_irqmap[irq].icr);
mcf_write32(v, MCFSIM_PITR);
mcf_write32(0x88888888, MCFSIM_ICR1);
mcf_write32(0x88888888, MCFSIM_ICR2);
mcf_write32(0x88888888, MCFSIM_ICR3);
mcf_write32(0x88888888, MCFSIM_ICR4);
mcf_write32(v, intc_irqmap[irq].icr);
mcf_write32(imr | (0x1 << index), MCFSIM_IMR);
mcf_write32(imr & ~(0x1 << index), MCFSIM_IMR);
mcf_write32(imr, MCFSIM_IMR);
mcf_write32(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
mcf_write32(gpio | 0x40, MCFSIM2_GPIOINTENABLE);
mcf_write32(gpio | 0x04000000, MCFINTC2_INTPRI5);
mcf_write32(f, MCFSIM2_GPIOFUNC);
mcf_write32(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
mcf_write32(v, MCFSIM_PBCNT);
mcf_write32(v, MCFSIM_PDCNT);
mcf_write32(0x77777777, MCF_SCM_MPR);
mcf_write32(0, MCF_SCM_PACRA);
mcf_write32(0, MCF_SCM_PACRB);
mcf_write32(0, MCF_SCM_PACRC);
mcf_write32(0, MCF_SCM_PACRD);
mcf_write32(0, MCF_SCM_PACRE);
mcf_write32(0, MCF_SCM_PACRF);
mcf_write32(MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW, MCF_SCM_BCR);
mcf_write32(0x10080000, MCF_FBCS1_CSAR);
mcf_write32(0x002A3780, MCF_FBCS1_CSCR);
mcf_write32(MCF_FBCS_CSMR_BAM_2M | MCF_FBCS_CSMR_V, MCF_FBCS1_CSMR);
mcf_write32(EXT_SRAM_ADDRESS, MCF_FBCS1_CSAR);
mcf_write32(MCF_FBCS_CSCR_PS_16 |
mcf_write32(MCF_FBCS_CSMR_BAM_512K | MCF_FBCS_CSMR_V, MCF_FBCS1_CSMR);
mcf_write32(FLASH_ADDRESS, MCF_FBCS0_CSAR);
mcf_write32(MCF_FBCS_CSCR_PS_16 |
mcf_write32(MCF_FBCS_CSMR_BAM_32M | MCF_FBCS_CSMR_V, MCF_FBCS0_CSMR);
mcf_write32(MCF_SDRAMC_SDCS_BA(SDRAM_ADDRESS) |
mcf_write32(MCF_SDRAMC_SDCFG1_SRD2RW((int)((SDRAM_CASL + 2) + 0.5)) |
mcf_write32(MCF_SDRAMC_SDCFG2_BRD2PRE(SDRAM_BL / 2 + 1) |
mcf_write32(MCF_SDRAMC_SDCR_MODE_EN |
mcf_write32(MCF_SDRAMC_SDMR_BNKAD_LEMR |
mcf_write32(MCF_SDRAMC_SDMR_BNKAD_LMR |
mcf_write32(mcf_read32(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IPALL, MCF_SDRAMC_SDCR);
mcf_write32(mcf_read32(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IREF, MCF_SDRAMC_SDCR);
mcf_write32(mcf_read32(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IREF, MCF_SDRAMC_SDCR);
mcf_write32(MCF_SDRAMC_SDMR_BNKAD_LMR |
mcf_write32(mcf_read32(MCF_SDRAMC_SDCR) & ~MCF_SDRAMC_SDCR_MODE_EN,
mcf_write32(MCF_SDRAMC_SDCR_REF | MCF_SDRAMC_SDCR_DQS_OE(0xC),
mcf_write32(mcf_read32(MCF_SDRAMC_SDCR) & ~MCF_SDRAMC_SDCR_CKE,
mcf_write32(mcf_read32(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_CKE,
mcf_write32(MCF_SDRAMC_REFRESH, MCF_SDRAMC_LIMP_FIX);
mcf_write32(mcf_read32(MCFSDHC_CLK) | (1 << clk->slot), MCFSDHC_CLK);
mcf_write32(mcf_read32(MCFSDHC_CLK) & ~(1 << clk->slot), MCFSDHC_CLK);
mcf_write32(r, MCF_PAR_FECI2CIRQ);
mcf_write32(0, MCF_GPT_GMS0);
mcf_write32(MCF_GPT_GCIR_CNT(1), MCF_GPT_GCIR0);
mcf_write32(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4),
mcf_write32(PCICAR_E | addr, PCICAR);
mcf_write32(cpu_to_le32(value), addr);
mcf_write32(0, PCICAR);
mcf_write32(PCIGSCR_RESET, PCIGSCR);
mcf_write32(0, PCITCR);
mcf_write32(PACR_INTMPRI | PACR_INTMINTE | PACR_EXTMPRI(0x1f) |
mcf_write32(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
mcf_write32(PCICR1_LT(32) | PCICR1_CL(8), PCICR1);
mcf_write32(0, PCICR2);
mcf_write32(WXBTAR(PCI_MEM_PA, PCI_MEM_BA, PCI_MEM_SIZE),
mcf_write32(WXBTAR(PCI_IO_PA, PCI_IO_BA, PCI_IO_SIZE),
mcf_write32(PCIIWCR_W0_MEM /*| PCIIWCR_W0_MRDL*/ | PCIIWCR_W0_E |
mcf_write32(CONFIG_RAMBASE, PCIBAR1);
mcf_write32(CONFIG_RAMBASE | PCITBATR1_E, PCITBATR1);
mcf_write32(0, PCIGSCR);
mcf_write32(PCICAR_E | addr, PCICAR);
mcf_write32(0, PCICAR);
mcf_write32(mcfslt_cycles_per_jiffy - 1, TA(MCFSLT_STCNT));
mcf_write32(MCFSLT_SCR_RUN | MCFSLT_SCR_IEN | MCFSLT_SCR_TEN,
mcf_write32(MCFSLT_SSR_BE | MCFSLT_SSR_TE, PA(MCFSLT_SSR));
mcf_write32(MCF_BUSCLK / PROFILEHZ - 1, PA(MCFSLT_STCNT));
mcf_write32(MCFSLT_SCR_RUN | MCFSLT_SCR_IEN | MCFSLT_SCR_TEN,
mcf_write32(MCFSLT_SSR_BE | MCFSLT_SSR_TE, TA(MCFSLT_SSR));
#define mcf_writetrr mcf_write32
#define mcfgpio_write(data, port) mcf_write32(data, port)