Symbol: mcf_write8
arch/m68k/coldfire/clk.c
45
mcf_write8(clk->slot, MCFPM_PPMCR0);
arch/m68k/coldfire/clk.c
50
mcf_write8(clk->slot, MCFPM_PPMSR0);
arch/m68k/coldfire/clk.c
61
mcf_write8(clk->slot, MCFPM_PPMCR1);
arch/m68k/coldfire/clk.c
66
mcf_write8(clk->slot, MCFPM_PPMSR1);
arch/m68k/coldfire/device.c
672
mcf_write8(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCFSIM_UART1ICR);
arch/m68k/coldfire/device.c
673
mcf_write8(MCF_IRQ_UART0, MCFUART_BASE0 + MCFUART_UIVR);
arch/m68k/coldfire/device.c
677
mcf_write8(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCFSIM_UART2ICR);
arch/m68k/coldfire/device.c
678
mcf_write8(MCF_IRQ_UART1, MCFUART_BASE1 + MCFUART_UIVR);
arch/m68k/coldfire/dma_timer.c
59
mcf_write8(0x00, DTXMR0);
arch/m68k/coldfire/dma_timer.c
60
mcf_write8(0x00, DTER0);
arch/m68k/coldfire/intc-2.c
100
mcf_write8(0x1 << (irq - EINT0), MCFEPORT_EPFR);
arch/m68k/coldfire/intc-2.c
124
mcf_write8(intc_intpri--, icraddr);
arch/m68k/coldfire/intc-2.c
134
mcf_write8(v & ~(0x1 << irq), MCFEPORT_EPDDR);
arch/m68k/coldfire/intc-2.c
138
mcf_write8(v | (0x1 << irq), MCFEPORT_EPIER);
arch/m68k/coldfire/intc-simr.c
109
mcf_write8(v & ~(0x1 << ebit), MCFEPORT_EPDDR);
arch/m68k/coldfire/intc-simr.c
114
mcf_write8(v | (0x1 << ebit), MCFEPORT_EPIER);
arch/m68k/coldfire/intc-simr.c
119
mcf_write8(5, MCFINTC2_ICR0 + irq - 128);
arch/m68k/coldfire/intc-simr.c
121
mcf_write8(5, MCFINTC1_ICR0 + irq - 64);
arch/m68k/coldfire/intc-simr.c
123
mcf_write8(5, MCFINTC0_ICR0 + irq);
arch/m68k/coldfire/intc-simr.c
182
mcf_write8(0xff, MCFINTC0_SIMR);
arch/m68k/coldfire/intc-simr.c
184
mcf_write8(0xff, MCFINTC1_SIMR);
arch/m68k/coldfire/intc-simr.c
186
mcf_write8(0xff, MCFINTC2_SIMR);
arch/m68k/coldfire/intc-simr.c
72
mcf_write8(irq - 128, MCFINTC2_SIMR);
arch/m68k/coldfire/intc-simr.c
74
mcf_write8(irq - 64, MCFINTC1_SIMR);
arch/m68k/coldfire/intc-simr.c
76
mcf_write8(irq, MCFINTC0_SIMR);
arch/m68k/coldfire/intc-simr.c
84
mcf_write8(irq - 128, MCFINTC2_CIMR);
arch/m68k/coldfire/intc-simr.c
86
mcf_write8(irq - 64, MCFINTC1_CIMR);
arch/m68k/coldfire/intc-simr.c
88
mcf_write8(irq, MCFINTC0_CIMR);
arch/m68k/coldfire/intc-simr.c
95
mcf_write8(0x1 << ebit, MCFEPORT_EPFR);
arch/m68k/coldfire/intc.c
109
mcf_write8(avec, MCFSIM_AVR);
arch/m68k/coldfire/m5206.c
43
mcf_write8(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
arch/m68k/coldfire/m520x.c
128
mcf_write8(0x3f, MCF_GPIO_PAR_QSPI);
arch/m68k/coldfire/m520x.c
147
mcf_write8(par, MCF_GPIO_PAR_FECI2C);
arch/m68k/coldfire/m520x.c
169
mcf_write8(par2, MCF_GPIO_PAR_FECI2C);
arch/m68k/coldfire/m520x.c
180
mcf_write8(v | 0xf0, MCF_GPIO_PAR_FEC);
arch/m68k/coldfire/m520x.c
183
mcf_write8(v | 0x0f, MCF_GPIO_PAR_FECI2C);
arch/m68k/coldfire/m523x.c
54
mcf_write8(0x1f, MCFGPIO_PAR_QSPI);
arch/m68k/coldfire/m523x.c
73
mcf_write8(par, MCFGPIO_PAR_FECI2C);
arch/m68k/coldfire/m523x.c
82
mcf_write8(mcf_read8(MCFGPIO_PAR_FECI2C) | 0xf0, MCFGPIO_PAR_FECI2C);
arch/m68k/coldfire/m5249.c
78
mcf_write8(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
arch/m68k/coldfire/m5249.c
92
mcf_write8(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
arch/m68k/coldfire/m525x.c
52
mcf_write8(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
arch/m68k/coldfire/m525x.c
64
mcf_write8(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
arch/m68k/coldfire/m5272.c
86
mcf_write8(0x40, MCFSIM_PIVR);
arch/m68k/coldfire/m527x.c
117
mcf_write8(v | 0xf0, MCFGPIO_PAR_FECI2C);
arch/m68k/coldfire/m527x.c
124
mcf_write8(v | 0xc0, MCFGPIO_PAR_FEC0HL);
arch/m68k/coldfire/m527x.c
130
mcf_write8(v | 0xc0, MCFGPIO_PAR_FEC1HL);
arch/m68k/coldfire/m527x.c
57
mcf_write8(0x1f, MCFGPIO_PAR_QSPI);
arch/m68k/coldfire/m527x.c
81
mcf_write8(par, MCFGPIO_PAR_FECI2C);
arch/m68k/coldfire/m528x.c
102
mcf_write8(0, 0x30000007);
arch/m68k/coldfire/m528x.c
103
mcf_write8(0x2, 0x30000007);
arch/m68k/coldfire/m528x.c
116
mcf_write8(mcf_read8(MCFGPIO_PDDR_E) | (1 << 5), MCFGPIO_PDDR_E);
arch/m68k/coldfire/m528x.c
119
mcf_write8(mcf_read8(MCFGPIO_PODR_E) & ~(1 << 5), MCFGPIO_PODR_E);
arch/m68k/coldfire/m528x.c
120
mcf_write8(mcf_read8(MCFGPIO_PODR_E) | (1 << 5), MCFGPIO_PODR_E);
arch/m68k/coldfire/m528x.c
54
mcf_write8(0x07, MCFGPIO_PQSPAR);
arch/m68k/coldfire/m528x.c
82
mcf_write8(port, MCFGPIO_PUAPAR);
arch/m68k/coldfire/m528x.c
94
mcf_write8(0xc0, MCFGPIO_PEHLPAR);
arch/m68k/coldfire/m5307.c
52
mcf_write8(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
arch/m68k/coldfire/m53xx.c
182
mcf_write8(r, MCFGPIO_PAR_FECI2C);
arch/m68k/coldfire/m53xx.c
204
mcf_write8(v, MCFGPIO_PAR_FECI2C);
arch/m68k/coldfire/m53xx.c
208
mcf_write8(v, MCFGPIO_PAR_FEC);
arch/m68k/coldfire/m53xx.c
335
mcf_write8(0x3E, MCFGPIO_PAR_CS);
arch/m68k/coldfire/m53xx.c
465
mcf_write8(0x00, MCFGPIO_PAR_TIMER);
arch/m68k/coldfire/m53xx.c
466
mcf_write8(0x08, MCFGPIO_PDDR_TIMER);
arch/m68k/coldfire/m53xx.c
467
mcf_write8(0x00, MCFGPIO_PCLRR_TIMER);
arch/m68k/coldfire/m53xx.c
519
mcf_write8(MCF_PLL_PODR_CPUDIV(BUSDIV/3) | MCF_PLL_PODR_BUSDIV(BUSDIV),
arch/m68k/coldfire/m53xx.c
522
mcf_write8(mfd, MCF_PLL_PFDR);
arch/m68k/coldfire/m5407.c
43
mcf_write8(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
arch/m68k/coldfire/m5441x.c
235
mcf_write8(0x0f, MCFGPIO_PAR_UART0);
arch/m68k/coldfire/m5441x.c
236
mcf_write8(0x00, MCFGPIO_PAR_UART1);
arch/m68k/coldfire/m5441x.c
237
mcf_write8(0x00, MCFGPIO_PAR_UART2);
arch/m68k/coldfire/m5441x.c
242
mcf_write8(0x03, MCFGPIO_PAR_FEC);
arch/m68k/coldfire/m54xx.c
54
mcf_write8(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC0);
arch/m68k/coldfire/m54xx.c
55
mcf_write8(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS,
arch/m68k/coldfire/m54xx.c
57
mcf_write8(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS |
arch/m68k/coldfire/m54xx.c
59
mcf_write8(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC3);
arch/m68k/coldfire/pci.c
109
mcf_write8(value, addr);
arch/m68k/coldfire/reset.c
30
mcf_write8(0xc0, MCFSIM_SYPCR);
arch/m68k/coldfire/reset.c
40
mcf_write8(MCF_RCR_SWRESET, MCF_RCR);
arch/m68k/coldfire/stmark2.c
119
mcf_write8(0x80, MCFGPIO_PAR_DSPIOWL);
arch/m68k/coldfire/stmark2.c
120
mcf_write8(0xfc, MCFGPIO_PAR_DSPIOWH);
arch/m68k/coldfire/stmark2.c
123
mcf_write8(0x00, MCFGPIO_PAR_BE);
arch/m68k/coldfire/stmark2.c
124
mcf_write8(0x00, MCFGPIO_PAR_FBCTL);
arch/m68k/coldfire/stmark2.c
125
mcf_write8(0x00, MCFGPIO_PAR_CS);
arch/m68k/coldfire/stmark2.c
128
mcf_write8(0x50, MCFGPIO_PAR_CANI2C);
arch/m68k/coldfire/timers.c
161
mcf_write8(MCFTIMER_TER_CAP | MCFTIMER_TER_REF, PA(MCFTIMER_TER));
arch/m68k/coldfire/timers.c
57
mcf_write8(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
arch/m68k/coldfire/timers.c
63
mcf_write8(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
arch/m68k/coldfire/timers.c
75
mcf_write8(MCFTIMER_TER_CAP | MCFTIMER_TER_REF, TA(MCFTIMER_TER));
arch/m68k/include/asm/mcfgpio.h
99
#define mcfgpio_write(data, port) mcf_write8(data, port)