mcf_read32
return mcf_read32(DTCN0);
unsigned long cycl = mcf_read32(DTCN0);
val = mcf_read32(imraddr);
val = mcf_read32(imraddr);
imr = mcf_read32(MCFSIM2_GPIOINTENABLE);
imr = mcf_read32(MCFSIM2_GPIOINTENABLE);
u32 imr = mcf_read32(MCFSIM2_GPIOINTENABLE);
u32 imr = mcf_read32(MCFSIM2_GPIOINTENABLE);
v = mcf_read32(intc_irqmap[irq].icr);
v = mcf_read32(MCFSIM_PITR);
imr = mcf_read32(MCFSIM_IMR);
imr = mcf_read32(MCFSIM_IMR);
imr = mcf_read32(MCFSIM_IMR);
gpio = mcf_read32(MCFSIM2_GPIOINTENABLE);
gpio = mcf_read32(MCFINTC2_INTPRI5);
r = mcf_read32(MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
u32 f = mcf_read32(MCFSIM2_GPIOFUNC);
r = mcf_read32(MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
v = mcf_read32(MCFSIM_PBCNT);
v = mcf_read32(MCFSIM_PDCNT);
if (!(mcf_read32(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)) {
mcf_write32(mcf_read32(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IPALL, MCF_SDRAMC_SDCR);
mcf_write32(mcf_read32(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IREF, MCF_SDRAMC_SDCR);
mcf_write32(mcf_read32(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IREF, MCF_SDRAMC_SDCR);
mcf_write32(mcf_read32(MCF_SDRAMC_SDCR) & ~MCF_SDRAMC_SDCR_MODE_EN,
if (mcf_read32(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)
mcf_write32(mcf_read32(MCF_SDRAMC_SDCR) & ~MCF_SDRAMC_SDCR_CKE,
if (mcf_read32(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)
mcf_write32(mcf_read32(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_CKE,
mcf_write32(mcf_read32(MCFSDHC_CLK) | (1 << clk->slot), MCFSDHC_CLK);
mcf_write32(mcf_read32(MCFSDHC_CLK) & ~(1 << clk->slot), MCFSDHC_CLK);
r = mcf_read32(MCF_PAR_FECI2CIRQ);
mcf_read32(PCICAR);
mcf_read32(PCICAR);
mcf_read32(PCICAR);
*value = le32_to_cpu(mcf_read32(addr));
mcf_read32(PCICAR);
scnt = mcf_read32(TA(MCFSLT_SCNT));
if (mcf_read32(TA(MCFSLT_SSR)) & MCFSLT_SSR_TE) {
scnt = mcf_read32(TA(MCFSLT_SCNT));
#define mcf_readtrr mcf_read32
#define mcfgpio_read(port) mcf_read32(port)