misr
u32 misr, csr, ccr;
misr = readl_relaxed(ddata->base + STM32_DMA3_MISR);
if (!(misr & MISR_MIS(chan->id))) {
u32 misr, src;
misr = readl(priv->virtbase + I2C_MISR);
src = __ffs(misr);
checksum = misr(checksum, data[i]);
u32 misr;
if (dcmi->misr & IT_OVR) {
if (dcmi->misr & IT_ERR)
dcmi->misr & IT_FRAME) {
dcmi->misr = reg_read(dcmi->regs, DCMI_MIS);
u16 misr, status;
misr = ioread16(ioaddr + MIER);
iowrite16(misr, ioaddr + MIER);
misr &= ~(RX_INTS | TX_INTS);
iowrite16(misr, ioaddr + MIER);
int misr;
misr = phy_read(phydev, MII_DP83640_MISR);
if (misr < 0)
return misr;
misr |=
err = phy_write(phydev, MII_DP83640_MISR, misr);
misr = phy_read(phydev, MII_DP83640_MISR);
if (misr < 0)
return misr;
misr &=
err = phy_write(phydev, MII_DP83640_MISR, misr);
static void msm_handle_rx_dm(struct uart_port *port, unsigned int misr)
if (misr & MSM_UART_IMR_RXSTALE) {
if (misr & (MSM_UART_IMR_RXSTALE))
unsigned int misr;
misr = msm_read(port, MSM_UART_MISR);
if (misr & MSM_UART_IMR_RXBREAK_START) {
if (misr & (MSM_UART_IMR_RXLEV | MSM_UART_IMR_RXSTALE)) {
msm_handle_rx_dm(port, misr);
if (misr & MSM_UART_IMR_TXLEV)
if (misr & MSM_UART_IMR_DELTA_CTS)