mem_config
.config = mem_config,
mem_conf->mem_config.num_stations = cpu_to_le16(DEFAULT_NUM_STATIONS);
mem_conf->mem_config.rx_mem_block_num = 35;
mem_conf->mem_config.tx_min_mem_block_num = 64;
mem_conf->mem_config.num_tx_queues = MAX_TX_QUEUES;
mem_conf->mem_config.host_if_options = HOSTIF_PKT_RING;
mem_conf->mem_config.num_ssid_profiles = 1;
mem_conf->mem_config.debug_buffer_size =
struct wl1251_acx_memory mem_config;
phys_addr_t addr = hbus->mem_config->start + offset;
hv_pci_write_mmio(dev, hbus->mem_config->start, 4,
phys_addr_t addr = hbus->mem_config->start +
hv_pci_write_mmio(dev, hbus->mem_config->start, 4,
phys_addr_t addr = hbus->mem_config->start + offset;
hv_pci_write_mmio(dev, hbus->mem_config->start, 4,
ret = vmbus_allocate_mmio(&hbus->mem_config, hbus->hdev, 0, -1,
hbus->mem_config->flags |= IORESOURCE_BUSY;
vmbus_free_mmio(hbus->mem_config->start, PCI_CONFIG_MMIO_LENGTH);
d0_entry->mmio_base = hbus->mem_config->start;
hbus->cfg_addr = ioremap(hbus->mem_config->start,
struct resource *mem_config;
default_par->mem_config = pm2_RD(default_par, PM2R_MEM_CONFIG);
default_par->mem_config);
default_par->mem_config == 0x259fffff) {
default_par->mem_config = 0xe6002021;
switch (default_par->mem_config & PM2F_MEM_CONFIG_RAM_MASK) {
pm2_WR(p, PM2R_MEM_CONFIG, p->mem_config);
u32 mem_config; /* MemConfig reg at probe */