mbox_read_reg
return mbox_read_reg(mbox->parent, fifo->msg);
return (mbox_read_reg(mbox->parent, fifo->msg_stat) == 0);
return mbox_read_reg(mbox->parent, fifo->fifo_stat);
mbox_read_reg(mbox->parent, irqstatus);
u32 enable = mbox_read_reg(mbox->parent, irqenable);
u32 status = mbox_read_reg(mbox->parent, irqstatus);
l = mbox_read_reg(mbox->parent, irqenable);
bit = mbox_read_reg(mbox->parent, irqdisable) & ~bit;
if (mbox_read_reg(mdev, MAILBOX_MSGSTATUS(fifo))) {
mdev->irq_ctx[usr] = mbox_read_reg(mdev, reg);
l = mbox_read_reg(mdev, MAILBOX_REVISION);
mbox->mbox_read_reg = (u8 *)oct->mmio[0].hw_addr +
writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg);
mbox->mbox_read_reg =
writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg);
writeq(OCTEON_PFVFACK, mbox->mbox_read_reg);
writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg);
writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg);
writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg);
writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg);
writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg);
writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg);
msg.u64 = readq(mbox->mbox_read_reg);
mbox->mbox_read_reg);
void *mbox_read_reg;
mbox->mbox_read_reg = oct->mmio.hw_addr + CN93_VF_SDP_R_MBOX_PF_VF_DATA(q_no);
mbox->mbox_read_reg = oct->mmio.hw_addr + CNXK_VF_SDP_R_MBOX_PF_VF_DATA(q_no);
u8 __iomem *mbox_read_reg;
pf_vf_data = readq(mbox->mbox_read_reg);