drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1213

uint8_t max_lane_count;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1257

union max_lane_count max_ln_count;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1666

link->dpcd_caps.lttpr_caps.max_lane_count =

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

392

link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

393

link->dpcd_caps.lttpr_caps.max_lane_count <= 4);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

433

if (link->dpcd_caps.lttpr_caps.max_lane_count <= LANE_COUNT_DP_MAX)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

434

lttpr_max_lane_count = link->dpcd_caps.lttpr_caps.max_lane_count;

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

1401

video_info->max_lane_count = 0x04;

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

1405

video_info->max_lane_count = 0x04;

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

1415

&video_info->max_lane_count);

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

695

return analogix_dp_full_link_train(dp, dp->video_info.max_lane_count,

drivers/gpu/drm/bridge/analogix/analogix_dp_core.h

139

enum link_lane_count_type max_lane_count;

drivers/gpu/drm/bridge/ite-it6505.c

1673

it6505->max_lane_count);

drivers/gpu/drm/bridge/ite-it6505.c

3326

u32 *max_lane_count = &it6505->max_lane_count;

drivers/gpu/drm/bridge/ite-it6505.c

3353

*max_lane_count = len;

drivers/gpu/drm/bridge/ite-it6505.c

3355

*max_lane_count = MAX_LANE_COUNT;

drivers/gpu/drm/bridge/ite-it6505.c

3359

*max_lane_count = MAX_LANE_COUNT;

drivers/gpu/drm/bridge/ite-it6505.c

3390

it6505->afe_setting, it6505->max_lane_count);

drivers/gpu/drm/bridge/ite-it6505.c

465

u32 max_lane_count;

drivers/gpu/drm/bridge/parade-ps8622.c

178

err = ps8622_set(cl, 0x01, 0x02, 0x80 | ps8622->max_lane_count);

drivers/gpu/drm/bridge/parade-ps8622.c

488

ps8622->max_lane_count = id->driver_data;

drivers/gpu/drm/bridge/parade-ps8622.c

492

ps8622->lane_count = ps8622->max_lane_count;

drivers/gpu/drm/bridge/parade-ps8622.c

493

} else if (ps8622->lane_count > ps8622->max_lane_count) {

drivers/gpu/drm/bridge/parade-ps8622.c

496

ps8622->lane_count = ps8622->max_lane_count;

drivers/gpu/drm/bridge/parade-ps8622.c

52

u32 max_lane_count;

drivers/gpu/drm/gma500/cdv_intel_dp.c

325

int max_lane_count = 4;

drivers/gpu/drm/gma500/cdv_intel_dp.c

328

max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;

drivers/gpu/drm/gma500/cdv_intel_dp.c

329

switch (max_lane_count) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

333

max_lane_count = 4;

drivers/gpu/drm/gma500/cdv_intel_dp.c

336

return max_lane_count;

drivers/gpu/drm/gma500/cdv_intel_dp.c

898

int max_lane_count = cdv_intel_dp_max_lane_count(intel_encoder);

drivers/gpu/drm/gma500/cdv_intel_dp.c

910

for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

928

intel_dp->lane_count = max_lane_count;

drivers/gpu/drm/i915/display/intel_display_types.h

1832

int max_lane_count;

drivers/gpu/drm/i915/display/intel_dp.c

1779

lane_count <= limits->max_lane_count;

drivers/gpu/drm/i915/display/intel_dp.c

2007

lane_count <= limits->max_lane_count;

drivers/gpu/drm/i915/display/intel_dp.c

2232

pipe_config->lane_count = limits->max_lane_count;

drivers/gpu/drm/i915/display/intel_dp.c

2620

limits->max_lane_count,

drivers/gpu/drm/i915/display/intel_dp.c

2682

limits->max_lane_count = intel_dp_max_lane_count(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

2728

limits->min_lane_count = limits->max_lane_count;

drivers/gpu/drm/i915/display/intel_dp.c

3294

int max_lane_count = 4;

drivers/gpu/drm/i915/display/intel_dp.c

3324

hactive_sym_cycles = drm_dp_link_symbol_cycles(max_lane_count,

drivers/gpu/drm/i915/display/intel_dp.c

3498

intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

406

lane_count = intel_dp->link.max_lane_count;

drivers/gpu/drm/i915/display/intel_dp.h

29

int min_lane_count, max_lane_count;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1337

intel_dp->link.max_lane_count = new_lane_count;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1961

*val = intel_dp->link.max_lane_count;

drivers/gpu/drm/i915/display/intel_dp_mst.c

446

crtc_state->lane_count = limits->max_lane_count;

drivers/gpu/drm/i915/display/intel_dp_mst.c

473

crtc_state->lane_count = limits->max_lane_count;

drivers/gpu/drm/i915/display/intel_dp_test.c

65

limits->max_lane_count = intel_dp->compliance.test_lane_count;

drivers/gpu/drm/i915/display/intel_tc.c

1186

if (tc->max_lane_count == 0)

drivers/gpu/drm/i915/display/intel_tc.c

1187

tc->max_lane_count = 4;

drivers/gpu/drm/i915/display/intel_tc.c

1536

tc->max_lane_count);

drivers/gpu/drm/i915/display/intel_tc.c

1695

tc->max_lane_count);

drivers/gpu/drm/i915/display/intel_tc.c

1709

tc->max_lane_count);

drivers/gpu/drm/i915/display/intel_tc.c

398

tc->max_lane_count = get_max_lane_count(tc);

drivers/gpu/drm/i915/display/intel_tc.c

408

return tc->max_lane_count;

drivers/gpu/drm/i915/display/intel_tc.c

68

u8 max_lane_count;