CLK_OPS_PARENT_ENABLE
if (core->flags & CLK_OPS_PARENT_ENABLE)
if (core->flags & CLK_OPS_PARENT_ENABLE)
if (core->flags & CLK_OPS_PARENT_ENABLE) {
if (core->flags & CLK_OPS_PARENT_ENABLE) {
if (core->flags & CLK_OPS_PARENT_ENABLE)
if (core->flags & CLK_OPS_PARENT_ENABLE)
if ((core->flags & CLK_OPS_PARENT_ENABLE) && core->parent)
ENTRY(CLK_OPS_PARENT_ENABLE),
init.flags = flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE;
hws[IMX7D_IPG_ROOT_CLK] = imx_clk_hw_divider_flags("ipg_root_clk", "ahb_root_clk", base + 0x9080, 0, 2, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_PARENT);
hws[IMX7D_ARM_A7_ROOT_CLK] = imx_clk_hw_gate2_flags("arm_a7_root_clk", "arm_a7_div", base + 0x4000, 0, CLK_OPS_PARENT_ENABLE);
hws[IMX7D_MAIN_AXI_ROOT_CLK] = imx_clk_hw_gate2_flags("main_axi_root_clk", "axi_post_div", base + 0x4040, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE);
hws[IMX7D_DRAM_ROOT_CLK] = imx_clk_hw_gate2_flags("dram_root_clk", "dram_post_div", base + 0x4130, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE);
hws[IMX7D_DRAM_PHYM_ROOT_CLK] = imx_clk_hw_gate2_flags("dram_phym_root_clk", "dram_phym_cg", base + 0x4130, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE);
hws[IMX7D_DRAM_PHYM_ALT_ROOT_CLK] = imx_clk_hw_gate2_flags("dram_phym_alt_root_clk", "dram_phym_alt_post_div", base + 0x4130, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE);
hws[IMX7D_DRAM_ALT_ROOT_CLK] = imx_clk_hw_gate2_flags("dram_alt_root_clk", "dram_alt_post_div", base + 0x4130, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE);
hws[IMX7ULP_CLK_DDR_SEL] = imx_clk_hw_mux_flags("ddr_sel", base + 0x30, 24, 2, ddr_sels, ARRAY_SIZE(ddr_sels), CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);
hws[IMX8MQ_CLK_VPU_G1_ROOT] = imx_clk_hw_gate2_flags("vpu_g1_root_clk", "vpu_g1", base + 0x4560, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);
hws[IMX8MQ_CLK_VPU_G2_ROOT] = imx_clk_hw_gate2_flags("vpu_g2_root_clk", "vpu_g2", base + 0x45a0, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);
hws[IMX8MQ_CLK_VPU_DEC_ROOT] = imx_clk_hw_gate2_flags("vpu_dec_root_clk", "vpu_bus", base + 0x4630, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);
__imx_clk_hw_gate2(name, parent, reg, shift, 0x3, CLK_OPS_PARENT_ENABLE, shared_count)
__imx_clk_hw_gate(name, parent, reg, shift, flags | CLK_OPS_PARENT_ENABLE, 0)
imx_clk_hw_gate2_flags(name, parent, reg, shift, flags | CLK_OPS_PARENT_ENABLE)
__imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, flags | CLK_OPS_PARENT_ENABLE, 0)
CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE)
(CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
&mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE)
&mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE)
&mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE)
.flags = CLK_OPS_PARENT_ENABLE, \
.flags = CLK_OPS_PARENT_ENABLE \
.flags = CLK_OPS_PARENT_ENABLE, \
.flags = CLK_OPS_PARENT_ENABLE, \
.flags = CLK_OPS_PARENT_ENABLE, \
.flags = CLK_OPS_PARENT_ENABLE, \
.flags = CLK_OPS_PARENT_ENABLE, \
.flags = CLK_OPS_PARENT_ENABLE, \
.flags = CLK_OPS_PARENT_ENABLE, \
.flags = CLK_OPS_PARENT_ENABLE, \
.flags = CLK_OPS_PARENT_ENABLE, \
.flags = CLK_OPS_PARENT_ENABLE, \
.flags = CLK_OPS_PARENT_ENABLE, \
.flags = CLK_OPS_PARENT_ENABLE, \
.flags = CLK_OPS_PARENT_ENABLE, \
.flags = CLK_OPS_PARENT_ENABLE, \
.flags = CLK_OPS_PARENT_ENABLE, \
.flags = CLK_OPS_PARENT_ENABLE \
.flags = CLK_OPS_PARENT_ENABLE, \
.flags = CLK_OPS_PARENT_ENABLE | \
.flags = CLK_OPS_PARENT_ENABLE, \
.flags = CLK_OPS_PARENT_ENABLE, \
.flags = CLK_OPS_PARENT_ENABLE | \
.flags = CLK_OPS_PARENT_ENABLE | \
.flags = CLK_OPS_PARENT_ENABLE, \
.flags = CLK_OPS_PARENT_ENABLE, \
.flags = CLK_OPS_PARENT_ENABLE, \
.flags = CLK_OPS_PARENT_ENABLE \
.flags = CLK_OPS_PARENT_ENABLE, \
.flags = CLK_OPS_PARENT_ENABLE, \
.flags = CLK_OPS_PARENT_ENABLE, \
CLK_OPS_PARENT_ENABLE, \
.flags = CLK_OPS_PARENT_ENABLE \
init.flags |= CLK_OPS_PARENT_ENABLE;
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE | CLK_GET_RATE_NOCACHE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE | CLK_GET_RATE_NOCACHE,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE | CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE | CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.flags = CLK_OPS_PARENT_ENABLE,
.flags = CLK_OPS_PARENT_ENABLE,
.flags = CLK_OPS_PARENT_ENABLE,
.flags = CLK_OPS_PARENT_ENABLE,
.flags = CLK_OPS_PARENT_ENABLE,
.flags = CLK_OPS_PARENT_ENABLE,
.flags = CLK_OPS_PARENT_ENABLE,
.flags = CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.flags = CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.flags = CLK_OPS_PARENT_ENABLE,
.flags = CLK_OPS_PARENT_ENABLE,
.flags = CLK_OPS_PARENT_ENABLE,
.flags = CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.flags = CLK_OPS_PARENT_ENABLE,
MUX(CLK_NPU_PRE_NDFT, "clk_npu_pre_ndft", clk_npu_pre_ndft_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
COMPOSITE(_id, _name, _parents, CLK_OPS_PARENT_ENABLE |\
MUX(CK_PER, "ck_per", per_src, CLK_OPS_PARENT_ENABLE,
MUX(CK_MPU, "ck_mpu", cpu_src, CLK_OPS_PARENT_ENABLE |
CLK_OPS_PARENT_ENABLE,
CLK_OPS_PARENT_ENABLE,
COMPOSITE(NO_ID, "ck_ker_eth", eth_src, CLK_OPS_PARENT_ENABLE |
DIV(ETHPTP_K, "ethptp_k", "ck_ker_eth", CLK_OPS_PARENT_ENABLE |
COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE,
COMPOSITE(CK_MCO1, "ck_mco1", mco1_src, CLK_OPS_PARENT_ENABLE |
COMPOSITE(CK_MCO2, "ck_mco2", mco2_src, CLK_OPS_PARENT_ENABLE |
COMPOSITE(CK_TRACE, "ck_trace", ck_trace_src, CLK_OPS_PARENT_ENABLE,
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT |
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT |
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE);