ltq_w32
#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y))
#define ltq_sys1_w32(x, y) ltq_w32((x), ltq_sys1_membase + (y))
ltq_w32((ltq_r32(reg) & ~(clear)) | (set), reg)
#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y))
#define ltq_cgu_w32(x, y) ltq_w32((x), ltq_cgu_membase + (y))
ltq_w32((unsigned long)&nmi_handler, (void *)BOOT_NVEC);
ltq_w32((unsigned long)&ejtag_debug_handler, (void *)BOOT_EVEC);
ltq_w32(BOOT_PW1, (void *)BOOT_PW1_REG); /* 'LTQ\0' */
ltq_w32(BOOT_PW2, (void *)BOOT_PW2_REG); /* '\0QTL' */
ltq_w32(0, (void *)BOOT_REG_BASE); /* reset Bootreg RVEC */
ltq_w32(WDT_PW1, (void *)WDT_REG_BASE);
ltq_w32(WDT_PW2 |
#define sysctl_w32(m, x, y) ltq_w32((x), sysctl_membase[m] + (y))
#define status_w32(x, y) ltq_w32((x), status_membase + (y))
ltq_w32((x), ltq_icu_membase[vpe] + m*LTQ_ICU_IM_SIZE + (y))
#define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y))
#define ltq_dma_w32(x, y) ltq_w32(x, ltq_dma_membase + (y))
#define gptu_w32(x, y) ltq_w32((x), gptu_membase + (y))
#define pmu_w32(x, y) ltq_w32((x), pmu_membase + (y))
ltq_w32(swab32(*data), ((u32 *)cfg_base));
ltq_w32(temp, ((u32 *)cfg_base));
#define ltq_pci_w32(x, y) ltq_w32((x), ltq_pci_membase + (y))
#define ltq_pci_cfg_w32(x, y) ltq_w32((x), ltq_pci_mapped_cfg + (y))
#define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y))
#define pad_w32(p, val, reg) ltq_w32(val, p + reg)