lo_hi_writeq
lo_hi_writeq(reg_value, chip->apb_regs + DMAC_APB_HW_HS_SEL_0);
lo_hi_writeq(value, idma64c->regs + offset);
lo_hi_writeq(val, priv->regs + LDMA_ORDER_ERG);
lo_hi_writeq(0, priv->regs + LDMA_ORDER_ERG);
lo_hi_writeq(val, priv->regs + LDMA_ORDER_ERG);
lo_hi_writeq(value, chan->xdev->regs + chan->ctrl_offset + reg);
lo_hi_writeq(value, chan->regs + reg);
lo_hi_writeq(addr, lpss->priv + LPSS_PRIV_REMAP_ADDR);
lo_hi_writeq(value, hw->mmio + reg);
lo_hi_writeq(val, addr);
lo_hi_writeq(val, addr);
lo_hi_writeq(value, priv->io_base + addr);
lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
lo_hi_writeq(val, cspmu->base1 + offset);
lo_hi_writeq(val, regs);
lo_hi_writeq(dbc->ctx->dma, &dbc->regs->dccp);
lo_hi_writeq(dbc->erst.erst_dma_addr, &dbc->regs->erstba);
lo_hi_writeq(deq, &dbc->regs->erdp);
lo_hi_writeq(deq, &dbc->regs->erdp);
lo_hi_writeq(val, regs);
lo_hi_writeq(val, gwdt->control_base + SBSA_GWDT_WOR);
#define writeq lo_hi_writeq