lan_rd
lan_rd(lan966x, SYS_CNT(offset)));
mask = lan_rd(lan966x, FDMA_INTR_DB_ENA);
mask = lan_rd(lan966x, FDMA_INTR_DB_ENA);
return lan_rd(lan966x, FDMA_CH_ACTIVE);
db = lan_rd(lan966x, FDMA_INTR_DB);
err = lan_rd(lan966x, FDMA_INTR_ERR);
err_type = lan_rd(lan966x, FDMA_ERRORS);
mtu = lan_rd(lan966x, DEV_MAC_MAXLEN_CFG(port->chip_port));
return lan_rd(lan966x, QSYS_SW_STATUS(CPU_PORT));
ac = lan_rd(lan966x, ANA_PGID(i));
return ANA_MACACCESS_VALID_GET(lan_rd(lan966x, ANA_MACACCESS));
return lan_rd(lan966x, ANA_MACACCESS);
val = lan_rd(lan966x, ANA_MACTINDX);
entry[column].mach = lan_rd(lan966x, ANA_MACHDATA);
entry[column].macl = lan_rd(lan966x, ANA_MACLDATA);
entry[column].maca = lan_rd(lan966x, ANA_MACACCESS);
return lan_rd(lan966x, SYS_RAM_INIT);
if (lan_rd(lan966x, SYS_RESET_CFG) & SYS_RESET_CFG_CORE_ENA)
return lan_rd(lan966x, QS_INJ_STATUS);
if (lan_rd(lan966x, QS_INJ_STATUS) & QS_INJ_STATUS_FIFO_RDY_SET(BIT(grp)))
val = lan_rd(lan966x, QS_INJ_STATUS);
val = lan_rd(lan966x, ANA_CPU_FWD_CFG(port));
return lan_rd(lan966x, QS_XTR_RD(grp));
val = lan_rd(lan966x, QS_XTR_RD(grp));
val = lan_rd(lan966x, QS_XTR_RD(grp));
*rval = lan_rd(lan966x, QS_XTR_RD(grp));
*rval = lan_rd(lan966x, QS_XTR_RD(grp));
if (!(lan_rd(lan966x, QS_XTR_DATA_PRESENT) & BIT(grp)))
lan_rd(lan966x, QS_XTR_RD(grp));
} while (lan_rd(lan966x, QS_XTR_DATA_PRESENT) & BIT(grp));
lan_wr(lan_rd(lan966x, QS_XTR_FLUSH) |
lan_wr(lan_rd(lan966x, QS_XTR_FLUSH) &
val = lan_rd(lan966x, QSYS_SW_STATUS(port->chip_port));
val = lan_rd(lan966x, DEV_PCS1G_STICKY(port->chip_port));
val = lan_rd(lan966x, DEV_PCS1G_LINK_STATUS(port->chip_port));
val = lan_rd(lan966x, DEV_PCS1G_ANEG_STATUS(port->chip_port));
val = lan_rd(lan966x, AFI_PORT_FRM_OUT(port->chip_port));
ts->tv_sec = lan_rd(lan966x, PTP_TOD_SEC_LSB(TOD_ACC_PIN));
curr_nsec = lan_rd(lan966x, PTP_TOD_NSEC(TOD_ACC_PIN));
val = lan_rd(lan966x, PTP_TWOSTEP_CTRL);
delay = lan_rd(lan966x, PTP_TWOSTEP_STAMP);
val = lan_rd(lan966x, PTP_TWOSTEP_CTRL);
id = lan_rd(lan966x, PTP_TWOSTEP_STAMP);
if (!(lan_rd(lan966x, PTP_PIN_INTR)))
if (!(lan_rd(lan966x, PTP_PIN_INTR) & BIT(pin)))
s = lan_rd(lan966x, PTP_TOD_SEC_MSB(pin));
s |= lan_rd(lan966x, PTP_TOD_SEC_LSB(pin));
ns = lan_rd(lan966x, PTP_TOD_NSEC(pin));
s = lan_rd(lan966x, PTP_TOD_SEC_MSB(TOD_ACC_PIN));
s |= lan_rd(lan966x, PTP_TOD_SEC_LSB(TOD_ACC_PIN));
ns = lan_rd(lan966x, PTP_TOD_NSEC(TOD_ACC_PIN));
val = lan_rd(lan966x, PTP_PIN_INTR_ENA);
flood_mask_ip = lan_rd(lan966x, ANA_PGID(pgid_ip));
flood_mask = lan_rd(lan966x, ANA_PGID(PGID_MC));
u32 val = lan_rd(port->lan966x, ANA_PGID(PGID_MC));
u32 val = lan_rd(port->lan966x, ANA_PGID(PGID_UC));
u32 val = lan_rd(port->lan966x, ANA_PGID(PGID_BC));
base = lan_rd(lan966x, QSYS_TAS_LIST_CFG);
next = lan_rd(lan966x, QSYS_TAS_GCL_CT_CFG2);
val = lan_rd(lan966x, QSYS_TAS_LST);
val = lan_rd(lan966x, ANA_VCAP_S2_CFG(port->chip_port));
val = lan_rd(lan966x, ANA_VCAP_CFG(port->chip_port));
val = lan_rd(lan966x, REW_PORT_CFG(port->chip_port));
val = lan_rd(lan966x, ANA_VCAP_S1_CFG(port->chip_port, l));
val = lan_rd(lan966x, ANA_VCAP_S1_CFG(port->chip_port, lookup));
val = lan_rd(lan966x, ANA_VCAP_S2_CFG(port->chip_port));
counter = lan_rd(lan966x, SYS_CNT(LAN966X_STAT_ESDX_GRN_PKTS)) +
lan_rd(lan966x, SYS_CNT(LAN966X_STAT_ESDX_YEL_PKTS));
lan_rd(lan966x, VCAP_ENTRY_DAT(instance, i));
~lan_rd(lan966x, VCAP_MASK_DAT(instance, i));
lan_rd(lan966x, VCAP_ACTION_DAT(instance, i));
lan_rd(lan966x, VCAP_CNT_DAT(instance, 0));
return lan_rd(cb->lan966x, VCAP_UPDATE_CTRL(cb->instance));
return lan_rd(lan966x, ANA_VLANACCESS);