ADDR_MASK
((unsigned int)(JAL | (((addr) >> 2) & ADDR_MASK)))
u8 addr = (amsg->cmd & ADDR_MASK) >> 4;
poll_addr = (last_poll_cmd & ADDR_MASK) >> 4;
tx_buf[0] = op | (addr & ADDR_MASK);
priv->spi_transfer_buf[0] = op | (addr & ADDR_MASK);
u8 banked_reg = reg & ADDR_MASK;
u8 banked_reg = reg & ADDR_MASK;
#define RCR(addr) (RCRCODE | (addr & ADDR_MASK)) /* Read Control Register */
#define WCR(addr) (WCRCODE | (addr & ADDR_MASK)) /* Write Control Register */
#define BFS(addr) (BFSCODE | (addr & ADDR_MASK)) /* Bit Field Set */
#define BFC(addr) (BFCCODE | (addr & ADDR_MASK)) /* Bit Field Clear */
u32 ADDR_MASK;
adrmask = ioread32(&hw->reg->ADDR_MASK);
iowrite32(adrmask | BIT(i), &hw->reg->ADDR_MASK);
pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
adrmask = ioread32(&hw->reg->ADDR_MASK);
iowrite32((adrmask | (0x0001 << index)), &hw->reg->ADDR_MASK);
pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
iowrite32((adrmask & ~(0x0001 << index)), &hw->reg->ADDR_MASK);
pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
iowrite32(0xFFFE, &hw->reg->ADDR_MASK);
pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
wu_evt, ioread32(&hw->reg->ADDR_MASK));
addr_mask = ioread32(&hw->reg->ADDR_MASK);